MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR <Dual-In-Line <Dual-In-Line Package Package Intelligent Intelligent Power Power Module> Module> PS21267-P/AP PS21267-P/AP TRANSFER-MOLD TRANSFER-MOLD TYPE TYPE INSULATED INSULATED TYPE TYPE PS21267 INTEGRATED POWER FUNCTIONS 600V/30A low-loss CSTBTTM inverter bridge for three phase DC-to-AC power conversion INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • • • • • For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply). Input interface : 3, 5V line compatible. (High Active) UL Approved : Yellow Card No. E80276 APPLICATION AC100V~200V three-phase inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES (Short-pin type : PS21267-P) Refer Fig. 6 for long-pin type : PS21267-AP. Dimensions in mm NOTE 27×2.8(=75.6) TERMINAL CODE D 2.8±0.3 10 11 12 13 14 15 16 17 18 19 20 21 2-φ4.5 22 23 10 ±0.3 24 10 ±0.3 25 10 ±0.3 13.4±0.5 11.5±0.5 Type name , Lot No. ±0.2 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. VN1 VNC CIN CFO FO UN VN WN P U V W N A 26 3.8±0.2 20 ±0.3 1±0.2 8±0.5 C 1±0.2 0.7±0.2 0.7±0.2 C0 .2 2 0. C 0.8±0.2 0.6±0.5 79±0.5 Irregular solder remains 0.5MAX 67±0.3 B 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. UP VP1 VUFB VUFS VP VP1 VVFB VVFS WP VP1 VPC VWFB VWFS 0.8±0.2 0.45±0.2 0.8±0.2 0.45±0.2 0.45±0.2 0.6±0.5 9 Irregular solder remains 0.5MAX 8 (11.5) 7 28±0.5 6 (8.5) 5 21.4±0.5 4 34.9±0.5 3 31±0.5 2 12.8±0.5 1 Heat sink side (2.5) (71) OTHERS 0.5±0.2 DETAIL A (0 ~ 5°) Heat sink side TERMINAL 22, 26 DETAIL B (5 pins t = 0.7) OTHERS TERMINAL 1-2, 20-21 DETAIL C (21 pins t = 0.7) DETAIL D Note: All outer lead terminals are with Pb-free solder plating. Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW– CBW+ CBU+ CBV+ CBV– CBU– High-side input (PWM) (3, 5V line) (Note 1, 2) C1 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system.) C2 : 0.22~2µF R-category ceramic capacitor for noise filtering C2 (Note 7) Input signal Input signal Input signal conditioning conditioning conditioning C1 Level shifter Level shifter Level shifter Protection circuit (UV) Protection circuit (UV) (Note 6) Protection circuit (UV) DIP-IPM Drive circuit Drive circuit Drive circuit Inrush current limiter circuit P AC line input H-side IGBTS U V (Note 4) M W C AC line output Z N1 VNC Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment.) N L-side IGBTS CIN Drive circuit Input signal conditioning Protection circuit Fo logic Control supply Under-Voltage protection FO CFO Low-side input (PWM) (3, 5V line) (Note 1, 2) Fault output (5V line) (Note 3, 5) Note1: 2: 3: 4: 5: 6: 7: (Note 7) VNC VD (15V line) The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. If using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement. By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor. The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P & N1 DC power input pins. Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.)) High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. To prevent ICS from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between each control supply terminals. Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT DIP-IPM Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. Drive circuit P IC (A) H-side IGBTS SC Protection Trip Level U V W L-side IGBTS External protection circuit Shunt Resistor N1 A N (Note 1) VNC C R Drive circuit CIN B C Note1: 2: Collector current waveform Protection circuit (Note 2) In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible. 0 2 tw (µs) Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Condition Applied between P-N Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Ratings 450 500 600 30 60 55.5 –20~+125 Applied between P-N TC = 25°C TC = 25°C, less than 1ms TC = 25°C, per 1 chip (Note 1) Unit V V V A A W °C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C) however, to insure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C). CONTROL (PROTECTION) PART Symbol Parameter Condition VD Control supply voltage VDB Control supply voltage VIN Input voltage VFO IFO VSC Fault output supply voltage Fault output current Current sensing input voltage Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Applied between UP, VP, WP-VPC, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings Unit 20 V 20 V –0.5~VD+0.5 V –0.5~VD+0.5 1 –0.5~VD+0.5 V mA V Ratings Unit 400 V –20~+100 –40~+125 °C 2500 Vrms TOTAL SYSTEM Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2 µs (Note 2) Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature TC Tstg Storage temperature Viso 60Hz, Sinusoidal, AC 1 minute, connecting pins to heat-sink plate Isolation voltage °C Note 2 : TC measurement point Control terminals Heat sink TC TC Heat sink boundary Power terminals Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f)F Condition Parameter Junction to case thermal resistance (Note 3) Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Contact thermal resistance Case to fin (per 1 module) thermal grease applied Min. — — Limits Typ. — — — — Max. Unit 1.80 °C/W 3.00 °C/W 0.067 °C/W Note 3 : Grease with good thermal conductivity should be applied evenly with a thickness of about +100µm~+200µm on the contact surface of DIP-IPM and heat-sink. ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Condition Parameter Collector-emitter saturation voltage FWDi forward voltage Switching times VD = VDB = 15V IC = 30A, Tj = 25°C VIN = 5V IC = 30A, Tj = 125°C Tj = 25°C, –IC = 30A, VIN = 0V VCC = 300V, VD = VDB = 15V IC = 30A, Tj = 125°C, VIN = 0 ↔ 5V Inductive load (upper-lower arm) Collector-emitter cut-off current VCE = VCES Tj = 25°C Tj = 125°C Min. — — — Limits Typ. 0.65 — — — — — — 1.50 1.50 1.50 1.25 0.30 0.30 1.70 0.40 — — Max. 2.00 2.00 2.00 1.85 — 0.50 2.40 0.70 1 10 Min. — — — — 4.9 — 0.45 1.0 10.0 10.5 10.3 10.8 1.0 2.1 0.8 Limits Typ. — — — — — — — 1.5 — — — — 1.8 2.3 1.4 Max. 7.00 0.55 7.00 0.55 — 0.95 0.52 2.0 12.0 12.5 12.5 13.0 — 2.6 2.1 Unit V V µs µs µs µs µs mA CONTROL (PROTECTION) PART Symbol ID Parameter Circuit current Condition VD = VDB = 15V Total of VP1-VPC, VN1-VNC VIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VD = VDB = 15V Total of VP1-VPC, VN1-VNC VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VSC = 0V, FO circuit pull-up to 5V with 10kΩ VSC = 1V, IFO = 1mA TC = –20~100°C, VD = 15V (Note 4) VIN = 5V Trip level Reset level Tj ≤ 125°C Trip level Reset level CFO = 22nF (Note 5) Unit mA mA mA mA V V V mA V V V V ms V V VFOH Fault output voltage VFOL Short circuit trip level VSC(ref) Input current IIN UVDBt Control supply under-voltage UVDBr protection UVDt UVDr Fault output pulse width tFO ON threshold voltage Vth(on) Applied between UP, VP, WP-VPC, UN, VN, WN-VNC OFF threshold voltage Vth(off) Note 4 : Short circuit protection is functioning only at the low-arms. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the collector current rating. 5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F]. Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Condition Parameter Mounting torque Weight Heat-sink flatness Note 6 : Mounting screw : M4 Recommended : 1.18 N·m (Note 6) Min. 0.98 — –50 Limits Typ. — 54 — Max. 1.47 — 100 Unit N·m g µm Measurement point 3mm + – Place to contact a heat sink Heat sink – + Heat sink RECOMMENDED OPERATION CONDITIONS Symbol Parameter VCC VD VDB ∆VD, ∆VDB tdead fPWM Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency IO Allowable r.m.s. current PWIN(on) PWIN(off) Minimum input pulse width Condition Applied between P-N Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS For each input signal, TC ≤ 100°C TC ≤ 100°C, Tj ≤ 125°C VCC = 300V, VD = VDB = 15V, fPWM = 5kHz P.F = 0.8, sinusoidal PWM fPWM = 15kHz TC ≤ 100°C, Tj ≤ 125°C (Note 7) (Note 8) 200 ≤ VCC ≤ 350V, Below rated current 13.5 ≤ VD ≤ 16.5V, 13.0 ≤ VDB ≤ 18.5V, Between rated current and 1.7 times of rated current –20°C ≤ TC ≤ 100°C, N-line wiring inductance less Between 1.7 times and than 10nH (Note 9) 2.0 times of rated current Recommended value Min. Typ. Max. Unit V V V V/µs µs kHz 0 13.5 13.0 –1 2 — 300 15.0 15.0 — — — 400 16.5 18.5 1 — 20 — — 19.0 — — 11.6 0.3 — — 1.5 — — 3.0 — — 3.6 — — Arms µs — VNC V –5.0 VNC variation between VNC-N (including surge) 5.0 Note 7 : The Allowable r.m.s. current value depends on the actual application conditions. 8 : Input signal with ON pulse width less than PWIN(on) might make no response. 9 : IPM might make no response or response delay to next turn-on pulse if off-pulse width is less than PWIN(off). (Please refer to Fig. 4) Please refer to Fig. 9 for recommended wiring method too. Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 4 CURRENT OUTPUT WHEN INPUT SIGNAL IS LESS THAN ALLOWABLE MINIMUM INPUT PULSE WIDTH PWIN(off) (P-side only) P-side control input Internal IGBT gate t2 Output current Ic t1 Real line ... off pulse width > PWIN(off) ; turn on time t1 Broken line ... off pulse width < PWIN(off) ; turn on time t2 Fig. 5 THE DIP-IPM INTERNAL CIRCUIT DIP-IPM VUFB VUFS VP1 UP P HVIC1 VB VCC IGBT1 Di1 HO IN VS COM U VVFB VVFS VP1 VP HVIC2 VB VCC IGBT2 Di2 HO IN VS COM V VWFB VWFS HVIC3 VP1 VCC WP IN VPC COM VB IGBT3 Di3 HO VS W IGBT4 LVIC Di4 UOUT VN1 VCC IGBT5 Di5 VOUT UN UN VN VN WN WN Fo Fo IGBT6 Di6 WOUT VNO CIN VNC GND N CFO CFO CIN Oct. 2005 2-φ4.5±0.2 1 2 DETAIL A 6 23 10±0.3 0.5±0.2 22 5 7 10 11 12 13 10±0.3 24 (71) B 79±0.5 67±0.3 10±0.3 25 14 26 16 17 18 19 Heat sink side 15 DETAIL D C 20±0.3 Type name , Lot No. 9 20 21 11.5±0.5 8±0.5 8 .2 C 0. 2 1±0.2 0.7±0.2 0.7±0.2 TERMINAL 22, 26 DETAIL B (5 pins t = 0.7) C0 28±0.5 35±0.6 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 0.8±0.2 0.45±0.2 0.8±0.2 0.45±0.2 0.45±0.2 VN1 VNC CIN CFO FO UN VN WN P U V W N TERMINAL 1-2, 20-21 DETAIL C (21 pins t = 0.7) 0.8±0.2 (0.6) UP VP1 VUFB VUFS VP VP1 VVFB VVFS WP VP1 VPC VWFB VWFS OTHERS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. TERMINAL CODE Note: All outer lead terminals are with Pb-free solder plating. OTHERS (2.5) 1±0.2 (0.7) A 3.8±0.2 Irregular solder remains 0.5MAX 4 31±0.5 16±0.5 (11.5) (8.5) 21.4±0.5 13.4±0.5 (1) Heat sink side 0.6±0.5 3 D (1) NOTE Irregular solder remains 0.5MAX 2.8±0.3 (0 ~ 5°) 0.6±0.5 27×2.8(=75.6) MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 6 PACKAGE OUTLINES (Long-pin type : PS21267-AP) Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 7 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only) (with external shunt resistor and CR connection) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input “L” : IGBT OFF state. a7. Input “H” : IGBT ON state, but during the FO signal active period the IGBT doesn’t turn ON. a8. IGBT OFF in spite of “H” input. Lower-arms control input a6 a7 Protection circuit state SET Internal IGBT gate RESET a3 a2 a1 SC a4 Output current Ic a8 SC reference voltage Sense voltage of the shunt resistance CR circuit time constant DELAY Error output Fo a5 [B] Under-Voltage Protection (Lower-arm, UVD) b1. Control supply voltage rises : After the voltage reaches UVDr level, the circuits start to operate when the next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT OFF in spite of control input condition. b5. FO operation starts. The minimum pulse width of FO is set by the external capacitor CFO, and FO outputs continuously during UV period. b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage VD RESET UVDr b1 SET UVDt b2 RESET b6 b3 b4 b7 Output current Ic Error output Fo b5 Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (Upper-arm, UVDB) c1. Control supply voltage rises : Operation starts soon after UVDBr. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UVDBt). c4. IGBT OFF in spite of control input condition, but there is no FO signal output. c5. Under voltage reset (UVDBr). c6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage VDB RESET SET RESET UVDBr c1 UVDBt c4 c2 c3 c5 c6 c7 Output current Ic High-level (no fault output) Error output Fo Fig. 8 RECOMMENDED MCU I/O INTERFACE CIRCUIT 5V line DIP-IPM 10kΩ UP,VP,WP,UN,VN,WN MCU Fo VNC(Logic) Note : RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s printed circuit board. The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, if using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement. Fig. 9 RECOMMENDED WIRING OF SHUNT RESISTOR DIP-IPM Wiring inductance should be less than 10nH. width=3mm, thickness=100µm, length=17mm in copper pattern (rough standard) VNC N Shunt resistor Please make the connection point as close as possible to the terminal of shunt resistor. Oct. 2005 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21267-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 10 EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUIT C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering. (Note: The capacitance value depends on the PWM control used in the applied system.) C2 VUFB C1 VUFS DIP-IPM P HVIC1 VP1 C3 UP C2 VVFB C1 VVFS VP1 C3 VCC VB IN HO COM VS U HVIC2 VCC VB IN HO COM VS VP C2 C1 M VWFS CONTROLLER HVIC3 VP1 C3 V VWFB VCC VB IN HO WP VPC COM W VS LVIC UOUT VN1 VCC C3 5V line VOUT UN VN WN Fo UN VN If this wiring is too long, short circuit might be caused. WOUT WN Fo VNO CIN VNC GND N CFO C CIN CFO 15V line C4(CFO ) A The long wiring of GND might generate noise on input and cause IGBT to be malfunction. B C5 R1 Shunt Resistor If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. N1 Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2-3cm) 2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open drain type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor. 4 : FO output pulse width is determined by the external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22nF → tFO = 1.8ms (typ.)) 5 : The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ (min) pull-down resistor. If using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement. 6 : To prevent malfunction of protection, the wiring of A, B, C should be as short as possible. 7 : Please set the R1C5 time constant in the range 1.5~2µs. 8 : Each capacitor should be located as nearby the pins of the DIP-IPM as possible. 9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P-N1 pins is recommended. 10 : To prevent ICS from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between each control supply terminals. Oct. 2005