MITSUBISHI PS21963-CT

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
PS21963-T
INTEGRATED POWER FUNCTIONS
600V/10A low-loss 5th generation IGBT inverter bridge for
three phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
•
•
•
•
•
For upper-leg IGBTS : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC), Over temperature protection (OT).
Fault signaling : Corresponding to an SC fault (Lower-leg IGBT), a UV fault (Lower-side supply) or an OT fault (LVIC temperature).
Input interface : 3V, 5V line (High Active).
UL Approved : Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES (PS21963-T)
Dimensions in mm
0.28
1.778 ±0.2
B
A
38 ±0.5
20×1.778(=35.56)
35 ±0.3
TERMINAL CODE
3.5
16-0.5
29.2 ±0.5
24 ±0.5
Type name
Lot No.
14.4 ±0.5
12
QR
Code
.6
R1
2-
3 MIN
18
(3.3)
(3.5)
1
14.4 ±0.5
17
(1)
0.4
1.5 ±0.05
0.8
HEAT SINK SIDE
25
4-C1.2
0.4
8-0.6
0.28
14×2.54 (=35.56)
2.5 MIN
1.5 M
0.5
HEAT SINK SIDE
9.5±0.5
(2.656)
5.5±0.5
0.5
0.5
(1.2)
IN
(1.2)
0.5
NC
VUFB
VVFB
VWFB
UP
VP
WP
VP1
VNC *
UN
VN
WN
VN1
FO
CIN
VNC *
NC
NC
NC
N
W
V
U
P
NC
(0~5°)
2.54 ±0.2
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
(2.756)
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Aug. 2007
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 LONG TERMINAL TYPE PACKAGE OUTLINES (PS21963-AT)
38
20×1.778(=35.56)
35 ±0.3
0.28
1.778 ±0.2
Dimensions in mm
B
A
±0.5
TERMINAL CODE
3.5
16-0.5
(3.5)
29.4 ±0.5
24 ±0.5
Type name
Lot No.
0.8
14.4 ±0.5
12
QR
Code
.6
R1
2-
(3.3)
1
14.4 ±0.5
17
(1)
0.4
1.5 ±0.05
3 MIN
HEAT SINK SIDE
25
8-0.6
4-C1.2
0.4
18
0.28
2.54 ±0.2
0.5
2.5 MIN
0.5
NC
VUFB
VVFB
VWFB
UP
VP
WP
VP1
VNC *
UN
VN
WN
VN1
FO
CIN
VNC *
NC
NC
NC
N
W
V
U
P
NC
(0~5°)
14×2.54 (=35.56)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
0.5
0.5
1.5 M
IN
(1.2)
(1.2)
5.5±0.5
14±0.5
(2.656)
(2.756)
HEAT SINK SIDE
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Dimensions in mm
Fig. 3 ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21963-CT)
38 ±0.5
20×1.778(=35.56)
35 ±0.3
0.28
1.778 ±0.2
B
A
TERMINAL CODE
3.5
1.5 ±0.05
0.4
Type name
Lot No.
3 MIN
18
0.8
HEAT SINK SIDE
0.4
25
8-0.6
0.28
(3.5)
14.4 ±0.5
29.2 ±0.5
33.7±0.5
24 ±0.5
QR
Code
.6
(0~5°)
R1
2-
14.4 ±0.5
12
18.9
±0.5
1
(1)
17
0.4
16-0.5
4-C1.2
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
NC
VUFB
VVFB
VWFB
UP
VP
WP
VP1
VNC *
UN
VN
WN
VN1
FO
CIN
VNC *
NC
NC
NC
N
W
V
U
P
NC
2.54 ±0.2
(0~5°)
14×2.54 (=35.56)
0.5
0.5
1.5 M
IN
9.5
5.5±0.5
(1.2)
(1.2)
(2.656)
±0.5
0.5
(2.756)
HEAT SINK SIDE
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Aug. 2007
2
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 4 BOTH SIDES ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21963-TW)
38
20×1.778(=35.56)
35 ±0.3
0.28
1.778 ±0.25
Dimensions in mm
B
A
±0.5
3.5
TERMINAL CODE
1.5 ±0.05
(1)
1
(3.5)
29.2 ±0.5
Type name
Lot No.
0.8
17.4 ±0.5
14.4 ±0.5
12
24 ±0.5
QR
Code
.6
R1
2-
35.2 ±0.6
17.4 ±0.5
14.4 ±0.5
0.4
17
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
0.4
16-0.5
3 MIN
HEAT SINK SIDE
(0~5°)
25
4-C1.2
0.4
7-0.6
14×2.54 (=35.56)
(0~5°)
(1.8)
0.4
18
0.28
2.54 ±0.25
2.5 MIN
0.5
1.5 M
0.5
0.5
NC
VUFB
VVFB
VWFB
UP
VP
WP
VP1
VNC *
UN
VN
WN
VN1
FO
CIN
VNC *
NC
NC
NC
N
W
V
U
P
NC
IN
(1.2)
(1.2)
5.5±0.5
11±0.5
(2.656)
(2.756)
HEAT SINK SIDE
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Fig. 5 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
Input signal
conditioning
Level shifter
Level shifter
Level shifter
Drive circuit
Drive circuit
CBW+
Input signal
conditioning
CBW–
CBV+
Input signal
conditioning
CBV–
CBU+
CBU–
High-side input (PWM)
(3V, 5V line)(Note 1, 2)
C1 : Electrolytic type with good temperature and frequency
characteristics
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
C2
C1
(Note 6)
(Note 5)
Protection
circuit (UV)
Inrush current
limiter circuit
Drive circuit
P
H-side IGBTS
DIP-IPM
AC line input
U
V
W
(Note 4)
M
(Note 7)
Z
C
N1
AC line output
N
L-side IGBTS
VNC
CIN
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
Drive circuit
Input signal conditioning
Fo logic
Protection Control supply
circuit
Under-Voltage
protection
Low-side input (PWM) FO
(3V, 5V line)(Note 1, 2) Fault output (5V line)
(Note 3)
Note1:
2:
3:
4:
5:
6:
7:
(Note 6)
VNC
(15V line)
VD
Input logic is high-active. There is a 3.3kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 11)
This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor.
(see also Fig. 11)
The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P & N1 DC power input pins.
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
Aug. 2007
3
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 6 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
Drive circuit
P
IC (A)
H-side IGBTS
SC Protection
Trip Level
U
V
W
L-side IGBTS
External protection circuit
N1
Shunt Resistor
A
N
(Note 1)
VNC
C R
Drive circuit
CIN
B
C
Collector current
waveform
Protection circuit
0
(Note 2)
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
2
tw (µs)
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Condition
Applied between P-N
Ratings
Applied between P-N
TC = 25°C
TC = 25°C, less than 1ms
TC = 25°C, per 1 chip
(Note 1)
450
500
600
10
20
27.0
–20~+125
Unit
V
V
V
A
A
W
°C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C). However, to
ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).
CONTROL (PROTECTION) PART
Symbol
VD
VDB
Parameter
Control supply voltage
Control supply voltage
VIN
Input voltage
VFO
IFO
VSC
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
Applied between UP, VP, WP, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Ratings
20
20
Unit
V
V
–0.5~VD+0.5
V
–0.5~VD+0.5
1
–0.5~VD+0.5
V
mA
V
Aug. 2007
4
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2µs
(Note 2)
Parameter
VCC(PROT) Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
TC
Tstg
Storage temperature
Viso
60Hz, Sinusoidal, 1 minute,
Between pins and heat-sink plate
Isolation voltage
Ratings
Unit
400
V
–20~+100
–40~+125
°C
°C
1500
Vrms
Note 2: TC measurement point
Control terminals
11.6mm
DIP-IPM
3mm
IGBT chip position
TC point
FWD chip position
Heat sink side
Power terminals
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Condition
Parameter
Junction to case thermal
resistance
(Note 3)
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
Min.
—
Limits
Typ.
—
Max.
3.7
°C/W
—
—
4.5
°C/W
Unit
Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal
conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and
the thermal conductivity is 1.0W/m·k.
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
Condition
Parameter
Collector-emitter saturation
voltage
FWD forward voltage
Switching times
IC = 10A, Tj = 25°C
VD = VDB = 15V
VIN = 5V
IC = 10A, Tj = 125°C
Tj = 25°C, –IC = 10A, VIN = 0V
VCC = 300V, VD = VDB = 15V
IC = 10A, Tj = 125°C, VIN = 0 ↔ 5V
Inductive load (upper-lower arm)
Collector-emitter cut-off
current
Tj = 25°C
VCE = VCES
Tj = 125°C
Min.
—
—
—
0.60
—
—
—
—
—
—
Limits
Typ.
1.70
1.80
1.70
1.10
0.30
0.40
1.50
0.50
—
—
Max.
2.20
2.30
2.20
1.70
—
0.60
2.10
0.80
1
10
Unit
V
V
µs
µs
µs
µs
µs
mA
Aug. 2007
5
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
CONTROL (PROTECTION) PART
Symbol
ID
VFOH
VFOL
VSC(ref)
IIN
OTt
OTrh
UVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
Vth(hys)
Parameter
Condition
VD = VDB = 15V
VIN = 5V
VD = VDB = 15V
VIN = 0V
Total of VP1-VNC, VN1-VNC
VUFB-U, VVFB-V, VWFB-W
Total of VP1-VNC, VN1-VNC
VUFB-U, VVFB-V, VWFB-W
VSC = 0V, FO terminal pull-up to 5V by 10kΩ
VSC = 1V, IFO = 1mA
Tj = 25°C, VD = 15V
(Note 4)
VIN = 5V
Trip level
VD = 15V,
At temperature of LVIC
Trip/reset hysteresis
Trip level
Reset level
Tj ≤ 125°C
Trip level
Reset level
(Note 6)
Circuit current
Fault output voltage
Short circuit trip level
Input current
Over temperature protection
(Note 5)
Control supply under-voltage
protection
Fault output pulse width
ON threshold voltage
OFF threshold voltage
ON/OFF threshold hysteresis
voltage
Applied between UP, VP, WP, UN, VN, WN-VNC
Min.
—
—
—
—
4.9
—
0.43
0.70
100
—
10.0
10.5
10.3
10.8
20
—
0.8
Limits
Typ.
—
—
—
—
—
—
0.48
1.00
120
10
—
—
—
—
—
2.1
1.3
Max.
2.80
0.55
2.80
0.55
—
0.95
0.53
1.50
140
—
12.0
12.5
12.5
13.0
—
2.6
—
0.35
0.65
—
Unit
mA
mA
mA
mA
V
V
V
mA
°C
V
V
V
V
µs
V
V
V
Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is
less than 1.7 times of the current rating.
5 : Over temperature protection (OT) outputs fault signal, when the LVIC temperature exceeds OT trip temperature level (OTt). In that case
if the heat sink comes off DIP-IPM or fixed loosely, don’t reuse that DIP-IPM. (There is a possibility that junction temperature of power
chips exceeded maximum Tj (150°C)).
6 : Fault signal is asserted only corresponding to a SC, a UV or an OT failure at lower side, and the FO pulse width is different for each failure modes. For SC failure, FO output is with a fixed width of 20µsec(min), but for UV or OT failure, FO output continuously during the
whole UV or OT period, however, the minimum FO pulse width is 20µsec(min) for very short UV or OT period less than 20µsec.
MECHANICAL CHARACTERISTICS AND RATINGS
Condition
Parameter
Mounting screw : M3
Recommended : 0.69 N·m
(Note 7)
Mounting torque
Weight
Heat-sink flatness
Note 7 : Plain washers (ISO 7089~7094) are recommended.
(Note 8)
Min.
Limits
Typ.
Max.
0.59
—
0.78
N·m
—
–50
10
—
—
100
g
µm
Unit
Note 8: Flatness measurement position
Measurement position
4.6mm
+ –
DIP-IPM
Heat sink side
–
+
Heat sink side
Aug. 2007
6
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
VCC
VD
VDB
∆VD, ∆VDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
IO
Allowable r.m.s. current
Condition
Applied between P-N
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
For each input signal, TC ≤ 100°C
TC ≤ 100°C, Tj ≤ 125°C
VCC = 300V, VD = VDB = 15V,
fPWM = 5kHz
P.F = 0.8, sinusoidal PWM,
(Note 9) fPWM = 15kHz
Tj ≤ 125°C, TC ≤ 100°C
PWIN(on) Allowable minimum input
PWIN(off) pulse width
(Note 10)
Min.
Limits
Typ.
Max.
0
13.5
13.0
–1
1.5
—
300
15.0
15.0
—
—
—
400
16.5
18.5
1
—
20
—
—
5.0
—
—
3.0
0.5
0.5
–5.0
—
—
—
—
—
5.0
Unit
V
V
V
V/µs
µs
kHz
Arms
VNC variation
VNC
Between VNC-N (including surge)
Note 9 : The allowable r.m.s. current value depends on the actual application conditions.
10 : IPM might not make response if the input signal pulse width is less than the recommended minimum value.
µs
V
Fig. 7 THE DIP-IPM INTERNAL CIRCUIT
DIP-IPM
VUFB
P
HVIC
VP1
VCC
VUB
UP
UP
UOUT
VNC
VVFB
VP
IGBT1
Di1
VUS
COM
U
IGBT2
VVB
Di2
VOUT
VP
VVS
VWFB
WP
V
VWB
WP
IGBT3
Di3
IGBT4
Di4
IGBT5
Di5
IGBT6
Di6
WOUT
VWS
W
LVIC
UOUT
VN1
VCC
VOUT
UN
UN
VN
VN
WN
WN
Fo
Fo
WOUT
CIN
VNO
VNC
GND
N
CIN
Aug. 2007
7
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 8 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-side only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO outputs (tFO(min) = 20µs).
a6. Input “L” : IGBT OFF.
a7. Input “H” : IGBT ON.
a8. IGBT OFF in spite of input “H”.
Lower-side control
input
a6 a7
Protection circuit state
SET
Internal IGBT gate
RESET
a3
a2
a1
SC
a4
Output current Ic
a8
SC reference voltage
Sense voltage of the
shunt resistor
CR circuit time
constant DELAY
Error output Fo
a5
[B] Under-Voltage Protection (Lower-side, UVD)
b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO outputs (tFO ≥ 20µs and FO outputs continuously during UV period).
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
Control supply voltage VD
RESET
UVDr
b1
SET
UVDt
b2
RESET
b6
b3
b4
b7
Output current Ic
Error output Fo
b5
Aug. 2007
8
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
[C] Under-Voltage Protection (Upper-side, UVDB)
c1. Control supply voltage rising : After the voltage level reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input signal level, but there is no FO signal outputs.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
RESET
SET
UVDBr
Control supply voltage VDB
c1
c5
UVDBt
c3
c2
c4
c6
Output current Ic
High-level (no fault output)
Error output Fo
[D] Over Temperature Protection (Lower-side, OT)
d1. Normal operation : IGBT ON and carrying current.
d2. LVIC temperature exceeds over temperature trip level (OTt).
d3. IGBT OFF in spite of control input condition.
d4. FO outputs during over temperature period, however, the minimum pulse width is 20µs.
d5. LVIC temperature becomes under over temperature reset level.
d6. Circuits start to operate normally when next input is applied.
Control input
RESET
Protection circuit state
SET
OTt
LVIC temperature
RESET
d5
d2
OTrh
d1
d3
d6
Output current Ic
d4
Fault output Fo
Fig. 9 RECOMMENDED MCU I/O INTERFACE CIRCUIT
5V line
DIP-IPM
10kΩ
UP,VP,WP,UN,VN,WN
MCU
3.3kΩ (min)
Fo
VNC(Logic)
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the
wiring impedance of the printed circuit board.
The DIP-IPM input section integrates a 3.3kΩ (min) pull-down resistor. Therefore, when using an external
filtering resistor, pay attention to the turn-on threshold voltage.
Fig. 10 WIRING CONNECTION OF SHUNT RESISTOR
DIP-IPM
Wiring inductance should be less than 10nH.
Equivalent to the inductance of a copper
pattern in dimension of width=3mm,
thickness=100µm, length=17mm
VNC
N
Shunt resistor
Please make the GND wiring connection
of shunt resistor to the VNC terminal
as close as possible.
Aug. 2007
9
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 11 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUIT
C1: Electrolytic capacitor with good temperature characteristics
C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering
C2
C1
VUFB
C2
VVFB
C2 C1
C1
VWFB
Bootstrap negative
electrodes should be
connected to U, V, W
terminals directly and
separated from the
main output wires.
DIP-IPM
P
HVIC
VP1
C3
UP
VCC
VUB
UP
UOUT
U
VUS
VVB
VP
VP
VOUT
V
VVS
M
VWB
MCU
WP
VNC
WP
WOUT
W
COM VWS
LVIC
UOUT
VN1
5V line
VCC
C3
VOUT
UN
VN
WN
Fo
UN
VN
WN
Long wiring here might
cause short-circuit.
WOUT
Fo
N
VNC
GND
C
CIN
15V line
Long GND wiring here might
generate noise to input and
cause IGBT malfunction.
B
R1
C4
A
Shunt
resistor
N1
Long wiring here might cause SC
level fluctuation and malfunction.
Note 1 : Input drive is High-Active type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the
wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on
and turn-off threshold voltage.
2 : Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
3 : FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ.
4 : To prevent erroneous protection, the wiring of A, B, C should be as short as possible.
5 : The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the
wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4.
6 : All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.)
7 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended.
8 : Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
9 : It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended
to connect control GND and power GND at only a point.
Aug. 2007
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