MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE PS21A7A MAIN FUNCTION AND RATINGS z 3 phase inverter with N-side open emitter structure z 600V / 75A (CSTBT) APPLICATION z AC100 ~ 200Vrms class, motor control INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS ● For P-side : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection ● For N-side : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC), ● Fault signaling : Corresponding to SC fault (N-side IGBT), UV fault (N-side supply) ● Temperature monitoring : Analog output of LVIC temperature ● Input interface : 3, 5V line, Schmitt trigger receiver circuit (High Active) ● UL Approved : File No. E80276 MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-NU,NV,NW Applied between P-NU,NV,NW TC= 25°C TC= 25°C, less than 1ms TC= 25°C, per 1 chip Ratings 450 500 600 75 150 162 -20~+150 Unit V V V A A W °C Ratings 20 20 -0.5~VD+0.5 -0.5~VD+0.5 1 -0.5~VD+0.5 Unit V V V V mA V Ratings Unit 400 V -20~+100 -40~+125 °C °C 2500 Vrms CONTROL (PROTECTION) PART Symbol VD VDB VIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Applied between UP, VP, WP-VPC, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC TOTAL SYSTEM Symbol TC Tstg Parameter Self protection supply voltage limit (Short circuit protection capability) Module case operation temperature Storage temperature Viso Isolation voltage VCC(PROT) Condition VD = 13.5~16.5V, Inverter Part Tj = 125°C, non-repetitive, less than 2μs (Note 1) 60Hz, Sinusoidal, AC 1minute, between connected all pins and heat-sink plate Note 1: Tc measurement point is described in Fig.1. THERMAL RESISTANCE Symbol Rth(j-c)Q Rth(j-c)F Parameter Junction to case thermal resistance (Note 2) Condition Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Min. - Limits Typ. - Max. 0.77 1.25 Unit °C/W °C/W Note 2: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of DIPIPM and heat-sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) is about 0.2°C/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k). 1 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE Fig. 1: TC MEASUREMENT POINT Measurement point for Tc ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton tC(on) toff tC(off) trr ICES Parameter Condition Tj= 25°C Tj= 125°C Collector-emitter saturation voltage VD=VDB = 15V VIN= 5V, IC= 75A FWDi forward voltage -IC= 75A, VIN= 0V Switching times VCC= 300V, VD= VDB= 15V IC= 75A, Tj= 125°C, VIN= 0↔5 V Inductive Load (upper-lower arm) Collector-emitter cut-off current VCE=VCES Tj= 25°C Tj= 125°C Min. 1.80 - Limits Typ. 1.55 1.65 1.70 2.40 0.40 3.40 0.60 0.30 - Max. 2.05 2.10 2.20 3.60 0.60 4.80 1.20 1 10 Min. - Limits Typ. - Max. 5.50 5.50 0.55 0.55 127 - - A 10.0 10.5 10.3 10.8 4.9 1.6 0.7 2.1 0.8 3.57 2.4 1.0 2.3 1.4 3.63 12.0 12.5 12.5 13.0 0.95 1.5 2.6 2.1 3.69 V V V V V V ms mA V V V Unit V V μs μs μs μs μs mA CONTROL (PROTECTION) PART Symbol Parameter ID Circuit current IDB Circuit current ISC Short circuit trip level UVDBt UVDBr UVDt UVDr VFOH VFOL tFO IIN Vth(on) Vth(off) VOT Control supply under-voltage protection Fault output voltage Fault output pulse width Input current ON threshold voltage OFF threshold voltage Temperature output Condition VD = 15V, VIN = 0V VD = 15V, VIN = 5V VD = VDB = 15V, VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VD = VDB = 15V, VIN = 5V -20°C≤Tj≤125°C, Rs= 23.2Ω (±1%), (Note 3) Not connecting outer shunt resistors to NU,NV,NW terminals Trip level P-side Reset level Tj ≤125°C Trip level N-side Reset level VSC = 0V, FO terminal pull-up to 5V by 10kΩ VSC = 1V, IFO = 1mA CFO=22nF (Note 4) VIN = 5V Total of VP1-VPC, VN1-VNC Applied between UP, VP, WP-VPC, UN, VN, WN-VNC LVIC temperature = 85°C (Note 5) Unit mA Note 3 : Short circuit protection can work for N-side IGBTs only. Isc level can change by sense resistance. For details, please refer the application note for this DIPIPM or contact us. And in that case, it should be for sense resistor to be larger resistance than the value mentioned above. Note 4 : Fault signal is output when short circuit or N-side control supply under-voltage protective functions operate. The fault output pulse-width tFO depends on the capacitance value of CFO. (CFO (typ.) = tFO x (9.1 x 10-6) [F]) Note 5 : DIPIPM don't shutdown IGBTs and output fault signal automatically when temperature rises excessively. When temperature exceeds the protective level that user defined, controller (MCU) should stop the DIPIPM. And this output might exceed 5V when temperature rises excessively, so it is recommended for protection of control part like MCU to insert a clamp Di between supply (e.g. 5V) for control part and this output. Temperature of LVIC vs. VOT output characteristics is described in Fig.2 2 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE Fig.2 Temperature of LVIC - VOT output characteristics 5.0 VOT Output (V) 4.5 4.26 4.0 110±10°C 3.63 3.5 85±3°C 3.0 60±10°C 2.5 40 50 60 70 80 90 100 110 120 130 LVIC Temperature (°C) MECHANICAL CHARACTERISTICS AND RATINGS Parameter Condition Mounting torque Mounting screw : M4 Terminal pulling strength Load 19.6N Terminal bending strength Load 9.8N, 90deg. bend Recommended 1.18N・m EIAJED-4701 EIAJED-4701 Weight Heat-sink flatness (Note 6) Min. 0.98 Limits Typ. 1.18 Max. 1.47 N・m 10 - - s 2 - - times - 46 - g -50 - 100 μm Unit Note 6: Measurement point of heat-sink flatness 3 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE RECOMMENDED OPERATION CONDITIONS Symbol Parameter VCC VD VDB ΔVD, ΔVDB tdead fPWM Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency IO Allowable r.m.s. current PWIN(on) PWIN(off) VNC Tj Minimum input pulse width VNC variation Junction temperature Min. 0 13.5 13.0 -1 2.7 - Limits Typ. 300 15.0 15.0 - Max. 400 16.5 18.5 +1 20 fPWM= 5kHz - - 35.0 fPWM= 15kHz - - 17.0 1.3 3.0 - - 5.0 - - -5.0 -20 - +5.0 +125 Condition Applied between P-NU, NV, NW Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS For each input signal, TC ≤ 100°C TC ≤ 100°C, Tj ≤ 125°C VCC = 300V, VD = 15V, P.F = 0.8, Sinusoidal PWM (Note 7) TC ≤ 100°C, Tj ≤ 125°C (Note 8) 200≤ VCC ≤ 350V, 13.5≤ VD ≤ 16.5V, IC≤75A 13.0≤ VDB ≤ 18.5V, -20°C ≤ TC ≤ 100°C, N line wiring inductance less than 10nH 75<IC≤127.5A (Note 9) Between VNC-NU, NV, NW (including surge) Unit V V V V/μs μs kHz Arms μs V °C Note 7: The allowable r.m.s. current value depends on the actual application conditions. 8: DIPIPM might not make response to the input on signal with pulse width less than PWIN (on). 9: IPM might make no response or delayed response (at P-side IGBT only) for the input signal with off pulse width less than PWIN(off). Please refer Fig. 3 about delayed response. Fig. 3 About Delayed Response Against Shorter Input Off Signal Than PWIN(off) (P-side only) P-side Control Input Internal IGBT Gate t2 Output Current Ic Solid line Broken line t1 …Off pulse width ≥ PWIN(off); Turn on time t1 (Normal delay) …Off pulse width < PWIN(off); Turn on time t2 (Longer delay in some cases) 4 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE Fig. 4 INTERNAL CIRCUIT VUFB VUFS P HVIC VP1 VCC VB UP IN HO IGBT1 Di1 COM VS VVFB VVFS VP1 HVIC VCC VB VP IN U IGBT2 Di2 HO V COM VS VWFB VWFS VP1 HVIC VCC VB WP IN VPC COM VS IGBT3 Di3 HO W LVIC IGBT4 Di4 UOUT VN1 NU VCC IGBT5 Di5 VOUT NV UN UN VN VN WN WN Fo VOT VNC Fo VOT GND IGBT6 WOUT Di6 VNO NW CIN CFO CFO 5 CIN Vsc March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE Fig. 5 TIMING CHARTS OF THE DIPIPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (N-side only with the external sense resistor and RC filter) a1. Normal operation: IGBT ON and outputs current. a2. Short circuit current detection (SC trigger) (It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs when SC.) a3. All N-side IGBT's gates are hard interrupted. a4. All N-side IGBTs turn OFF. a5. FO outputs with a fixed pulse width determined by the external capacitor CFO. a6. Input = “L”: IGBT OFF a7. Fo finishes output, but IGBTs don't turn on until inputting next ON signal (LÆH). (IGBT of each phase can return to normal state by inputting ON signal to each phase.) a8. Normal operation: IGBT ON and outputs current. Lower-side control input a6 SET Protection circuit state RESET a3 Internal IGBT gate a4 SC trip current level a8 Output current Ic a1 a7 a2 Sense voltage of the sense resistor SC reference voltage Delay by RC filtering Error output Fo a5 [B] Under-Voltage Protection (N-side, UVD) b1. Control supply voltage V D exceeds under voltage reset level (UVDr), but IGBT turns ON when inputting next ON signal (LÆH). (IGBT of each phase can return to normal state by inputting ON signal to each phase.) b2. Normal operation: IGBT ON and outputs current. b3. VD level drops to under voltage trip level. (UVDt). b4. All N-side IGBTs turn OFF in spite of control input condition. b5. Fo outputs for the period determined by the capacitance CFO, but output is extended during VD keeps below UVDr. b6. VD level reaches UVDr. b7. Normal operation: IGBT ON and outputs current. Control input RESET Protection circuit state Control supply voltage VD UVDr SET b1 UVDt b3 b4 b2 RESET b6 b7 Output current Ic b5 Error output Fo 6 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (P-side, UVDB) c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, IGBT can turn on when inputting next ON signal (LÆH). c2. Normal operation: IGBT ON and outputs current. c3. VDB level drops to under voltage trip level (UVDBt). c4. IGBT of corresponding phase only turns OFF in spite of control input signal level, but there is no FO signal output. c5. VDB level reaches UVDBr. c6. Normal operation: IGBT ON and outputs current. Control input RESET Protection circuit state SET RESET UVDBr Control supply voltage VDB c1 UVDBt c2 c5 c3 c6 c4 Output current Ic Error output Fo Keep High-level (no fault output) Fig. 6 MCU I/O INTERFACE CIRCUIT 5V line 10kΩ DIPIPM UP,VP,WP,UN,VN,WN MCU Fo 3.3kΩ(min) VNC(Logic) Note) Design for input RC filter depends on the PWM control scheme used in the application and the wiring impedance of the printed circuit board. The DIPIPM input signal interface integrates a 3.3kΩ(min) pull-down resistor. Therefore, when using RC filter, be careful to satisfy the turn-on threshold voltage requirement. Fo output is open drain type. It should be pulled up to the positive side of 5V or 15V power supply with the resistor that limits Fo sink current IFo under 1mA. In the case of pulling up to 5V supply, over 5.1kΩ is needed. (10kΩ is recommended.) 7 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE Fig. 7 AN EXAMPLE OF APPLICATION CIRCUIT UP(1) R3 C5 P(40) IGBT1 Di1 VP1(3) C2 HVIC VUFB(4) D2 + U(39) VUFS(6) C1 D1 C2 R3 C5 VP(7) IGBT2 Di2 VP1(9) C2 HVIC VVFB(10) D2 + V(38) VVFS(12) C1 D1 C2 R3 C5 WP(13) VPC(15) C2 IGBT3 VP1(14) Di3 HVIC VWFB(16) MCU D2 M W(37) + + VWFS(18) IGBT4 C1 D1 C2 Di4 C3 UN(27) R3 C5 NU(36) VN(28) R3 C5 WN(29) R3 IGBT5 Di5 C5 5V CFO(25) NV(35) R2 Fo(26) LVIC IGBT6 Di6 VOT(23) NW(34) 15V VD C1 VN1(21) + D1 C2 VNO VNC(22) C VSC(19) CIN(24) B C4 D R1 Rs Sense resistor A N1 Note 1 :If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point at which NU, NV, NW are connected to power GND line. 2 :To prevent surge destruction, the wiring between the smoothing capacitor and the P,N1 terminals should be as short as possible. Generally inserting a 0.1μ~0.22μF snubber capacitor C3 between the P-N1 terminals is recommended. 3 :The time constant R1C4 of RC filter for preventing protection circuit malfunction should be selected in the range of 1.5μs~2μs. SC interrupting time might vary with the wiring pattern. Tight tolerance, temp-compensated type is recommended for R1,C4. When R1 is too small, it will leads to delay of protection. So R1 should be min. 10 times larger resistance than Rs. (Over 100 times is recommended.) 4 :All capacitors should be mounted as close to the terminals of the DIPIPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and C2: 0.22μ~2.0μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.) 5 :It is recommended to insert a Zener diode D1 (24V/1W) between each pair of control supply terminals to prevent surge destruction. 6 :To prevent erroneous SC protection, the wiring from VSC terminal to CIN filter should be divided at the point D that is close to the terminal of sense resistor. And the wiring should be patterned as short as possible. 7 :For sense resistor, the variation within 1%(including temperature characteristics), low inductance type is recommended. And the over 1/8W is recommended, but it is necessary to evaluate in your real system finally. 8 :To prevent erroneous operation, the wiring of A, B, C should be as short as possible. 9 :Fo output is open drain type. It should be pulled up to the positive side of 5V or 15V power supply with the resistor that limits Fo sink current IFo under 1mA. In the case pull up to 5V supply, over R2=5.1kΩ is needed. (10kΩ is recommended.) 10 :Error signal output width (tFo) can be set by the capacitor connected to CFO terminal. CFO(typ.) = tFo x (9.1 x 10-6) (F) 11 :High voltage (VRRM =600V or more) and fast recovery type (trr=less than 100ns or less) diode D2 should be used in the bootstrap circuit. 12 :If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause erroneous operation. To avoid such problem, voltage ripple of control supply line should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p. 13 :Input drive is High-Active type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each input should be patterned as short as possible. When using RC filter R3C5, it is necessary to confirm the input signal level to meet the turn-on and turn-off threshold voltage. Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible. 8 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE Fig. 8 PACKAGE OUTLINES Dimensions in mm 9 March 2011 MITSUBISHI SEMICONDUCTOR < Dual-In-Line Package Intelligent Power Module> PS21A7A TRANSFER-MOLD TYPE INSULATED TYPE Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but these are always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (1) placement of substitutive, auxiliary circuits, (2) use of non-flammable material or (3) prevention against any malfunction or mishap. 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Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. DIPIPM and CSTBT are registered trademarks of MITSUBISHI ELECTRIC CORPORATION. 10 March 2011