HV9112 High-Voltage Current-Mode PWM Controller General Description Features ► ► ► ► ► ► The Supertex HV9112 is a BiCMOS/DMOS single-output, pulse width modulator IC intended for use in high-speed, high-efficiency switch mode power supplies. It provides all the functions necessary to implement a single-switch current mode PWM, in any topology, with a minimum of external parts. 10V to 120V Input Voltage Range Current-mode control High efficiency Up to 1.0MHz internal oscillator Internal start-up circuit Low internal noise Because the HV9112 utilizes Supertex’s proprietary BiCMOS/ DMOS technology, it requires less than one tenth of the operating power of conventional bipolar PWM ICs, and can operate at more than twice their switching frequency. The dynamic range for regulation is also increased, to approximately 8 times that of similar bipolar parts. It starts directly from any DC input voltage between 10 and 120VDC, requiring no external power resistor. The output stage is push-pull CMOS and thus requires no clamping diodes for protection, even when significant lead length exists between the output and the external MOSFET. The clock frequency is set with a single external resistor. Applications ► ► ► ► ► DC/DC converters Distributed power systems ISDN equipment PBX systems Modems Accessory functions are included to permit fast remote shutdown (latching or nonlatching) and under voltage shutdown. Ordering Information Device Package Option 14-Lead Narrow Body SOIC (NG) HV9112 HV9112NG-G For similar ICs intended to operate directly from up to 450VDC input, please consult the data sheets for the HV9120 and HV9123. For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24. -G indicates package is RoHS compliant (‘Green’) Pin Configuration OSC IN DISCHARGE VREF SHUTDOWN RESET COMP FB Absolute Maximum Ratings OSC OUT Parameter Input voltage, VIN Logic voltage, VDD Logic linear input, FB and sense input voltage Storage temperature VDD Value -VIN OUTPUT SENSE 80V 15.5V +VIN BIAS 14-Lead Narrow Body SOIC (NG) -0.3V to VDD +0.3V -65°C to +150°C Product Marking Top Marking Power dissipation 750mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HV9112NG YWW LLLLLLLL Bottom Marking CCCCCCCCC AAA Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking 14-Lead Narrow Body SOIC (NG) HV9112 Electrical Characteristics (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions VREF Output voltage - 3.88 4.00 4.12 V RL = 10MΩ ZOUT Output impedence # 15 30 45 KΩ --- ISHORT Short circuit current - - 125 250 μA VREF = -VIN ΔVREF Change in VREF with temperature # - 0.25 - mV/°C fMAX Oscillator frequency - 1.0 3.0 - MHz fOSC Initial accuracy(1) - 80 100 120 - 160 200 240 - Voltage stability - - - 15 % - Temperature coefficient # - 170 - ppm/°C Maximum duty cycle - 49.0 49.4 49.6 % --- Deadtime # - - - ns --- Minimum duty cycle - - - 0 % --- Maximum pulse width before pulse drops out # - 80 125 ns --- Maximum input signal - 1.0 1.2 1.4 V VFB = 0V Delay to output # - 80 120 ns VSENSE = 1.5V, VCOMP ≤ 2.0V Reference TA = -55°C to 125°C Oscillator PWM DMAX DMIN KHz ROSC = 1.0MΩ ROSC = 330KΩ ROSC = 150KΩ VSYNC = 0.1V TA = -55°C to 125°C Current Limit tD Error Amplifier VFB Feedback voltage - 3.92 4.00 4.08 V VFB shorted to comp IIN Input bias current - - 25 500 nA VFB = 4.0V VOS Input offset voltage - nulled during trim AVOL Open loop voltage gain # 60 80 GB Unity gain bandwidth # 1.0 1.3 ZOUT Out impedance # Output source current - -1.4 -2.0 - mA VFB = 3.4V Output sink current - 0.12 0.15 - mA VFB = 4.5V Power supply rejection # dB --- ISOURCE ISINK PSRR - --- - dB --- - MHz --- Ω --- see Fig. 1 see Fig. 2 Notes: # Guaranteed by design. Not subject to production test. (1) Stray capacitance on OSC In pin must be ≤5pF. 2 HV9112 Electrical Characteristics (cont.) (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions Pre-regulator/Startup +VIN Input voltage - 9.0 - 80 V IIN < 10µA; VCC > 9.4V +IIN Input leakage current - - - 10 μA VDD > 9.4V VTH Vdd pre-regulator turn-off threshold voltage - 8.0 8.7 9.4 V IPREREG = 10µA Undervoltage lockout - 7.0 8.1 8.9 V --- IDD Supply current - - 0.75 1.0 mA CL < 75pF IQ Quiescent supply current - - 0.55 - mA Shutdown = -VIN IBIAS Nominal Bias current - - 20 - μA --- VDD Operating range - 9.0 - 13.5 V --- CL = 500pF, VSENSE = -VIN VLOCK Supply Shutdown Logic tSD Shutdown delay # - 50 100 ns tSW Shutdown pulse width # 50 - - ns tRW RESET pulse width # 50 - - ns --- tLW Latching pulse width # 25 - - ns Shutdown and reset low VIL Input low voltage - - - 2.0 V --- VIH Input high voltage - 7.0 - - V --- IIH Input current, input high voltage - - 1.0 5.0 μA VIN = VDD IIL Input current, input low voltage - - -25 -35 μA VIN = 0V VOH Output high voltage - VDD - 0.3 - - V IOUT = 10mA, VOL Output low voltage - - - 0.2 V IOUT = -10mA Pull up - - 15 25 Ω Pull down - - 8.0 20 Ω Pull up - - 20 30 Ω Pull down - - 10 30 Ω IOUT = ±10mA, TA = -55°C to 125°C Output ROUT Output resistance IOUT = ±10mA tR Rise time # - 30 75 ns CL = 500pF tF Fall time # - 20 75 ns CL = 500pF Notes: # Guaranteed by design. Not subject to production test. 3 HV9112 Truth Table Shutdown Reset Output H H H H→L L H Off, not latched L L Off, latched L→H L Off, latched, no change Normal operation Normal operation, no change Shutdown Timing Waveforms 1.5V tF ≤ 10ns VDD tR ≤ 10ns 50% Sense 50% Shutdown 0 0 td t SD VDD Output VDD 90% Output 0 0 t SW VDD 50% Shutdown 90% tR, tF ≤ 10ns 50% 0 t LW VDD Reset 50% 50% 50% 0 t RW Functional Block Diagram FB COMP 14 (19) Discharge 13 (18) 9 (12) OSC IN OSC OUT 8 (11) 7 (10) Error Amplifier OSC – 10 (14) VREF + 2V Modulator Comparator – 4V 4 (6) Q Output S + Current Sources To Internal Circuits 5 (8) Current Limit Comparator – 1 (20) To VDD Q R + REF GEN BIAS T -VIN 1.2V 3 (5) 6 (9) Current Sense VDD VDD 2 (3) – +VIN 11 (16) Undervoltage Comparator Shutdown S Q 8.1V – + Reset R + 12 (17) 8.6V Pre-regulator/Startup 4 HV9112 Typical Performance Curves Fig. 1 Fig. 4 Error Amplifier Output Impedance (Z0) 1M 6 10 Output Switching Frequency vs. Oscillator Resistance 105 fOUT (Hz) ZO (Ω) 104 103 102 100k 10 1 .1 1KHz 100KHz 10KHz 1MHz 10k 10k 10MHz 100 k Frequency PSRR — Error Amplifier and Reference Fig. 2 Fig. 5 0 80 -10 70 -20 Gain (dB) -30 PSSR (dB) 1M ROSC (Ω) -40 -50 -60 -70 Error Amplifier Open Loop Gain/Phase 60 180 50 120 40 60 30 0 20 -60 10 -120 0 -180 -10 -80 10 100 1K 10K 100K 1M 100 1K 100K 10K 1M Frequency (Hz) Frequency (Hz) RDISCHARGE vs. tOFF (9113 only) 100 Fig. 6 104 ROSC = 100K VDD = 12V VDD = 10V tOFF (nsec) Bias Current (µA) Fig. 3 10 103 ROSC = 10K ROSC = 1K 1 105 10 6 102 10-1 107 100 101 102 103 RDISCHARGE (Ω) Bias Resistance (Ω) 5 104 105 106 Phase (°C) 100Hz HV9112 Test Circuits Error Amp ZOUT +10V (VDD) 0.1V swept 10Hz – 1MHz PSRR 1.0V swept 100Hz – 2.2MHz 100K1% 60.4K – (FB) + Reference GND (–VIN) 100K1% 10.0V V1 Tektronix P6021 (1 turn secondary) 4.00V V2 + Reference 40.2K 0.1µF V1 – V2 0.1µF NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE ± 1mV before connecting transformer Detailed Description Preregulator Bias Circuit The preregulator/startup circuit for the HV9112 consists of a high-voltage n-channel depletion-mode DMOS transistor driven by an error amplifier to form a variable current path between the VIN terminal and the VDD terminal. The maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source(generally the supply the chip is controlling). No current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. An external bias resistor, connected between the BIAS pin and VSS is required by the HV9112 to set currents in a series of current mirrors used by the analog sections of the chip. The nominal external bias current requirement is 15 to 20µA, which can be set by a 390KΩ to 510KΩ resistor if a 10V VDD is used, or a 510kΩ to 680KΩ resistor if VDD will be 12V. A precision resistor is not required; ± 5% is fine. Clock Oscillator The clock oscillator of the HV9112 consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in the 50% maximum duty cycle versions, a frequency dividing flip-flop. A single external resistor between the OSC IN and OSC OUT is required to set the oscillator frequency (see graph). For the 50% maximum duty cycle versions the Discharge pin is internally connected to GND. For the 99% duty cycle version, the Discharge pin can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One major difference exists between the Supertex HV9112 and competitive 9110’s. On the Supertex part, the oscillator is shut off when a shutoff command is received. This saves about 150µA of quiescent current, which aids in the construction of power supplies that meet CCITT specification I-430, and in other situations where an absolute minimum of quiescent power dissipation is required. An external capacitor between VDD and VSS is generally required to store energy used by the chip in the time between shutoff of the high voltage path and the VDD supply’s output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., CSTORAGE ≥ 100 x (gate charge of FET at 10V ÷ 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor VDD for both the under voltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the under voltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the under voltage lockout always releases before the FET shuts off. 6 HV9112 Reference Current Sense Comparators The Reference of the HV9112 consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier, when connected in a gain of –1 configuration, is as close to 4.0V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. The HV9112 uses a true dual comparator system with independent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction. Remote Shutdown The shutdown and reset pins of the 9110 can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open drain logic. When not used they should be left open, or connected to VDD. A ≈ 50KΩ resistor is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a low impedance voltage source ≤6.0V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. Because the reference of the HV9112 is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1µF. Output Buffer The output buffer of the HV9112 is of standard CMOS construction (P-channel pull-up, N-channel pull-down). Thus the body-drain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required. Error Amplifier The error amplifier in the HV9112 is a true low-power differential input operational amplifier intended for around the amplifier compensation. It is of mixed CMOS-bipolar construction: A PMOS input stage is used so the common mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity gain stable. 7 HV9112 14-Lead SOIC (Narrow Body) Package Outline (NG) 8.65x3.90mm body, 1.27mm pitch D 14 θ1 E1 Note 1 (Index Area D/2 x E1/2) E 1 L L2 Gauge Plane θ Seating Plane L1 Top View View B A View B h A A2 e A1 Note 1 h Seating Plane b A Side View View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol A MIN Dimension (mm) NOM MAX 1.35 1.75 A1 0.10 0.25 A2 1.25 1.65 b 0.31 0.51 D 8.55 8.65 8.75 E 5.80 6.00 6.20 E1 e 3.80 3.90 4.00 h 0.25 1.27 BSC 0.50 L L1 L2 0.40 1.27 θ 0 1.04 REF 0.25 BSC O O 8 θ1 5O 15O JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005. Drawinngs not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV9112 A101007 8