HV9105 HV9108 High-Voltage Switchmode Controllers with MOSFET Ordering Information MOSFET Switch +VIN Package Outlines BVDSS RDS(ON) Min Max Feedback Voltage Max Duty Cycle 14 Pin Plastic DIP 20 Pin Plastic PLCC 200V 5.0Ω 10V 120V ±1% 49% HV9105P HV9105PJ 200V 5.0Ω 10V 120V ±1% 99% HV9108P HV9108PJ Standard temperature range for all parts is industrial (-40° to +85°C). Features General Description ❏ 10 to 120V input range ❏ 200V, 5Ω output MOSFET ❏ Current-Mode Control ❏ High Efficiency The Supertex HV9105 and HV9108 are high-efficiency high voltage SMPS ICs intended for use in power converters requiring extreme efficiency at output power levels of 5.0W or less. The low supply current (0.5mA max) allows them to be used to build supplies which meet CCITT I.430 performance recommendations (60% efficiency at .025W out). ❏ CCITT Compatible ❏ Internal Start-up Circuit The HV9105/08 provides all the functions necessary to build a single-switch current-mode converter of any common topology, with a minimum of external parts. In addition to high efficiency, because it uses Supertex’s proprietary high voltage BiCMOS/DMOS technology, the HV9105/08 offers numerous performance advantages when compared to conventional PWM ICs. Dynamic range is approximately 8 times wider than with bipolar ICs, both response speed and maximum clock rate are faster, and no external power resistors or zeners are necessary for high voltage starting. Applications ❏ DC/DC Converters ❏ Distributed Power Systems ❏ ISDN Equipment Accessory circuits are included to provide either latching or nonlatching shutdown. When shut down, device dissipation is less than 4mW. ❏ PBX Systems ❏ Modems The HV9105/08 is intended for operation with input voltages from 10 to 120VDC. Absolute Maximum Ratings +VIN, Input Voltage 120V VDS 200V VDD, Logic Voltage 15.0V Control Inputs ID (Peak) Storage Temperature Power Dissipation, Plastic DIP Power Dissipation, PLCC -0.3V to VDD+0.3V 2.5A -65°C to 150°C 750mW 1400mW For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24. 11/12/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV9105/HV9108 Electrical Characteristics (VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 820KΩ, ROSC = 910KΩ,TA = 25°C, unless otherwise specified) Symbol Parameters Min Typ Max Unit Conditions 3.92 4.00 4.08 V RL = 10MΩ 15 30 45 KΩ 130 µA Reference VREF Output Voltage Impedance1 ZOUT Output ISHORT Short Circuit Current 100 ∆VREF Change in VREF with Temperature 0.25 mV/°C MHz VREF = -VIN Oscillator fMAX Maximum Oscillator Frequency 1.0 3.0 fOSC Initial Accuracy2 32 40 Voltage Stability1 Temperature Coefficient1 48 KHz 15 % 170 ROSC = 0Ω 9.5V < VDD < 13.5V ppm/°C PWM DMAX Maximum Duty Cycle1 Deadtime1 DMIN HV9105 49.0 49.4 49.6 HV9108 99.0 99.4 99.6 HV9108 100 Minimum Duty Cycle Minimum Pulse Width Before Pulse Drops Out1 % nsec 0 % 110 175 nsec 4.00 4.04 V VFB Shorted to Comp 25 500 nA VFB = 4.0V Error Amplifier VFB Feedback Voltage IIN Input Bias Current VOS Input Offset Voltage AVOL gbw Open Loop Voltage Unity Gain 3.96 Gain1 Bandwidth1 mV 60 80 dB 0.5 0.8 MHz See Fig. 2 Ω Impedance1 ZOUT Output ISOURCE Output Source Current ISINK Output Sink Current PSRR nulled at trim Power Supply -1.3 50 -1.0 80 Rejection1 mA VFB = 3.4V µA VFB = 4.5V See Fig. 1 Current Limit VSOURCE Threshold Voltage td 1.0 1.2 1.4 V VFB = 0V, RL = 100Ω 150 200 ns VSOURCE = 1.5V, RL = 100Ω Allowable Input Voltage 120 V IIN = 10µA Input Leakage Current 10 µA VDD > 9.4V Delay to Output1 Pre-Regulator/Startup +VIN VTH VDD Pre-regulator Turn-off Threshold Voltage 7.8 8.6 9.4 V IPREREG = 10µA VLOCK Undervoltage Lockout 7.0 8.1 8.9 V RL = 100Ω from Drain to VDD Notes: 1. Guaranteed by design. Not subject to production test. 2. Stray capacitance on OSC IN pin ≤5pF. 2 HV9105/HV9108 Electrical Characteristics (Continued) (VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 820KΩ, ROSC = 910KΩ,TA = 25°C, unless otherwise specified) Symbol Parameters Min Typ Max Unit 0.6 mA Conditions Supply IDD Supply Current IBIAS Bias Current VDD Operating Range 0.35 mA 7.5 µA 9.0 13.5 Shutdown = -VIN V Logic tSD Shutdown Delay Time1 tSW Shutdown Pulse Width1 50 ns tRW RESET Pulse Width1 50 ns tLW Latching Pulse Width1 25 VIL Input Low Voltage VIH Input High Voltage IIH Input High Current 1.0 5.0 µA VIN = 10V IIL Input Low Current -25 -35 µA VIN = 0V V VSOURCE = Shutdown = 0V, 50 100 ns VSOURCE = -VIN ns 2.0 7.0 V V MOSFET Switch BVDSS Breakdown Voltage 200 240 ID = 100µA RDS(ON) Drain-to-Source On-resistance 3.5 IDSS OFF State Drain Leakage Current CDS Drain Capacitance 35 Note: 1. Guaranteed by design. Not subject to production test. Truth Table Shutdown Reset Output H H H H→L L H Off, Not Latched L L Off, Latched L→H L Off, Latched, No Change Normal Operation Normal Operation, No Change 3 5.0 Ω VSOURCE = 0V, ID = 100mA 10 µA VSOURCE = Shutdown = 0V, VDRAIN = 100V pF VDS = 25V, Shutdown = 0V HV9105/HV9108 Switching Waveforms 1.5V tF ≤ 10ns VDD tR ≤ 10ns 50% Source 50% SHUTDOWN 0 0 td t SD VDD Drain VDD 90% Drain 0 90% 0 t SW VDD Shutdown 50% tR, tF ≤ 10ns 50% 0 t LW VDD Reset 50% 50% 50% 0 t RW Functional Block Diagram FB 14 (20) COMP 13 (18) Error Amplifier OSC OSC In Out Discharge 8 (11) 9 (12) OSC – 10 (14) + VREF 2V Current-mode Comparator – 4V VDD R Q S To Internal Circuits Current Sources Q 9105 9108 V DD + Drain (5) 3 C/L Comparator – 1 (2) T + REF GEN BIAS 7 (10) (8) 5 1.2V -V IN V DD 6 (9) 2 (3) – +VIN Undervoltage Comparator S Source (7) 4 (16) 11 Shutdown Q 8.1V – + Reset R + (17) 12 8.6V Pre-regulator/Startup Pin numbers in parentheses are for PLCC package. 4 HV9105/HV9108 Typical Performance Curves 80 0 70 240° 60 180° 50 120° 40 60° 30 0° 20 -60° -60 10 -120° -70 0 -180° -10 -20 Gain (dB) -30 (dB) Error Amplifier Open Loop Gain/Phase Fig. 3 PSRR – Error Amplifier and Reference -40 -50 -10 -80 10Hz 100Hz 1KHz 10KHz 100KHz 100Hz 1MHz 1KHz 10KHz 100KHz 1MHz Frequency Fig. 2 Error Amplifier Output Impedance (Z0) Output Switching Frequency vs. Oscillator Resistance Fig. 4 1M 106 105 104 fOUT (Hz) (Ω) HV9108 HV9105 103 102 100k 10 1.0 0.1 10k 10k .01 100Hz 1KHz 10KHz 1MHz 100KHz 10MHz 100 k 1M ROSC (Ω) Test Circuits Error Amp ZOUT PSRR 0.1V swept 10Hz – 1MHz +10V (VDD) 1.0V swept 100Hz – 2.2MHz 100K1% 60.4K – (FB) GND (–VIN) 10.0V + Reference 100K1% V1 Tektronix P6021 (1 turn secondary) 4.00V V2 Reference 40.2K 0.1µF 0.1µF NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE ± 1mV before connecting transformer 5 V1 – + V2 Phase Fig. 1 HV9105/HV9108 Technical Description Preregulator Reference The preregulator/startup circuit for the HV9105/08 consists of a high-voltage N-channel depletion-mode DMOS transistor driven by an error amplifier to form a controlled current path between the VIN terminal and the VDD terminal of the HV9105/08. Maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source (generally the supply the chip is controlling) no current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. The reference section of the HV9105/08 consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier when connected in a gain of -1 configuration is as close to 4.000V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be 4.0V. An external capacitor between VDD and VSS is generally required to store energy used by the chip during the time between shutoff of the high voltage path and the VDD supply’s output rising enough to take over the powering of the chip. This capacitor generally also serves as the output filter capacitor for that output from the supply. 1.0µF is generally sufficient to assure against double-starting. Capacitors as small as 0.1µF can work when faster response from the VDD line is required. The chosen capacitor should have very good high frequency characteristics and be mounted so that the sum of the lead length between capacitor and IC for both leads is less than 2.5 cm. Stacked polyester or ceramic capacitors work well. Electrolytic capacitors are generally not suitable. A resistor of approximately 50KΩ is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a lowimpedance voltage source ≤6.0V. In general, because the reference voltage of the Supertex HV9105/08 is not noisy, as some previous devices have been, overriding the reference should seldom be necessary. Because the reference is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1µF. A common resistor divider string is used to monitor VDD for both the undervoltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout always releases before the FET shuts off. Error Amplifier The error amplifier is a true low-power differential input operational amplifier intended for around-the-amplifier compensation. It is of mixed CMOS-bipolar construction: a PMOS input stage is used so the common-mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity-gain stable. Bias Circuit An external bias resistor, connected between the bias pin and VSS is required by the HV9105/08 to set currents in a series of current mirrors used by the analog sections of the chip. Nominal external bias current requirement is 7.5µA, which can be set by a 820KΩ to 1.3MΩ resistor if a 10V VDD is used, or a 1.2MΩ to 2.0MΩ resistor if a 12V VDD is used. A precision resistor is NOT required; ± 5% is fine. Current Sense Comparators The HV9105/08 uses a true dual comparator system with independent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction. For extremely low power operation, the value of bias current can be reduced to as low as 4.0µA by further increases in the value of the bias resistor. Clock Oscillator Remote Shutdown The clock oscillator of the HV9105/08 consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in the 50% maximum duty cycle version, a frequency dividing flipflop. A single external resistor between the OSC In and OSC Out pins is required to set oscillator frequency (see Fig. 4). For the 50% maximum duty cycle versions the ‘Discharge’ pin is internally connected to GND. For the 99% duty cycle version, ‘Discharge’ can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. The shutdown and reset pins can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open-drain logic. When not used, they should be left open, or connected to VDD. Main Switch The main switch is a normal N-channel power MOSFET. Unlike the situation with competitive devices, the body diode can be used if desired without destroying the chip. One difference exists between the Supertex HV9105/08 and competitive 9105 parts. The oscillator of the Supertex HV9105/08 is shut off when a shutoff command is received. This saves about 100µA of quiescent current, which aids in the construction of power supplies to meet CCITT specification I.430, and in other situations where an absolute minimum of quiescent power dissipation is required. 6 HV9105/HV9108 +VIN 2 13 COMP Drain 3 12 Reset Source 4 11 Shutdown –VIN 5 10 VREF VDD 6 9 Discharge OSC Out 7 8 OSC In Reset Shutdown NC VREF 15 14 NC 19 13 NC Feedback 20 12 Discharge NC 1 11 OSC In BIAS 2 10 OSC Out +VIN 3 9 VDD 14 Pin DIP Package • NC 4 5 6 7 8 –VIN Feedback 16 Source 14 17 NC 1 18 Drain BIAS COMP Pinout 20-pin PJ Package top view 11/12/01 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com