SUPERTEX HV9103P

HV9100
HV9102
HV9103
High-Voltage Switchmode Controllers with MOSFET
Ordering Information
+VIN
Min
Max
Feedback
Voltage
Max
Duty Cycle
MOSFET Switch
BVDSS
RDS (ON)
Package Options
14 Pin Plastic DIP 20 Pin Plastic PLCC
10V
70V
± 1.0%
49%
150V
5.0Ω
HV9100P
HV9100PJ
10V
120V
± 1.0%
49%
200V
7.0Ω
HV9102P
HV9102PJ
10V
120V
±1.0%
99%
200V
7.0Ω
HV9103P
HV9103PJ
Standard temperature range for all parts is industrial (-40° to +85°C).
Features
General Description
❏
10 to 120V input range
❏
200V, 7.0Ω output MOSFET
❏
Current-Mode Control
❏
High Efficiency
The Supertex HV9100 through HV9103 are a series of BiCMOS/
DMOS single-output, pulse width modulator ICs intended for use
in high-speed high-efficiency switchmode power supplies. They
provide all the functions necessary to implement a single-switch
current-mode PWM, in any topology, with a minimum of external
parts.
❏
Up to 1MHz Internal Oscillator
❏
Internal Start-up Circuit
Utilization of Supertex proprietary BiCMOS/DMOS technology
results in a device with one tenth of the operating power of
conventional bipolar PWM ICs, which can operate at more than
twice their switching frequency. Dynamic range for regulation is
also increased, to approximately 8 times that of similar bipolar
parts. They start directly from any DC input voltage between 10
and 70VDC for the HV9100 or 10 to 120VDC for the HV9102 and
HV9103, requiring no external power resistor. The output stage
for the HV9100 is a 150V, 5.0 ohm MOSFET and for the HV9102
and HV9103 is a 200V, 7.0 ohm MOSFET. The clock frequency
is set with a single external resistor.
Applications
❏ DC/DC Converters
❏ Distributed Power Systems
❏ ISDN Equipment
❏ PBX Systems
❏ Modems
Accessory functions are included to permit fast remote shutdown
(latching or nonlatching), and undervoltage shutdown.
Absolute Maximum Ratings
+VIN, Input Voltage
120V
VDS
200V
VDD, Logic Voltage
15.0V
Input Voltage Logic, Linear, FB and Sense -0.3V to VDD+0.3V
ID (Peak)
Storage Temperature
Power Dissipation, Plastic DIP
Power Dissipation, PLCC
2.5A
-65°C to 150°C
750mW
1400mW
For detailed circuit and application information, please refer
to application notes AN-H13 and AN-H21 to AN-H24.
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products,
1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV9100/HV9102/HV9103
Electrical Characteristics
(VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C, unless otherwise specified)
Symbol Parameters
Min
Typ
Max
Unit
Conditions
HV9100/02/03
3.92
4.00
4.08
V
RL = 10MΩ
HV9102/03
3.86
4.00
4.14
V
IN = VIN, RL = 10MΩ
TA = -55°C to 125°C
15
30
45
KΩ
250
µA
Reference
VREF
Output Voltage
ZOUT
Output Impedance1
ISHORT
Short Circuit Current
100
∆VREF
Change in VREF with Temperature
0.25
mV/°C
MHz
ROSC = 0Ω
KHz
ROSC = 330KΩ
VREF = -VIN
Oscillator
fMAX
Oscillator Frequency
1.0
3.0
fOSC
Accuracy2
80
100
120
160
200
240
Initial
Voltage Stability
15
Temperature Coefficient
170
ROSC = 150KΩ
%
9.5V < VDD < 13.5V
ppm/°C
PWM
DMAX
Maximum Duty Cycle
Deadtime
DMIN
HV9100/02
49.0
49.4
49.6
HV9103
99.0
99.4
99.6
HV9103
100
Minimum Duty Cycle
%
nsec
0
%
110
175
nsec
4.00
4.04
V
VFB Shorted to Comp
25
500
nA
VFB = 4.0V
nulled at trim
mV
Except 9101
60
80
dB
1.0
1.3
MHz
See Fig. 2
Ω
Minimum Pulse Width
Before Pulse Drops Out 1
Error Amplifier
VFB
Feedback Voltage
IIN
Input Bias Current
VOS
Input Offset Voltage
AVOL
gbw
Open Loop Voltage
Unity Gain
HV9100/02/03
Gain1
Bandwidth1
3.96
Impedance1
ZOUT
Output
ISOURCE
Output Source Current
ISINK
Output Sink Current
PSRR
Power Supply Rejection
-2.0
0.12
-1.4
0.15
mA
VFB = 3.4V
mA
VFB = 4.5V
See Fig. 1
Current Limit
VSOURCE Threshold Voltage
td
Delay to
1.0
1.2
Output1
Notes:
1. Guaranteed by design. Not subject to production test.
2. Stray capacitance on OSC In pin ≤5pF.
2
1.4
V
VFB = 0V, RL = 100Ω
150
ns
VSOURCE = 1.5V, RL = 100Ω
HV9100/HV9102/HV9103
Electrical Characteristics
(Continued)
(VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C, unless otherwise specified)
Symbol Parameters
Min
Typ
Max
Unit
Conditions
HV9100
70
V
IIN = 10µA
HV9102/03
120
10
µA
VDD > 9.4V
Pre-Regulator/Startup
+VIN
Allowable Input Voltage
Input Leakage Current
VTH
VDD Pre-regulator Turn-off
Threshold Voltage
7.8
8.6
9.4
V
IPREREG = 10µA
VLOCK
Undervoltage Lockout
7.0
8.1
8.9
V
RL = 100Ω from Drain to VDD
0.60
1.0
mA
Supply
IDD
Supply Current
IBIAS
Bias Current
VDD
Operating Range
0.55
mA
20
µA
9.0
13.5
V
100
ns
Shutdown = -VIN
Logic
tSD
Shutdown Delay Time1
tSW
Width1
Shutdown Pulse
tRW
RESET Pulse
50
Width1
Width1
50
ns
50
ns
25
ns
VSOURCE = -VIN
tLW
Latching Pulse
VIL
Input Low Voltage
VIH
Input High Voltage
IIH
Input High Current
1.0
5.0
µA
VIN = 10V
IIL
Input Low Current
-25
-35
µA
VIN = 0V
V
VSOURCE = Shutdown = 0V,
2.0
7.0
V
V
MOSFET Switch
BVDSS
RDS(ON)
Breakdown Voltage
HV9100
150
HV9102/03
200
Drain-to-Source
HV9100
On-resistance
HV9102/03
IDSS
OFF State Drain Leakage Current
CDS
Drain Capacitance
ID = 100µA,
TA = -55°C to 125°C
3.5
35
Note:
1. Guaranteed by design. Not subject to production test.
Truth Table
Shutdown
Reset
Output
H
H
H
H→L
L
H
Off, Not Latched
L
L
Off, Latched
L→H
L
Off, Latched, No Change
Normal Operation
Normal Operation, No Change
3
5.0
Ω
7.0
Ω
10
µA
VSOURCE = Shutdown = 0V,
VDRAIN = 100V
pF
VDS = 25V, Shutdown = 0V
VSOURCE = 0V, ID = 100mA
HV9100/HV9102/HV9103
Switching Waveforms
1.5V
tF ≤ 10ns
VDD
tR ≤ 10ns
50%
Source
50%
Shutdown
0
0
td
t SD
VDD
Drain
VDD
90%
90%
Drain
0
0
t SW
VDD
Shutdown
50%
tR, tF ≤ 10ns
50%
0
t LW
VDD
Reset
50%
50%
50%
0
t RW
Functional Block Diagram
FB
14
(20)
COMP
13
(18)
Error
Amplifier
OSC OSC
In Out
Discharge
8
(11)
9
(12)
OSC
–
10 (14)
+
VREF
2V
Current-mode
Comparator
–
4V
Q
VDD
To
Internal
Circuits
9100
9102
V DD
+
Current
Sources
Q
9103
S
Drain
(5) 3
C/L
Comparator
–
BIAS
T
R
+
REF
GEN
1 (2)
7
(10)
(8) 5
1.2V
-V IN
V DD
6 (9)
2 (3)
–
+VIN
Undervoltage
Comparator
S
Source
(7) 4
(16) 11
Shutdown
Q
8.1V
–
+
Reset
R
+
(17) 12
8.6V
Pre-regulator/Startup
Pin numbers in parentheses are for PLCC pacage.
4
HV9100/HV9102/HV9103
Typical Performance Curves
80
70
-10
-20
Gain (dB)
-30
(dB)
Error Amplifier
Open Loop Gain/Phase
Fig. 3
PSRR – Error Amplifier and Reference
0
-40
-50
60
180°
50
120°
40
60°
30
0°
20
-60°
-60
10
-70
0
-120°
-180°
-10
-80
10Hz
100Hz
1KHz
10KHz
100KHz
100Hz
1MHz
1KHz
100KHz
10KHz
1MHz
Frequency
Error Amplifier Output Impedance (Z0)
Fig. 2
Output Switching Frequency
vs. Oscillator Resistance
Fig. 4
1M
106
105
104
HV9103
fOUT (Hz)
(Ω)
103
102
HV9100, 9101, 9102
100k
10
1.0
0.1
.01
100Hz
1KHz
10KHz
1MHz
100KHz
10k
10k
10MHz
100 k
1M
ROSC (Ω)
Test Circuits
Error Amp ZOUT
PSRR
0.1V swept 10Hz – 1MHz
+10V
(VDD)
1.0V swept 100Hz – 2.2MHz
60.4K
100K1%
–
(FB)
+
Reference
GND
(–VIN)
100K1%
10.0V
V1
Tektronix
P6021
(1 turn
secondary)
4.00V
V2
Reference
40.2K
0.1µF
0.1µF
NOTE: Set Feedback Voltage so that
VCOMP = VDIVIDE ± 1mV before connecting transformer
5
V1
–
+
V2
Phase
Fig. 1
HV9100/HV9102/HV9103
Technical Description
Preregulator
Reference
The preregulator/startup circuit for the HV910x consists of a highvoltage N-channel depletion-mode DMOS transistor driven by an
error amplifier to form a controlled current path between the VIN
terminal and the VDD terminal. Maximum current (about 20 mA)
occurs when VDD = 0, with current reducing as VDD rises. This path
shuts off altogether when VDD rises to somewhere between 7.8
and 9.4V, so that if VDD is held at 10 or 12V by an external source
(generally the supply the chip is controlling) no current other than
leakage is drawn through the high voltage transistor. This minimizes dissipation.
The reference consists of a stable bandgap reference followed by
a buffer amplifier which scales the voltage up to approximately
4.0V. The scaling resistors of the reference buffer amplifier are
trimmed during manufacture so that the output of the error
amplifier when connected in a gain of -1 configuration is as close
to 4.000V as possible. This nulls out any input offset of the error
amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4V, the feedback
voltage required for proper regulation will be 4V.
A resistor of approximately 50KΩ is placed internally between the
output of the reference buffer amplifier and the circuitry it feeds
(reference output pin and NON-INVERTING input to the error
amplifier). This allows overriding the internal reference with a lowimpedance voltage source ≤6V. Using an external reference
reinstates the input offset voltage of the error amplifier, and its
effect of the exact value of feedback voltage required. In general,
because the reference voltage of the Supertex HV910x is not
noisy, as some previous devices have been, overriding the
reference should seldom be necessary.
An external capacitor between VDD and VSS is generally required
to store energy used by the chip during the time between shutoff
of the high voltage path and the VDD supply’s output rising enough
to take over the powering of the chip. This capacitor generally also
serves as the output filter capacitor for that output from the supply.
1µF is generally sufficient to assure against double-starting.
Capacitors as small as 0.1µF can work when faster response from
the VDD line is required. Whatever capacitor is chosen should
have very good high frequency characteristics. Stacked polyester
or ceramic capacitors work well. Electrolytic capacitors are generally not suitable.
Because the reference is a high impedance node, and usually
there will be significant electrical noise near it, a bypass capacitor
between the reference pin and VSS is strongly recommended. The
reference buffer amplifier is intentionally compensated to be
stable with a capacitive load of 0.01 to 0.1µF.
A common resistor divider string is used to monitor VDD for both
the undervoltage lockout circuit and the shutoff circuit of the high
voltage FET. Setting the undervoltage sense point about 0.6V
lower on the string than the FET shutoff point guarantees that the
undervoltage lockout always releases before the FET shuts off.
Error Amplifier
The error amplifier is a true low-power differential input operational amplifier intended for around-the-amplifier compensation.
It is of mixed CMOS-bipolar construction: a PMOS input stage is
used so the common-mode range includes ground and the input
impedance is very high. This is followed by bipolar gain stages
which provide high gain without the electrical noise of all-MOS
amplifiers. The amplifier is unity-gain stable.
Bias Circuit
An external bias resistor, connected between the bias pin and VSS
is required to set currents in a series of current mirrors used by the
analog sections of the chip. Nominal external bias current requirement is 15 to 20µA, which can be set by a 390KΩ to 510KΩ
resistor if a 10V VDD is used, or a 510KΩ to 680KΩ resistor if a 12V
VDD is used. A precision resistor is NOT required; ± 5% is fine.
Current Sense Comparators
For extremely low power operation, the value of bias current can
be reduced to as low as 5µA by further increases in the value of
the bias resistor. This will reduce quiescent current by about a
third, reduce bandwidth of the error amp by about half, and slow
the current sense comparator by about 30%.
The HV910x uses a true dual comparator system with independent comparators for modulation and current limiting. This allows
the designer greater latitude in compensation design, as there are
no clamps (except ESD protection) on the compensation pin. Like
the error amplifier, the comparators are of low-noise BiCMOS
construction.
Clock Oscillator
The clock oscillator of the HV910x consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and, in
the 50% maximum duty cycle versions, a frequency dividing flipflop. A single external resistor between the OSC In and OSC Out
pins is required to set oscillator frequency (see Fig. 4). For the
50% maximum duty cycle versions the ‘Discharge’ pin is internally
connected to GND. For the 99% duty cycle version, ‘Discharge’
can either be connected to VSS directly or connected to VSS
through a resistor used to set a deadtime.
Remote Shutdown
One difference exists between the Supertex HV910x and competitive parts. The oscillator of the HV910x is shut off when a
shutoff command is received. This saves about 150µA of quiescent current, which aids in situations where an absolute minimum
of quiescent power dissipation is required.
The main switch is a normal N-channel power MOSFET. Unlike
the situation with competitive devices, the body diode can be used
if desired without destroying the chip.
The shutdown and reset pins can be used to perform either
latching or non-latching shutdown of a converter as required.
These pins have internal current source pull-ups so they can be
driven from open-drain logic. When not used, they should be left
open, or connected to VDD.
Main Switch
6
HV9100/HV9102/HV9103
BIAS
1
14
Feedback
+VIN
2
13
COMP
Drain
3
12
Reset
Source
4
11
Shutdown
–VIN
5
10
VREF
VDD
6
9
Discharge
OSC Out
7
8
OSC In
COMP
Reset
Shutdown
NC
VREF
Pinout
18
17
16
15
14
NC
19
13
NC
Feedback
20
12
Discharge
NC
1
11
OSC In
BIAS
2
10
OSC Out
+VIN
3
9
VDD
•
6
7
8
Source
–VIN
NC
5
Drain
4
14-pin DIP
NC
top view
top view
20-pin PJ Package
11/12/01
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
7
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com