HV9120 HV9123 High-Voltage Current-Mode PWM Controller Ordering Information +VIN Min Max Feedback Accuracy 10V 10V 450V 450V <±2% <±2% Max Duty Cycle 49% 99% Package Options 16 Pin 20 Pin SOIC Plastic PLCC HV9120NG HV9120PJ HV9123NG HV9123PJ 16 Pin Plastic DIP HV9120P HV9123P DIE HV9120X HV9123X Standard temperature range for all parts is industrial (-40° to +85°C). Features General Description ❏ 10 to 450V input acceptance range ❏ <1.3mA supply current ❏ >1.0MHz clock ❏ >20:1 dynamic range @ 500KHz ❏ Low internal noise The Supertex HV9120 and HV9123 are Switch Mode Power Supply (SMPS) controller subsystems that can start and run directly from almost any DC input, from a 12V battery to a rectified and filtered 240V AC line. They contain all the elements required to build a single-switch converter except for the switch, magnetic assembly, output rectifier(s) and filter(s). A unique input circuit allows the 912x to self-start directly from a high voltage input, and subsequently take the power to operate from one of the outputs of the converter it is controlling, allowing very efficient operation while maintaining input-to-output galvanic isolation limited in voltage only by the insulation system of the associated magnetic assembly. A ±2% internal bandgap reference, internal operational amplifier, very high speed comparator, and output buffer allow production of rugged, high performance, high efficiency power supplies of 50 watts or more, which can still be over 80% efficient at outputs of 1.0W or less. The wide dynamic range of the controller system allows designs with extremely wide line and load variations with much less difficulty and much higher efficiency than usual. The exceptionally wide input voltage acceptance range also allows much better usage of energy stored in input dropout capacitors than with other PWM ICs. Remote on/off controls allow either latching or nonlatching remote shutdown. During shutdown, power required is under 6.0mW. Applications ❏ Off-line high frequency power supplies ❏ Universal input power supplies ❏ High density power supplies ❏ Very high efficiency power supplies ❏ Extra wide load range power supplies Absolute Maximum Ratings Voltages are referenced to -VIN +VIN Input Voltage VDD Device Supply Voltage 450V 15.5V Logic Input Voltages -0.3 to VDD + 0.3V Linear Input Voltages -0.3 to VDD + 0.3V IIN Preregulator Input Current (continuous) 2.5mA Tj Operating Junction Temperature 150° C Storage Temperature -65°C to 150°C Power Dissipation, PDIP 1000mW Power Dissipation PLCC 1400mW Power Dissipation SOIC 900mW For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24. 11/12/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV9120/HV9123 Electrical Characteristics (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C.) Symbol Parameters Min Typ Max Unit Conditions 3.92 4.00 4.08 V RL = 10MΩ 3.84 4.00 4.16 15 30 45 KΩ 250 µA Reference VREF Output Voltage RL = 10MΩ, TA = -55°C to 125°C ZOUT Output Impedance1 ISHORT Short Circuit Current 125 ∆VREF Change in VREF with Temperature1 0.25 mV/°C MHz ROSC = 0Ω KHz ROSC = 330KΩ VREF = -VIN TA = -55°C to 125°C Oscillator fMAX Oscillator Frequency 1.0 3.0 fOSC Accuracy2 80 100 120 160 200 240 ∆VOSC TCOSC Initial Voltage Stability Temperature 15 Coefficient1 170 ROSC = 150KΩ % ppm/°C 9.5V < VDD <13.5V TA = -55°C to 125°C PWM DMAX Maximum Duty Cycle1 Deadtime1 DMIN HV9120 49.0 49.4 49.6 HV9123 95 97 99 HV9123 225 nsec Minimum Duty Cycle Minimum Pulse Width Before Pulse Drops Out 1 % 0 % 80 125 nsec 1.2 1.4 V VFB = 0V 80 150 ns VSENSE = 1.5V, VCOMP ≤ 2.0V 4.00 4.08 V VFB Shorted to Comp 25 500 nA VFB = 4.0V Current Limit Vlim td Maximum Input Signal Delay to 1.0 Output1 Error Amplifier VFB Feedback Voltage IIN Input Bias Current VOS Input Offset Voltage AVOL GB Open Loop Voltage Unity Gain 3.92 nulled during trim Gain1 Bandwidth1 60 80 dB 1.0 1.3 MHz see fig. 1 Ω Impedance1 ZOUT Output ISOURCE Output Source Current -1.4 -2.0 mA VFB = 3.4V ISINK Output Sink Current 0.12 0.15 mA VFB = 4.5V see fig. 2 dB PSRR Power Supply Rejection1 Notes: 1. Guaranteed by design. Not subject to production test. 2. Stray C on OSC IN pin must be ≤5pF. 2 HV9120/HV9123 Electrical Characteristics (continued) (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C.) Symbol Parameters Min Typ Max Unit Conditions Pre-regulator/Startup +VIN Input Voltage 450 V IIN < 10µA; VCC > 9.4V +IIN Input Leakage Current 10 µA VDD > 9.4V VTH VDD Pre-regulator Turn-off Threshold Voltage 8.0 8.7 9.4 V IPREREG = 10µA VLOCK Undervoltage Lockout 7.0 8.1 8.9 V 1.3 mA CL < 75pF Shutdown = -VIN Supply IDD Supply Current 0.75 IQ Quiescent Supply Current 0.55 mA IBIAS Nominal Bias Current 20 µA VDD Operating Range 9.0 13.5 V 100 ns Shutdown Logic tSD Shutdown Delay1 tSW Shutdown Pulse Width1 50 ns tRW RESET Pulse Width1 50 ns 25 ns 50 Width1 CL = 500pF, VSENSE = -VIN tLW Latching Pulse VIL Input Low Voltage VIH Input High Voltage IIH Input Current, Input Voltage High 1.0 5.0 µA VIN = VDD IIL Input Current, Input Voltage Low -25 -35 µA VIN = 0V V IOUT = 10mA 2.0 7.0 Shutdown and reset low V V Output VOH Output High Voltage VDD -0.25 VDD -0.3 VOL IOUT = 10mA, TA = -55°C to 125°C Output Low Voltage 0.2 V 0.3 ROUT tR tF Output Resistance Rise Fall IOUT = -10mA IOUT = -10mA, TA = -55°C to 125°C Ω IOUT = ±10mA Ω IOUT = ±10mA, Pull Up 15 25 Pull Down 8.0 20 Pull Up 20 30 Pull Down 10 30 30 75 ns CL = 500pF 20 75 ns CL = 500pF Time1 Time1 Note: 1. Guaranteed by design. Not subject to production test. 3 TA = -55°C to 125°C HV9120/HV9123 Truth Table Shutdown Reset H H Output H H→L L H Off, Not Latched L L Off, Latched L→H L Off, Latched, No Change Normal Operation Normal Operation, No Change Shutdown Timing Waveforms 1.5V tF ≤ 10ns VDD tR ≤ 10ns 50% Sense 50% Shutdown 0 0 td t SD VDD Output VDD 90% Output 0 90% 0 t SW VDD 50% Shutdown tR, tF ≤ 10ns 50% 0 t LW VDD Reset 50% 50% 50% 0 t RW Functional Block Diagram FB 15 (19) COMP Discharge 14 (18) 10 (12) OSC In OSC Out 9 8 (11) (10) Error Amplifier OSC – 11 (14) + VREF 2V Modulator Comparator – 4V 5 (6) Q S 9123 Output 9120 + Current Limit Comparator – BIAS To V DD Q R + REF GEN 16 (20) T Current Sources To Internal Circuits 6 (8) -V IN 1.2V 4 (5) Sense V DD 7 (9) VDD 1 (3) – +V IN 12 (16) Undervoltage Comparator Q 8.1V – + 13 (17) R + 8.6V Pre-regulator/Startup Pin number in parentheses are for PLCC package. 4 Shutdown S Reset HV9120/HV9123 Typical Performance Curves Error Amplifier Output Impedance (Z0) Fig. 1 10 Fig. 4 1M 6 Output Switching Frequency vs. Oscillator Resistance 105 104 10 fOUT (Hz) ZO (Ω) HV9123 3 102 HV9120 100k 10 1 1K 10K 100K 1M 10k 10k 10M 100 k Frequency (Hz) ROSC (Ω) PSRR — Error Amplifier and Reference Fig. 2 80 -10 70 -20 -30 Gain (dB) PSSR (dB) Error Amplifier Open Loop Gain/Phase Fig. 5 0 -40 -50 -60 -70 -80 110 60 180 50 120 40 60 30 0 20 -60 10 -120 0 -180 -10 100 1K 10K 100K 1M 100 1K 100K 10K Frequency (Hz) 1M Frequency (Hz) Fig. 3 Fig. 6 RDISCHARGE vs. tOFF (9123 only) 104 100 ROSC = 100K VDD = 12V VDD = 10V tOFF (nsec) Bias Current (µA) 1M 10 103 ROSC = 10K ROSC = 1K 1 105 106 102 10-1 107 100 101 102 103 RDISCHARGE (Ω) Bias Resistance (Ω) 5 104 105 106 Phase (°C) .1 100 HV9120/HV9123 Test Circuits PSRR Error Amp ZOUT 0.1V swept 10Hz – 1MHz +10V (VDD) 1.0V swept 100Hz – 2.2MHz 100K1% 60.4K – (FB) Reference GND (–VIN) 100K1% 10.0V + V1 Tektronix P6021 (1 turn secondary) 4.00V V2 Reference 40.2K 0.1µF V1 – + V2 0.1µF NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE ± 1mV before connecting transformer Detailed Description Preregulator The preregulator/startup circuit for the HV912x consists of a highvoltage n-channel depletion-mode DMOS transistor driven by an error amplifier to form a variable current path between the VIN terminal and the VDD terminal. Maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source (generally the supply the chip is controlling) no current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. the 50% maximum duty cycle versions, a frequency dividing flipflop. A single external resistor between the OSC In and OSC Out pins is required to set oscillator frequency (see graph). For the 50% maximum duty cycle versions the Discharge pin is internally connected to VSS (ground). For the 99% duty cycle version, Discharge can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One difference exists between the Supertex HV912x and competitive 912x’s: The oscillator is shut off when a shutoff command is received. This saves about 150µA of quiescent current, which aids in the construction of power supplies to meet CCITT specification I-430, and in other situations where an absolute minimum of quiescent power dissipation is required. An external capacitor between VDD and VSS is generally required to store energy used by the chip in the time between shutoff of the high voltage path and the VDD supply’s output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., Reference The Reference of the HV912x consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier when connected in a gain of –1 configuration is as close to 4.000V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. Cstorage ≥ 100 x (gate charge of FET at 10V ÷ 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor VDD for both the undervoltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout always releases before the FET shuts off. A ≈50KΩ resistor is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a low-impedance voltage source ≤6.0V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. In general, because the reference voltage of the Supertex HV912x is not noisy, as some previous examples have been, overriding the reference should seldom be necessary. Bias Circuit An external bias resistor, connected between the bias pin and VSS is required by the HV912x to set currents in a series of current mirrors used by the analog sections of the chip. Nominal external bias current requirement is 15 to 20µA, which can be set by a 390KΩ to 510KΩ resistor if a 10V VDD is used, or a 510kΩ to 680KΩ resistor if VDD will be 12V. A precision resistor is not required; ± 5% is fine. Because the reference of the 912x is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1µF. Clock Oscillator The clock oscillator of the HV912x consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in 6 HV9120/HV9123 Detailed Description (continued) Error Amplifier Remote Shutdown The error amplifier in the HV912x is a true low-power differential input operational amplifier intended for around-the-amplifier compensation. It is of mixed CMOS-bipolar construction: A PMOS input stage is used so the common-mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity-gain stable. The shutdown and reset pins of the HV912x can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open-drain logic. When not used they should be left open, or connected to VDD. Current Sense Comparators The output buffer of the HV912x is of standard CMOS construction (P-channel pull-up, N-channel pull-down). Thus the bodydrain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required. 16 BIAS NC 2 15 FB NC 3 14 COMP Sense 4 13 Reset Output 5 12 Shutdown –VIN 6 11 VREF VDD 7 10 Discharge OSC Out 8 9 OSC In VREF 1 NC +VIN Shutdown Pinout Reset The HV912x uses a true dual comparator system with independent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction. COMP Output Buffer 18 17 16 15 14 FB 19 13 NC BIAS 20 12 Discharge NC 1 11 OSC In NC 2 10 OSC Out +VIN 3 9 VDD • +VIN 1 16 BIAS 15 FB 14 COMP Sense 4 13 Reset Output 5 12 Shutdown –VIN 6 11 VREF VDD 7 10 Discharge OSC Out 8 9 OSC In 5 6 7 8 Output NC –VIN NC 4 Sense 16 Pin Dip Package top view 20-pin PJ Package top view 16 Pin SOIC top view Note: Pins 2 and 3 are removed 11/12/01 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com