White Electronic Designs WV3HG128M72EER-D7 ADVANCED* 1GB – 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM FEATURES DESCRIPTION 244-pin, dual in-line memory module (Mini-DIMM) Fast data transfer rates: PC2-6400*, PCS-5300*, PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 Mb/s DDR2 SDRAM components The WV3HG128M72EER is a 128Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of nine 128Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 244-pin DIMM FR4 substrate. VCC = VCCQ = 1.8V ±0.1V VCCSPD = 1.7V to 3.6V Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture * This product is under development, is not qualified or characterized and is subject to change without notice. Programmable CAS# latency (CL): 3, 4, 5* and 6* On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM JEDEC Standard 1.8V I/O (SSTL_18 Compatible) Gold (Au) edge contacts Sinlge Rank RoHS compliant Package option NOTE: Consult factory for availability of: • Vendor source control options • Industrial temperature option • 244 Pin Mini-DIMM • PCB – 30.00mm (1.181") TYP OPERATING FREQUENCIES PC2-3200 PC2-4200 PC2-5300* PC2-6400* Clock Speed 200MHz 266MHz 333MHz 400MHz CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 6-6-6 *Consult factory for availability. May 2006 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED PIN CONFIGURATION PIN NAMES Pin No. 1 Symbol VREF Pin No. 62 Symbol A4 Pin No. 123 Symbol VSS Pin No. 184 Symbol VCC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS NC VCC CKE0 VCC BA2 NC VCC A11 A7 VCC A5 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 VCC A2 VCC VSS VSS NC VCC A10/AP BA0 VCC WE# VCC CAS# VCC NC NC VCC NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SA0 SA1 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC VCC NC VCC NC NC VCC A12 A9 VCC A8 A6 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 A3 A1 VCC CK0 CK0# VCC A0 BA1 VCC RAS# VCC CS0# VCC ODT0 A13 VCC NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS SDA SCL VCCSPD Pin Name A0-A13 BA0-BA2 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0 CK0,CK0# CKE0 CS0# RAS# CAS# WE# RESET# DM (0-8) VCCSPD VCC VSS SA0-SA2 SDA SCL VREF NC Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination control Clock Inputs, positive line Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable Register Reset Input Data Masks SPD Power Voltage Supply (1.8V±0.1V) Ground SPD address SPD Data Input/Output Serial Presence Detect(SPD) Clock Input Input/Output Reference Spare pins, No connect RESET (pin 18) is connected to both OE of the PLL and Reset# of the register . May 2006 Rev. 0 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED FUNCTIONAL BLOCK DIAGRAM RCS0# DQS4 DQS4# DM4 DQS0 DQS0# DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ CS# DQS DQS# RDQS DM/ CS# DQS DQS# RDQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1# DM1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5# DM5 DM/ CS# DQS DQS# RDQS DM/ CS# DQS DQS# RDQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DQS2# DM2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6# DM6 DM/ CS# DQS DQS# RDQS DM/ CS# DQS DQS# RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7# DM7 DQS3 DQS3# DM3 DM/ CS# DQS DQS# RDQS DM/ CS# DQS DQS# RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS8 DQS8# DM8 VCCSPD DM/ CS# DQS DQS# RDQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS0# BA0-BA2 A0-A13 RAS# CAS# WE# CKE0 ODT0 RESET# PCK7#** R E G I S T E R I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 RCS0# CS#: SDRAMs RBA0-RBA2 BA0-BA2: SDRAMs RA0-RA13 A0-A13: SDRAMs RRAS# RAS# SDRAMs RCAS# CAS# SDRAMs RWE# WE# SDRAMs RCKE0 CKE SDRAMs RODT0 ODT SDRAMs SCL Serial PD WP A0 A1 SDA A2 Serial PD VCC\VCCQ DDR2 SDRAMs VREF DDR2 SDRAMs VSS DDR2 SDRAMs SA0 SA1 SA2 PCK0, PCK4-PCK6, PCK9 CK0 CK0# RESET#** P L L CK: SDRAMs PCK0# , PCK4#-PCK6#, PCK9# PCK7 PCK7# CK#: SDRAMs CK#: Register CK#: Register ** RESET#, CK AND CK# connects to both Registers. Other signals connct to one of two Registers. RST# PCK7** NOTE: All resistor values are 22 ohms ±5% unless otherwise specified. May 2006 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units VCC Voltage on VCC pin relative to VSS -0.5 2.3 V VIN, VOUT Voltage on any pin relative to VSS -0.5 2.3 V Storage Temperature -55 100 °C TSTG Command/Address, RAS#, CAS#, WE#, -5 5 µA IL Input leakage current; Any input 0V<VIN<VCC; VREF input 0V,VIN,0.95V; Other pins not under test = 0V CK, CK# -10 10 µA DM -5 5 µA IOZ Output leakage current; 0V<VIN<VCC; DQs and ODT are disable DQ, DQS, DQS# -5 5 µA -18 18 µA IVREF VREF leakage current; VREF = Valid VREF level DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Symbol Min Typical Max Unit Notes Supply Voltage VCC 1.7 1.8 1.9 V 3 I/O Reference Voltage VREF 0.49 x VCC 0.50 x VCC 0.51 x VCC V 1 VTT VREF-0.04 VREF VREF+0.04 V 2 VCCSPD 1.7 - 3.6 V I/O Termination Voltage SPD Supply Voltage Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC. INPUT/OUTPUT CAPACITANCE TA=25 0 C, f=1 00MHz Parameter Symbol Min Max Unit Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#) CIN1 11 12 pF Input capacitance ( CKE0), (ODT0) CIN2 11 12 pF Input capacitance (CS0#) CIN3 11 12 pF Input capacitance (CK0, CK0#) CIN4 10 11 pF Input capacitance (DM0 - DM8), (DQS0 - DQS8) Input capacitance (DQ0 - DQ63), (CB0 - CB7) May 2006 Rev. 0 4 CIN5 (665) 6.5 8 pF CIN5 (534,403) 6.5 7.5 pF COUT1 (665) 6.5 8 pF COUT1 (534,403) 6.5 7.5 pF White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED OPERATING TEMPERATURE CONDITION Parameter Operating temperature (Commercial) Symbol Rating Units Notes TOPER 0°C to 85°C °C 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51 .2 2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit Input High (Logic 1 ) Voltage VIH(DC) VREF + 0.125 VREF + 0.300 V Input Low (Logic 0) Voltage VIL(DC) -0.300 VREF - 0.125 V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit AC Input High (Logic 1 ) Voltage DDR2-400 & DDR2-533 VIH(AC) VREF + 0.250 — V AC Input High (Logic 1 ) Voltage DDR2-667 VIH(AC) VREF + 0.200 — V AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 VIL(AC) — VREF - 0.250 V AC Input Low (Logic 1 ) Voltage DDR2-667, DDR2-800(TBD) VIL(AC) — VREF - 0.200 V May 2006 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED DDR2 ICC SPECIFICATIONS AND CONDITIONS VCC = +1.8V ± 0.1V Symbol Parameter Operating one bank ICC0* activeprecharge; Operating one bank ICC1* activereadprecharge; Precharge powerICC2P** down current; Precharge quite ICC2Q** standby current; Precharge ICC2N** standby current; ICC3P** ICC3N** ICC4W* ICC4R* ICC5** ICC6** ICC7* Active powerdown current; Active standby current; Operating burst write current; Operating burst read current; Burst auto refresh current; Self refresh current; Operating bank interleave read current; Condition 806 665 534 403 Unit tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,210 1,165 1,120 mA IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data pattern is same as ICC4W. TBD 1,300 1,255 1,210 mA All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 508 508 508 mA All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 760 715 715 mA All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING TBD 805 760 760 mA TBD 670 625 625 mA TBD 508 508 508 mA TBD 850 805 805 mA TBD 1,795 1,570 1,435 mA TBD 1,795 1,570 1,435 mA TBD 2,380 2,335 2,290 mA TBD 90 90 90 mA TBD 3,100 2,920 2,740 mA Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; tCK = tCK(ICC), CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(ICC) - 1*tCK(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING Notes: ICC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition. May 2006 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED AC TIMING PARAMETERS VCC = +1.8V ± 0.1V 806 Parameter Data Strobe Data Clock Clock cycle time 665 534 403 Symbol Unit Min Max Min Max Min Max Min Max CL=6 tCK(6) TBD TBD CL=5 tCK(5) TBD TBD 3000 8000 - - - - ps CL=4 tCK(4) TBD TBD 3750 8000 3,750 8,000 5,000 8,000 ps CL=3 tCK(3) TBD TBD 5000 8000 5,000 8,000 5,000 8,000 ps CK high-level width tCH TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK Half clock period tHP TBD TBD MIN(tCH, tCL) Clock jitter tJIT TBD TBD -125 -450 MIN (tCH, tCL) 125 -125 +450 -500 MIN (tCH, tCL) 125 -125 +500 -600 DQ output access time from CK/CK# tAC TBD TBD Data-out high impedance window from CK/CK# tHZ TBD TBD Data-out low-impedance window from CK/CK# tLZ TBD TBD DQ and DM input setup time relative to DQS tDS TBD TBD 100 100 150 DQ and DM input hold time relative to DQS tDH TBD TBD 175 225 275 0.35 ps 125 ps +600 ps tAC(MAX) ps tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) ps tAC(MAX) tAC(MAX) DQ and DM input pulse width (for each input) tDIPW TBD TBD Data hold skew factor tQHS TBD TBD DQ-DQS hold, DQS to first DQ to go nonvalid, per access tQH TBD TBD tHP - tQHS tHP - tQHS tHP - tQHS ps Data valid output window (DVW) tDVW TBD TBD tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns DQS input high pulse width tDQSH TBD TBD 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL TBD TBD 0.35 DQS output access time from CK/CK# tDQSCK TBD TBD -400 DQS falling edge to CK rising - setup time tDSS TBD TBD 0.2 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH TBD TBD 0.2 0.2 0.2 tCK DQS-DQ skew, DOS to last DQ valid, per group, per access tDQSQ TBD TBD DQS read preamble tRPRE TBD TBD 0.9 1.1 0.9 1.1 DQS read postamble tRPST TBD TBD 0.4 0.6 0.4 0.6 DQS write preamble setup time tWPRES TBD TBD 0 DQS write preamble tWPRE TBD TBD 0.35 DQS write postamble tWPST TBD TBD 0.4 Write command to first DQS latching transition tDQSS TBD TBD 0.35 340 0.35 400 0.35 +400 -450 240 0.35 +450 -500 300 0 0.4 ps 350 ps 0.9 1.1 tCK 0.4 0.6 tCK ps 0.35 0.6 ps tCK +500 0 0.35 0.6 tCK 450 0.4 tCK 0.6 WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK tCK AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. May 2006 Rev. 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED AC TIMING PARAMETERS (continued) VCC = +1.8V ± 0.1V Power-Down ODT Self Refresh Command and Address Parameter 806 Symbol Address and control input pulse width for each input Address and control input setup time Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK, CK# uncertainty REFRESH to Active or Refresh to Refresh command interval Average periodic refresh interval tDELAY tRFC tREFI Exit self refresh to non-READ command Min tIPW tIS tIH tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD 665 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tXSNR TBD TBD Exit self refresh to READ Exit self refresh timing reference ODT turn-on delay tXSRD tlSXR tAOND TBD TBD TBD TBD TBD TBD ODT turn-on tACN TBD TBD ODT turn-off delay tAOFD TBD TBD ODT turn-off tAOF TBD TBD ODT turn-on (power-down mode) tAONPD TBD TBD ODT turn-off (power-down mode) tAOFPD TBD TBD ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any non-READ command CKE minimum high/low time tANPD tAXPD tXARD tXARDS tXP tCKE TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 534 403 Min Max Min Max Min Max 0.6 0.6 0.6 200 250 250 275 375 475 2 2 2 55 55 55 7.5 7.5 7.5 15 15 15 37.5 37.5 37.5 40 70,000 40 70,000 40 70,000 7.5 7.5 7.5 15 15 15 tWR + tRP tWR + tRP tWR + tRP 7.5 7.5 10 15 15 15 tRP + tCK tRP + tCK tRP + tCK 2 2 2 tIS+tCK+tIH tIS+tCK+tIH tIS+tCK+tIH 127.5 70,000 127.5 70,000 127.5 70,000 7.8 7.8 7.8 tRFC(MIN) tRFC(MIN) tRFC(MIN) + 10 + 10 + 10 200 200 200 tIS tIS tIS 2 2 2 2 2 2 tAC(MAX) tAC(MAX) tAC(MAX) tAC(MIN) tAC(MIN) tAC(MIN) + 1000 + 1000 + 1000 2.5 2.5 2.5 2.5 2.5 2.5 tAC(MAX) tAC(MAX) tAC(MAX) + tAC(MIN) + tAC(MIN) + tAC(MIN) 600 600 600 2 x tCK + 2 x tCK + 2 x tCK + tAC(MIN) + tAC(MIN) + tAC(MIN) + tAC(MAX) tAC(MAX) tAC(MAX) 2000 2000 2000 + 1000 + 1000 + 1000 2.5 x 2.5 x 2.5 x tAC(MIN) + tCK + tAC(MIN) + tCK + tAC(MIN) + tCK + 2000 tAC(MAX) + 2000 tAC(MAX) + 2000 tAC(MAX) 1000 1000 + 1000 3 3 3 8 8 8 2 2 2 7-AL 6-AL 6-AL 2 2 2 3 3 3 Unit tCK ps ps ps ns ns ns ns ns ns ns ns ns ns ns tCK ns ns µs ns tCK ps tCK ps tCK ps ps ps tCK tCK tCK tCK tCK tCK AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. May 2006 Rev. 0 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED ORDERING INFORMATION FOR D7 Clock Speed/ Data Rate CAS Latency tRCD tRP Height* WV3HG128M72EER806D7xxG** 400MHz/800Mb/s 6 6 6 30.00mm (1.181") TYP WV3HG128M72EER665D7xxG** 333MHz/667Mb/s 5 5 5 30.00mm (1.181") TYP WV3HG128M72EER534D7xxG 266MHz/533Mb/s 4 4 4 30.00mm (1.181") TYP WV3HG128M72EER403D7xxG 200MHz/400Mb/s 3 3 3 30.00mm (1.181") TYP Part Number ** Contact factory for availability. NOTES: • RoHS product. (“G” = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case“x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D7 FRONT VIEW 3.80 (0.150) MAX 82.15 (3.234) 81.15 (3.222) 4.10 (0.161) 3.90 (0.154) 2.10 (0.083) 1.90 (0.075) 30.15 (1.187) 29.85 (1.175) 20.0 (0.787) TYP 1.80 (0.071) D X2 10.0 (0.394) TYP 6.0 (0.236) TYP 0.50 (0.02) R 1.0 (0.039) TYP 2.0 (0.079) TYP PIN 122 PIN 1 1.10 (0.043) MAX 42.90 (1.689) TYP 78.0 (3.071) TYP 3.60 (0.142) FULL R BACK VIEW 3.80 ±0.10 (0.150 ±0.004) 1.30 (0.051) 1.00 ±0.05 (0.039 ±0.002) Detail A 3.3 (0.130) TYP 0.60 TYP (0.024)TYP 3.6 (0.142) TYP PIN 244 33.6 (1.323) TYP 3.2 (0.126) TYP 0.25 (0.010) MAX 2.55 (0.100) 38.4 (1.512) TYP Detail A 0.45±0.03 (0.018 ±0.001) PIN 123 Detail B Detail B Tolerances: + /- 0.13 (0.005) unless otherwise specified. * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) May 2006 Rev. 0 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED PART NUMBERING GUIDE WV 3 H G 128M 72 E E R xxx D7 x x G WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH (x8) 1.8V REGISTERED SPEED (Mb/s) PACKAGE 244 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT May 2006 Rev. 0 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG128M72EER-D7 ADVANCED Document Title 1GB – 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM DRAM DIE OPTIONS: • SAMSUNG: B-Die • MICRON: U28A:A: will move to U38z:D Q4'06 and U488:E Q2'07 Revision History Rev # History Release Date Status Rev 0 Created May 2006 Advanced May 2006 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com