White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY* 512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM FEATURES DESCRIPTION 244-pin, dual in-line memory module (Mini-DIMM) Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM components The WV3HG64M72EER is a 64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of nine 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 244-pin DIMM FR4 substrate. VCC = VCCQ = 1.8V ±0.1V VCCSPD = 1.7V to 3.6V Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture * This product is under development, is not qualified or characterized and is subject to change without notice. Programmable CAS# latency (CL): 3, 4, 5 and 6 On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Auto and Self Refresh Capability (64ms: 8,192 cycle refresh) Gold (Au) edge contacts RoHS compliant Single Rank Package option NOTE: Consult factory for availability of: • Vendor source control options • Industrial temperature option • 244 Pin Mini-DIMM • PCB – 30.00mm (1.181") TYP OPERATING FREQUENCIES PC2-3200 PC2-4200 PC2-5300* PC2-6400* Clock Speed 200MHz 266MHz 333MHz 400MHz CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 6-6-6 *Consult factory for availability. February 2006 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY PIN CONFIGURATION PIN NAMES Pin No. 1 Symbol VREF Pin No. 62 Symbol A4 Pin No. 123 Symbol VSS Pin No. 184 Symbol VCCQ 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS NC VCCQ CKE0 VCC NC NC VCCQ A11 A7 VCC A5 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 VCCQ A2 VCC VSS VSS NC VCC A10/AP BA0 VCC WE# VCCQ CAS# VCCQ NC NC VCCQ NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SA0 SA1 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC VCCQ *CKE1 VCC NC NC VCCQ A12 A9 VCC A8 A6 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 A3 A1 VCC CK0 CK0# VCC A0 BA1 VCC RAS# VCCQ CS0# VCCQ ODT0 A13 VCC NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS SDA SCL VCCSPD Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0 CK0,CK0# CKE0 CS0# RAS# CAS# WE# RESET# DM (0-8) VCCSPD VCC VCCQ A10/AP VSS SA0-SA2 SDA SCL NC VREF Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination control Clock Inputs, positive line Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable Register Reset Input Data Masks SPD Power Core and I/O Power (1.8V) I/O Power (1.8V) Address Input/Auto Precharge Ground SPD address SPD Data Input/Output Serial Presence Detect(SPD) Clock Input Spare pins, No connect Input/Output Reference RESET (pin 18) is connected to both OE of the PLL and Reset# of the register . February 2006 Rev. 2 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY FUNCTIONAL BLOCK DIAGRAM RCS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS# DQS DQS# DQS1 DQS1# DM1 DQS5 DQS5# DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQS2 DQS2# DM2 DQS6 DQS6# DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQS3 DQS3# DM3 DQS7 DQS7# DM7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS# DQS DQS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS8 DQS8# DM8 VCCSPD ODT0 1:1 R E G I S T E R RESET# RST# CS0# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 Serial PD VCC/VCCQ DDR SDRAMs VREF DDR SDRAMs VSS DDR SDRAMs Serial PD SCL RCS0# CS# DDR SDRAMs SDA WP A0 A1 A2 RBA0 - RBA1 BA0 - BA1 DDR SDRAMs RA0 - RA13 A0 - A13 DDR SDRAMs SA0 SA1 SA2 RRAS# RAS# DDR SDRAMs RCAS# RCAS# DDR SDRAMs RWE# WE# DDR SDRAMs CK0 RCKE0 CKE0 DDR SDRAMs RODT0 ODT0 DDR SDRAMs P PCK0, PCK4 - PCK6, PCK8, PCK9 CK : DDR SDRAMs L CK0# RESET# PCK7 L OE PCK0#, PCK4# - PCK6#, PCK8#, PCK9# CK# : DDR SDRAMs PCK7 CK : Register PCK7# CK# : Register PCK7# NOTE: All resistor values are 22 ohms ±5% unless otherwise specified. February 2006 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage VCCL Supply voltage I/O Reference voltage I/O Termination voltage Symbol VCC VCCQ VCCL VREF VTT Min 1 .7 1 .7 1 .7 0.49 x VCCQ VREF-0.04 Typical 1 .8 1 .8 1 .8 0.50 x VCCQ VREF Max 1 .9 1 .9 1 .9 0.51 x VCCQ VREF + 0.04 Unit V V V V V Notes 1 4 4 2 3 Notes: 1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC; VCCL track with VCC. ABSOLUTE MAXIMUM RATINGS Symbol VCC VCCQ VCCL VIN, VOUT TSTG TCASE IL IOZ IVREF Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on VCCL pin relative to VSS Voltage on any pin relative to VSS Storage temperature Device operating temperature Input leakage current; Any input 0V<VIN<VCC; VREF input 0V<VIN<0.95V; Other pins not under test = 0V Output leakage current; 0V<VOUT<VCCQ; DQs and ODT are disable VREF leakage current; VREF = Valid VREF level MIN -1.0 -0.5 -0.5 -0.5 -55 0 MAX 2.3 2.3 2.3 2.3 100 85 Unit V V V V °C °C Command/Address, RAS#, CAS#, WE#, CS#, CKE CK, CK# DM -5 5 µA -10 -5 10 5 µA µA DQ, DQS, DQS# -5 5 µA -18 18 µA INPUT/OUTPUT CAPACITANCE TA=25 0 C, f=1 00MHz Parameter Symbol Min Max Unit Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#) CIN1 6.5 7.5 pF Input capacitance ( CKE0), (ODT0) CIN2 6.5 7.5 pF Input capacitance (CS0#) CIN3 6.5 7.5 pF Input capacitance (CK0, CK0#) CIN4 6 7 pF CIN5 6.5 8 pF COUT1 6.5 8 pF Input capacitance (DM0 - DM8), (DQS0 - DQS8) Input capacitance (DQ0 - DQ63), (CB0 - CB7) February 2006 Rev. 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY OPERATING TEMPERATURE CONDITION Parameter Operating temperature Symbol Rating Units Notes TOPER 0 to 85 °C 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51 .2 2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit Input High (Logic 1 ) Voltage VIH(DC) VREF + 0.1 25 VREF + 0.300 V Input Low (Logic 0) Voltage VIL(DC) -0.300 VREF - 0.125 V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit AC Input High (Logic 1 ) Voltage VIH(AC) VREF + 0.250 — V AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 (DDR2-667 & DDR2-806) TBD VIL(AC) — VREF - 0.250 V February 2006 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY DDR2 ICC SPECIFICATIONS AND CONDITIONS Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V Symbol Parameter ICC0* Operating one bank active-precharge; ICC1* ICC2P** ICC2Q** ICC2N** ICC3P** Operating one bank active-readprecharge; Precharge powerdown current; Precharge quite standby current; Precharge standby current; Active power-down current; ICC3N** Active standby current; ICC4W* Operating burst write current; ICC4R* Operating burst read current; ICC5** Burst auto refresh current; ICC6** Self refresh current; ICC7* Operating bank interleave read current; Condition tCK = tCK(DD); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data pattern is same as ICC4W. All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Fast PDN Exit All banks open; tCK = tCK(ICC), CKE is LOW; Other control MRS(12) = 0 and address bus inputs are STABLE; Data bus inputs are Slow PDN Exit FLOATING MRS(12) = 1 All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING CK and CK# at 0V; CKE < 0.2V; Other control and address Normal bus inputs are FLOATING; Data bus inputs are FLOATING All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(ICC) - 1*tCK(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING 806 665 534 403 Unit TBD TBD 1120 1120 mA TBD TBD 1255 1255 mA TBD TBD 472 472 mA TBD TBD 670 670 mA TBD TBD 715 715 mA TBD TBD 670 670 mA TBD TBD 508 508 mA TBD TBD 850 850 mA TBD TBD 1480 1390 mA TBD TBD 1525 1390 mA TBD TBD 1660 1660 mA TBD TBD 472 472 mA TBD TBD 2380 2380 mA Notes: ICC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition. February 2006 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY AC TIMING PARAMETERS 0°C ≤ TCASE < +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V 806 Parameter Data Strobe Data Clock Clock cycle time 665 534 403 Symbol Unit Min Max Min Max Min Max Min Max CL=6 tCK(6) TBD TBD TBD TBD ps CL=5 tCK(5) TBD TBD TBD TBD CL=4 tCK(4) TBD TBD TBD TBD 3,750 8,000 5,000 8,000 CL=3 ps ps tCK(3) TBD TBD TBD TBD 5,000 8,000 5,000 8,000 ps CK high-level width tCH TBD TBD TBD TBD 0.45 0.55 0.45 0.55 tCK CK low-level width tCL TBD TBD TBD TBD 0.45 0.55 0.45 0.55 tCK MIN (tCH, tCL) ps TBD ps Half clock period tHP TBD TBD TBD TBD MIN (tCH, tCL) Clock jitter tJIT TBD TBD TBD TBD TBD DQ output access time from CK/CK# tAC TBD TBD TBD TBD -500 Data-out high impedance window from CK/CK# tHZ TBD TBD TBD TBD Data-out low-impedance window from CK/CK# tLZ TBD TBD TBD TBD tAC(MN) DQ and DM input setup time relative to DQS tDS TBD TBD TBD TBD 100 DQ and DM input hold time relative to DQS +500 -600 tAC(MAX) tAC(MAX) tAC(MN) +600 ps tAC(MAX) ps tAC(MAX) ps 150 tQH TBD TBD TBD TBD 225 275 DQ and DM input pulse width (for each input) tDIPW TBD TBD TBD TBD 0.35 0.35 Data hold skew factor tQHS TBD TBD TBD TBD DQ-DQS hold, DQS to first DQ to go nonvalid, per access tHQ TBD TBD TBD TBD tHP - tQHS tHP - tQHS tCK 400 450 ps ps Data valid output window (DVW) tDVW TBD TBD TBD TBD tQH - tDQSQ tQH - tDQSQ ns DQS input high pulse width tDQSH TBD TBD TBD TBD 0.35 0.35 tCK DQS input low pulse width tDQSL TBD TBD TBD TBD 0.35 DQS output access time from CK/CK# tDQSCK TBD TBD TBD TBD -450 0.35 +450 -500 tCK +500 Ps DQS falling edge to CK rising - setup time tDSS TBD TBD TBD TBD 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH TBD TBD TBD TBD 0.2 0.2 tCK O DQS-DQ skew, DOS to last DQ valid, per group, per access tDQSQ TBD TBD TBD TBD 300 350 ps DQS read preamble tRPRE TBD TBD TBD TBD 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST TBD TBD TBD TBD 0.4 0.6 0.4 0.6 tCK DQS write preamble setup time tWPRES TBD 0 TBD TBD TBD DQS write preamble tWPRE TBD TBD TBD TBD 0.35 DQS write postamble tWPST TBD TBD TBD TBD 0.4 Write command to first DQS latching transition tDQSS TBD TBD TBD TBD AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. February 2006 Rev. 2 7 0 ps 0.35 0.6 0.4 tCK 0.6 WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK tCK Continued on next page White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY AC TIMING PARAMETERS (continued) Power-Down ODT Self Refresh Command and Address 0°C ≤ TCASE < +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V Parameter Symbol Address and control input pulse width for each input Address and control input setup time Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK, CK# uncertainty REFRESH to Active or Refresh to Refresh command interval Average periodic refresh interval tIPW tIS tIH tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD 806 Min 665 Max Min 534 Max TBD TBD TBD TBD tDELAY TBD TBD TBD TBD Min 0.6 250 375 2 60 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP + tCK 2 4.375 tRFC TBD TBD TBD TBD 127.5 tREFI TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Exit self refresh to non-READ command tXSNR TBD Exit self refresh to READ Exit self refresh timing reference ODT tum-on delay tXSRD tlSXR tAOND TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ODT turn-on tACN TBD TBD TBD TBD ODT turn-off delay tAOFD TBD TBD TBD TBD ODT turn-off tAOF TBD TBD TBD TBD ODT turn-on (power-down mode) tAONPD TBD TBD TBD TBD ODT turn-off (power-down mode) tAOFPD TBD TBD TBD TBD ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any non-READ command CKE minimum high/low time tANPD tAXPD tXARD tXARDS tXP tCKE TBD TBD TBD TBD TBD TBD TBD 403 Max 37.5 70,000 37.5 70,000 70,000 127.5 70,000 ns 7.8 ns 7.8 tRPC(MIN) + 10 200 tIS 2 2 tAC(MAX) + tAC(MIN) 1000 2.5 2.5 tAC(MAX) + tAC(MIN) 600 2 x tCK + tAC(MIN) + tAC(MAX) + 2000 1000 +1000 2 x tCK + tAC(MIN) + tAC(MAX) + 2000 1000 +1000 3 8 2 6-AL 2 3 tRFC(MIN) + 10 200 tIS 2 Max Unit Min 0.6 250 475 2 65 7.5 15 37.5 45 7.5 15 tWR + tRP 10 15 tRP + tCK 2 4.375 2 tAC(MAX) + tAC(MIN) 1000 2.5 2.5 tAC(MAX) + tAC(MIN) 600 2 x tCK + tAC(MIN) + tAC(MAX) + 2000 1000 2 x tCK + tAC(MIN) + tAC(MAX) + 2000 1000 3 8 2 6-AL 2 3 tCK ps ps ps ns ns ns ns ns ns ns ns ns ns ns tCK ns ns tCK ps tCK ps tCK ps ps ps tCK tCK tCK tCK tCK tCK AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. February 2006 Rev. 2 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY ORDERING INFORMATION FOR D7 Clock Speed/ Data Rate CAS Latency tRCD tRP Height* WV3HG64M72EER806D7xG 400MHz/800Mb/s 6 6 6 30.00mm (1.181") TYP WV3HG64M72EER665D7xG 333MHz/667Mb/s 5 5 5 30.00mm (1.181") TYP WV3HG64M72EER534D7xG 266MHz/533Mb/s 4 4 4 30.00mm (1.181") TYP WV3HG64M72EER403D7xG 200MHz/400Mb/s 3 3 3 30.00mm (1.181") TYP Part Number NOTES: • Consult Factory for availability of RoHS products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D7 FRONT VIEW 3.80 (0.150) MAX 82.00 (3.228) 2.00(0.079) R X2 30.00 (1.181) TYP 1.00 (0.039) R X2 20.0 (0.787) TYP 1.80 (0.071) D X2 10.0 (0.394) TYP 6.0 (0.236) TYP (1.10) 0.043 0.50 (0.02) R 1.0 (0.039) TYP 2.0 (0.079) TYP PIN 122 PIN 1 42.90 (1.689) TYP 78.0 (3.071) TYP 3.60 (0.142) FULL R BACK VIEW 3.80 ±0.10 (0.150 ±0.004) 1.30 (0.051) 1.00 ±0.05 (0.039 ±0.002) Detail A 3.3 (0.130) TYP 0.60 (0.024) 3.6 (0.142) TYP PIN 244 33.6 (1.323) TYP 3.2 (0.126) TYP 0.25 (0.010) MAX 2.55 (0.100) 38.4 (1.512) TYP Detail A 0.45±0.03 (0.018 ±0.001) PIN 123 Detail B Detail B Tolerances: + /- 0.13 (0.005) unless otherwise specified. * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) February 2006 Rev. 2 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY PART NUMBERING GUIDE WV 3 H G 64M 72 E E R xxx D7 x G WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH (x8) 1.8V REGISTERED SPEED (Mb/s) PACKAGE 244 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT February 2006 Rev. 2 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG64M72EER-D7 PRELIMINARY Document Title 512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM Revision History Rev # History Release Date Status Rev 0 Created August 2005 Advanced Rev 1 1.0 Updated CAP, ICC and AC specs. September 2005 Preliminary February 2006 Preliminary 1.1 Changed from Advanced to Preliminary Rev 2 2.0 Update ICC specs 2.1 Added DDR2-667 & DDR2-800 as TBD February 2006 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com