White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED*
128MB – 32Mx40 DDR2 SDRAM UNBUFFERED, ECC, w/PLL
FEATURES
DESCRIPTION
Unbuffered 200-pin, Small-Outline DIMM (SODIMM)
The WV3HG32M40SEU is a 32Mx40 Double Data Rate 2
SDRAM memory module based on 512Mb DDR2 SDRAM
components. The module consists of three 32Mx16, in
FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
Suppot ECC error detection and correction
Fast data transfer rates: PC2-5300*, PC2-4200 and
PC2-3200
Utilizes 667*, 533 and 400 Mb/s DDR2 SDRAM
components
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
VCC = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Differential clock inputs (CK, CK#)
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, and 5
Posted CAS# additive latency; 0, 1, 2, 3 and 4
Programmable burst: length (4, 8)
On-die termination (ODT)
On memory PLL clock
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
RoHS Compliant
JEDEC proposed Pin-out
Package option:
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-5300*
PC2-4200
PC2-3200
Clock Speed
333MHz
266MHz
200MHz
CL-tRCD-tRP
5-5-5
4-4-4
3-3-3
Note:
• Consult factory for availability
June 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
June 2006
Rev. 2
Symbol
VREF
VSS
DQ0
DQ4
VSS
DQ5
DQ1
VSS
DQS0#
DM0
DQS0
VSS
VSS
DQ6
DQ2
DQ7
DQ3
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DM1
DQS1#
VSS
DQS1
DQ14
VSS
DQ15
DQ10
VSS
DQ11
DQ20
VSS
DQ21
DQ16
VSS
DQ17
NC
VSS
DM2
DQS2#
VSS
DQS2
DQ22
VSS
DQ23
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
DQ18
VSS
DQ19
DQ28
VSS
DQ29
DQ24
VSS
DQ25
DM3
VSS
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
VSS
DQ26
CB4
DQ27
CB5
VSS
VSS
CB0
DM8
CB1
VSS
VSS
CB6
DQS8#
CB7
DQS8
VSS
VSS
CB2
CKE0
CB3
NC
VSS
NC
NC
VCC
NC
A12
A11
A9
VCC
A7
A8
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
VCC
A6
A5
A4
A3
VCC
A2
A1
VCC
A0
A10/AP
BA1
BA0
VCC
RAS#
WE#
VCC
CS0#
CAS#
ODT0
NC
NC
VCC
VCC
NC
CK
NC
CK#
NC
VSS
VSS
NC
NC
NC
NC
VSS
NC
NC
VSS
VSS
NC
NC
NC
NC
VSS
VSS
NC
NC
NC
NC
PIN NAMES
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
VSS
VSS
NC
NC
NC
VSS
VSS
NC
NC
NC
NC
VSS
VSS
NC
NC
NC
NC
VSS
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
NC
SDA
VSS
SCL
NC
SA1
VCCSPD
SA0
SYMBOL
A0-A12
ODT0
CK, CK#
CB0 - CB7
CKE0
CS0#
RAS#, CAS#, WE#
BA0, BA1
DM0-DM3, DM8
DQ0-DQ31
DQS0-DQS3,
DQS8
DQS03-DQS3#,
DQS8#
SCL
SA0-SA1
SDA
VCC
VREF
VSS
VCCSPD
NC
2
DESCRIPTION
Address input
On-Die Termination
Clock Input
Check Bits
Clock Enable input
Chip select
Command Inputs
Bank Address Inputs
Input Data Mask
Data Input/Output
Data Strobe
Data Strobe Complement
SPD Clock Input
SPD Address Inputs
Serial Data Input/Output
Power Supply
Input/Output reference voltage
Ground
Serial EEPROM Power Supply
No Connect
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DQS0#
DM0
DQS1
DQS1#
DM1
DQS2
DQS2#
DM2
DQS3
DQS3#
DM3
DQS8
DQS8#
DM8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
DQS
DQS#
DM/RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM/RDQS
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DQS#
DM/RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM/RDQS
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS
DQS
DQS#
DM/RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS#
DM/RDQS
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS0#
BA0-BA1
A0-A12
RAS#
CAS#
WE#
CKE0
ODT0
CK
CK#
CS0# → CS#: DDR2 SDRAMs
BA0-BA1 → BA0-BA1: DDR2 SDRAMs
A0-A12 → A0-A12: DDR2 SDRAMs
RAS# → RAS#: DDR2 SDRAMs
CAS# → CAS#: DDR2 SDRAMs
WE# → WE#: DDR2 SDRAMs
CKE0 → CKE: DDR2 SDRAMs
ODT0 → ODT: DDR2 SDRAMs
PCK0-PCK2 → CK: DDR2 SDRAMs
P
L
L
PCK0# → PCK2# → CK#: DDR2 SDRAMs
SCL
June 2006
Rev. 2
3
A1
A2
SDA
SA0 SA1
VCCSPD
NOTE: All resistor value, are 22 ohms ± 5% unless otherwise specified.
Serial PD
WP A0
Serial PD
VCC
DDR2 SDRAMs
VREF
DDR2 SDRAMs
VSS
DDR2 SDRAMs
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
VCC
Voltage on VCC pin relative to VSS
-0.5
2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
-0.5
2.3
V
TSTG
Storage Temperature
-55
100
˚C
Command/Address,
RAS#, CAS#, WE#
-15
15
µA
CS#, CKE
-15
15
µA
CK, CK#
-10
10
µA
DM
-5
5
µA
DQ, DQS, DQS#
-5
5
µA
-6
6
µA
IL
IOZ
IVREF
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
Output leakage current; 0V<VIN<VCC; DQs and ODT are
disable
VREF leakage current; VREF = Valid VREF level
DC OPERATING CONDITIONS
All voltages referenced to VSS
Rating
Parameter
Symbol
Min.
Type
Max.
Units
Notes
Supply Voltage
VCC
1.7
1.8
1.9
V
3
I/O Reference Voltage
VREF
0.49 x VCC
0.50 x VCC
0.51 x VCC
V
1
VTT
VREF-0.04
VREF
VREF+0.04
V
2
VCCSPD
1.7
-
3.6
V
I/O Termination Voltage
SPD Supply Voltage
Notes:
1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. VCCQ of all IC's are tied to VCC.
June 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Symbol
Min
Max
Units
Input Capacitance (A0~A12, BA0~BA1, RAS#, CAS#, WE#)
CIN1
7
10
pF
Input Capacitance CKE0, ODT0
CIN2
7
10
pF
Input Capacitance CS0#
CIN3
7
10
pF
Input Capacitance (CK, CK#)
CIN4
6
7
pF
CIN5 (665)
6.5
7.5
pF
Input Capacitance (DM0 ~ DM3, DM8), (DQS0 ~ DQS3, DQS8)
Input Capacitance (DQ0 ~ DQ31) (CB0 ~ CB7)
CIN5 (534)
6.5
8
pF
COUT1 (665)
6.5
7.5
pF
COUT1 (534)
6.5
8
pF
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature (Commercial)
TOPER
0° to 85°
°C
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Units
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VCC + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Symbol
Min
Max
Units
Input High (Logic 1) Voltage DDR2-400 & DDR2-533
VIH(AC)
VREF + 0.250
-
V
Input Low (Logic 1) Voltage DDR2-667
VIH(AC)
VREF + 0.200
-
V
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
VIL(AC)
-
VREF - 0.250
V
Input Low (Logic 0) Voltage DDR2-667
VIL(AC)
-
VREF - 0.200
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
June 2006
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
DDR2 ICC SPECIFICATION AND CONDITIONS
Symbol
ICC0*
ICC1*
ICC2P**
ICC2Q**
ICC2N**
ICC3P**
ICC3N**
ICC4W*
ICC4R*
ICC5**
ICC6**
ICC7*
Proposed Conditions
665
534
403
Units
Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
660
630
615
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as ICC4W
720
690
675
mA
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
330
330
324
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
390
375
360
mA
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
405
390
375
mA
Fast PDN Exit MRS(12) = 0
405
390
330
mA
Slow PDN Exit MRS(12) = 1
360
360
360
mA
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
480
450
450
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
990
885
780
mA
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
990
885
780
mA
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,110
1,050
990
mA
18
18
18
mA
1,725
1,470
1,245
mA
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
ICC specification is based on ELPIDA components. Other DRAM manufactures specification may be different.
Note:
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
June 2006
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
665
PARAMETER
Data
403
SYMBOL
tCK (5)
tCK (4)
tCK (3)
MIN
3,000
3,750
5,000
MAX
8,000
8,000
8,000
MIN
MAX
MIN
MAX
3,750
5,000
8,000
8,000
5,000
5,000
8,000
8,000
UNIT
ps
ps
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.55
0.45
MIN (tCH,
tCL)
-125
-600
0.55
tCK
tHP
0.45
MIN (tCH,
tCL)
-125
-500
0.55
Half clock period
0.45
MIN (tCH,
tCL)
-125
-450
Clock Cycle Time
Data Strobe
534
CL = 5
CL = 4
CL = 3
Clock jitter
DQ output access time from CK/CK#
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go nonvalid, per
access
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
DQS…DQ skew, DQS to last DQ valid, per group,
per access
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
t JIT
tAC
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
tWPRES
tWPRE
tWPST
Write command to first DQS latching transition
tDQSS
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
Address and control input hold time
tIPW
tIS
tIH
tCCD
tAC MIN
100
175
0.35
125
+450
tAC MAX
tAC MAX
tAC MIN
100
225
0.35
340
125
+500
tAC MAX
tAC MAX
tAC MIN
150
275
0.35
400
ps
125
+600
tAC MAX
tAC MAX
450
ps
ps
ps
ps
ps
ps
tCK
ps
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tQH - tDQSQ
0.35
0.35
-400
0.2
0.2
tQH - tDQSQ
0.35
0.35
-450
0.2
0.2
tQH - tDQSQ
0.35
0.35
-500
0.2
0.2
ns
tCK
tCK
ps
tCK
tCK
tDQSQ
tRPRE
tRPST
+400
240
0.9
0.4
0
0.35
0.4
WL
- 0.25
1.1
0.6
0.6
WL +
0.25
0.6
200
275
2
+450
300
0.9
0.4
0
0.35
0.4
WL
- 0.25
0.6
250
375
2
1.1
0.6
0.6
WL +
0.25
0.9
0.4
0
0.35
0.4
WL
- 0.25
0.6
350
475
2
+500
350
ps
1.1
0.6
tCK
tCK
ps
tCK
tCK
0.6
WL +
0.25
tCK
tCK
ps
ps
tCK
Note:
AC specification is based on ELPIDA components. Other DRAM manufactures specification may be different.
Continued on next page
June 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
AC TIMING PARAMETERS (cont'd)
Power-Down
ODT
Self Refresh
Command and Address
AC CHARACTERISTICS
665
PARAMETER
SYMBOL
MIN
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
tDAL
tWTR
tRP
tRPA
tMRD
55
10
15
50
45
7.5
15
tWR + tRP
7.5
15
tRP+tCK
2
tIS + tCK
+ tIH
tDELAY
REFRESH to Active of Refresh to Refresh command
interfal
tRFC
Average periodic refresh interval
tREFI
105
534
MAX
70,000
70,000
MIN
55
10
15
50
45
7.5
15
tWR + tRP
7.5
15
tRP+tCK
2
tIS + tCK
+ tIH
105
7.8
403
MAX
70,000
70,000
MIN
55
10
15
50
40
7.5
15
tWR + tRP
10
15
tRP+tCK
2
tIS + tCK
+ tIH
105
7.8
tIS
tIS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
70,000
ns
7.8
µs
Exit self refresh to READ command
tXSRD
Exit self refresh timing reference
tISXR
tIS
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
ODT turn-on
tAON
tAC (MIN)
tAC (MAX)
+ 700
tAC (MIN)
tAC (MAX)
+ 1000
tAC (MIN)
tAC (MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC (MIN)
tAC (MIN)
tAC (MIN)
+ 2000
ODT turn-off (power-down mode)
tAOFPD
tAC (MIN)
+ 2000
tAC (MAX)
+ 600
2 x tCK +
tAC (MAX)
+ 1000
2.5 x
tCK + tAC
(MAX) +
1000
ps
tAONPD
tAC (MAX)
+ 600
2 x tCK +
tAC (MAX)
+ 1000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
ODT turn-on (power-down mode)
tAC (MAX)
+ 600
2 x tCK +
tAC (MAX)
+ 1000
2.5 x
tCK + tAC
(MAX) +
1000
tXSNR
tRFC (MIN)
+ 10
200
70,000
UNIT
tRFC (MIN)
+ 10
200
Exit self refresh to non-READ command
tRFC (MIN)
+ 10
200
MAX
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
ns
tCK
ps
ps
ps
ODT to power-down entry latency
tANPD
3
3
3
tCK
ODT power-down exit latency
tAXPD
8
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
A Exit precharge power-down to any non-READ
command.
CKE minimum high/low time
tXARD
2
2
2
tCK
tXARDS
7 - AL
6 - AL
6 - AL
tCK
tXP
2
2
2
tCK
tCKE
3
3
3
tCK
Note:
AC specification is based on ELPIDA components. Other DRAM manufactures specification may be different.
June 2006
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
ORDERING INFORMATION FOR PD4
Part Number
Clock/Data Rate
Frequency
CAS Latency
tRCD
tRP
Height**
WV3HG32M40SEU665PD4xxG*
333MHz/667Mb/s
5
5
5
30.00mm (1.181") TYP
WV3HG32M40SEU534PD4xxG
266MHz/533Mb/s
4
4
4
30.00mm (1.181") TYP
WV3HG32M40SEU403PD4xxG
200MHz/400Mb/s
3
3
3
30.00mm (1.181") TYP
* Consult Factory for availability
NOTES:
• RoHS product. ("G" = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung, Elpida & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR PD4
FRONT VIEW
3.302 (0.130)
MAX
67.75 (2.667)
67.45 (2.656)
4.10(0.161) (2X)
3.90(0.154)
30.15 (1.187)
29.85 (1.175)
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
1.10 (0.043)
0.90 (0.035)
PIN 199
63.60 (2.504)
TYP
BACK VIEW
PIN 200
4.2 (0.165)
TYP
47.40 (1.866)
TYP
PIN 2
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
June 2006
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 32M 40 S E U xxx PD4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x16
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 200 PIN
(P = JEDEC proposed pin-out)
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(E = Elpida)
G = RoHS COMPLIANT
June 2006
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG32M40SEU-PD4
ADVANCED
Document Title
128MB – 32Mx40 DDR2 SDRAM UNBUFFERED
DRAM DIE OPTIONS:
• ELPIDA: F-Die
Rev #
History
Release Date
Status
Rev 0
Created
6-06
Concept
Rev 1
1.0 Update to x40 depth
6-8-06
Concept
6-9-06
Advanced
1.1 Added CB4, CB5, CB6, and CB7
1.2 Indicated SPD supply voltage
1.3 Change part number to indicated x40 (8 ECC bits)
Rev 2
June 2006
Rev. 2
2.0 Moved from concept to advanced
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com