Obsolete - Not Recommended for New Designs U635H64 PowerStore 8K x 8 nvSRAM Features • • • • • • • • • • • • • • • • High-performance CMOS nonvolatile static RAM 8192 x 8 bits 25, 35 and 45 ns Access Times 12, 20 and 25 ns Output Enable Access Times ICC = 15 mA at 200 ns Cycle Time Automatic STORE to EEPROM on Power Down using system capacitance Software initiated STORE (STORE Cycle Time < 10 ms) Automatic STORE Timing 105 STORE cycles to EEPROM 10 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation (RECALL Cycle Time < 20 μs) Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature ranges: 0 to 70 °C -40 to 85 °C QS 9000 Quality Standard ESD characterization accordingMIL STD 883C M3015.7-HBM (classification see IC Code Numbers) • • RoHS compliance and Pb- free Packages: PDIP28 (600 mil) SOP28 (330 mil) Description The U635H64 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U635H64 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in system capacitance. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U635H64 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. STORE cycles also may be initiated under user control via a software sequence. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Pin Description Pin Configuration n.c. 1 28 VCC A12 2 27 W A7 3 26 n.c. Signal Name Signal Description A6 4 25 A8 A0 - A12 Address Inputs A5 5 24 A9 DQ0 - DQ7 Data In/Out A4 6 23 A11 A3 7 G E Chip Enable A2 8 PDIP 22 SOP 21 G Output Enable A1 9 20 E Write Enable A0 10 19 DQ7 W VCC Power Supply Voltage DQ0 11 18 DQ6 VSS Ground DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 A10 Top View March 31, 2006 STK Control #ML0052 1 Rev 1.0 U635H64 Block Diagram EEPROM Array 128 x (64 x 8) VCC VSS STORE A5 Row Decoder A6 A7 A8 A9 A11 SRAM Array RECALL Power Control VCC 128 Rows x 64 x 8 Columns Store/ Recall Control A12 DQ0 DQ1 Input Buffers Column I/O DQ2 DQ3 DQ4 DQ5 DQ6 Software Detect Column Decoder A0 - A12 G A0 A1 A2 A3 A4 A10 DQ7 E W Truth Table for SRAM Operations Operating Mode E W G DQ0 - DQ7 Standby/not selected H * * High-Z Internal Read L H H High-Z Read L H L Data Outputs Low-Z Write L L * Data Inputs High-Z * H or L Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. Absolute Maximum Ratingsa Symbol Min. Max. Unit VCC -0.5 7 V Input Voltage VI -0.3 VCC+0.5 V Output Voltage VO -0.3 VCC+0.5 V Power Dissipation PD 1 W Power Supply Voltage Operating Temperature Storage Temperature a: C-Type K-Type Ta 0 -40 70 85 °C °C Tstg -65 150 °C Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. STK Control #ML0052 2 Rev 1.0 March 31, 2006 U635H64 Recommended Operating Conditions Symbol Power Supply Voltage VCC Input Low Voltage VIL Input High Voltage VIH DC Characteristics Symbol Conditions -2 V at Pulse Width 10 ns permitted Min. Max. Unit 4.5 5.5 V -0.3 0.8 V 2.2 VCC+0.3 V C-Type K-Type Conditions Unit Min. Operating Supply Currentb ICC1 Max. Min. Max. VCC VIL VIH = 5.5 V = 0.8 V = 2.2 V tc tc tc = 25 ns = 35 ns = 45 ns 90 80 75 95 85 80 mA mA mA Average Supply Current during STOREc ICC2 VCC E W VIL VIH = 5.5 V ≤ 0.2 V ≥ VCC-0.2 V ≤ 0.2 V ≥VCC-0.2 V 6 7 mA Average Supply Current during PowerStore Cyclec ICC4 VCC VIL VIH = 4.5 V = 0.2 V ≥ VCC-0.2 V 4 4 mA ICC(SB)1 VCC E tc tc tc = 5.5 V = VIH = 25 ns = 35 ns = 45 ns 30 23 20 34 27 23 mA mA mA Standby Supply Currentd (Cycling TTL Input Levels) Operating Supply Current at tcR = 200 nsb (Cycling CMOS Input Levels) ICC3 VCC W VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 15 15 mA Standby Supply Curentd (Stable CMOS Input Levels) ICC(SB) VCC E VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 3 3 mA b: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (STORE Cycle Time). d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2. March 31, 2006 STK Control #ML0052 3 Rev 1.0 U635H64 C-Type DC Characteristics Symbol Unit Min. Output High Voltage Output Low Voltage VOH VOL VCC IOH IOL = 4.5 V =-4 mA = 8 mA Output High Current Output Low Current IOH IOL VCC VOH VOL = 4.5 V = 2.4 V = 0.4 V VCC = 5.5 V VIH VIL = 5.5 V = 0V VCC = 5.5 V VOH VOL = 5.5 V = 0V Input Leakage Current High Low IIH IIL Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ K-Type Conditions Max. 2.4 Min. Max. 2.4 0.4 0.4 -4 8 -4 mA mA 1 μA μA 8 1 -1 -1 1 1 -1 V V -1 μA μA SRAM Memory Operations No. e: f: g: h: Switching Characteristics Read Cycle Symbol 25 35 45 Unit Alt. IEC Min. Max. Min. Max. Min. Max. 1 Read Cycle Timef tAVAV tcR 2 Address Access Time to Data Validg tAVQV ta(A) 25 35 45 ns 3 Chip Enable Access Time to Data Valid tELQV ta(E) 25 35 45 ns 4 Output Enable Access Time to Data Valid tGLQV ta(G) 12 20 25 ns 5 E HIGH to Output in High-Zh tEHQZ tdis(E) 13 17 20 ns 6 G HIGH to Output in High-Zh tGHQZ tdis(G) 13 17 20 ns 7 E LOW to Output in Low-Z tELQX ten(E) 5 5 5 ns 8 G LOW to Output in Low-Z tGLQX ten(G) 0 0 0 ns 9 Output Hold Time after Address Change tAXQX tv(A) 3 3 3 ns 10 Chip Enable to Power Activee tELICCH tPU 0 0 0 ns 11 Chip Disable to Power Standbyd, e tEHICCL tPD 25 35 25 45 35 ns 45 ns Parameter guaranteed but not tested. Device is continuously selected with E and G both LOW. Address valid prior to or coincident with E transition LOW. Measured ± 200 mV from steady state output voltage. STK Control #ML0052 4 Rev 1.0 March 31, 2006 U635H64 Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f tcR (1) Ai Address Valid ta(A) (2) DQi Previous Data Valid Output Output Data Valid tv(A) (9) Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g tcR (1) Ai Address Valid ta(A) (2) ta(E) (3) E tdis(E) (5) ten(E) (7) G ta(G) (4) tdis(G) (6) ten(G) (8) DQi High Impedance Output Output Data Valid tPU (10) ACTIVE ICC No. tPD (11) STANDBY Switching Characteristics Write Cycle Symbol 25 35 45 Unit Alt. #1 Alt. #2 12 Write Cycle Time tAVAV 13 Write Pulse Width tWLWH 14 Write Pulse Width Setup Time tAVAV IEC Min. Max. Min. Max. Min. Max. tcW 25 35 45 ns tw(W) 20 30 35 ns tWLEH tsu(W) 20 30 35 ns 15 Address Setup Time tAVWL tAVEL tsu(A) 0 0 0 ns 16 Address Valid to End of Write tAVWH tAVEH tsu(A-WH) 20 30 35 ns 17 Chip Enable Setup Time tELWH tsu(E) 20 30 35 ns tELEH tw(E) 20 30 35 ns 18 Chip Enable to End of Write 19 Data Setup Time to End of Write tDVWH tDVEH tsu(D) 12 18 20 ns 20 Data Hold Time after End of Write tWHDX tEHDX th(D) 0 0 0 ns 21 Address Hold after End of Write tWHAX tEHAX th(A) 0 0 0 ns 22 W LOW to Output in High-Zh, i tWLQZ tdis(W) 23 W HIGH to Output in Low-Z tWHQX ten(W) March 31, 2006 STK Control #ML0052 5 10 5 13 5 Rev 1.0 15 5 ns ns U635H64 Write Cycle #1: W-controlledj tcW (12) Ai Address Valid tsu(E) (17) th(A) (21) E tsu(A-WH) W DQi (16) tw(W) tsu(A) (15) (13) tsu(D) (19) th(D) (20) Input Input Data Valid DQi tdis(W) (22) ten(W) (23) High Impedance Output Previous Data Write Cycle #2: E-controlledj tcW (12) Ai tsu(A) (15) E Address Valid tw(E) (18) th(A) (21) tsu(W) (14) W th(D) (20) tsu(D) (19) DQi Input Input Data Valid DQi High Impedance Output undefined i: j: L- to H-level H- to L-level If W is LOW and when E goes LOW, the outputs remain in the high impedance state. E or W must be VIH during address transition. STK Control #ML0052 6 Rev 1.0 March 31, 2006 U635H64 Nonvolatile Memory Operations Mode Selection E W A12 - A0 (hex) Mode I/O Power H X X Not Selected Output High Z Standby L H X Read SRAM Output Data Active L L X Write SRAM Input Data Active L H 0000 1555 0AAA 1FFF 10F0 0F0F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z Active k, l k, l k, l k, l k, l k L H 0000 1555 0AAA 1FFF 10F0 0F0E Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z Active k, l k, l k, l k, l k, l k Notes m k: The six consecutive addresses must be in order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a Store cycle or (0000, 1555, 0AAA, 1FFF,10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C. l: Activation of nonvolatile cycles does not depend on the state of G. m: I/O state assumes that G ≤ VIL. No. PowerStore Power Up RECALL 24 Power Up RECALL Durationn, e 25 STORE Cycle Durationf 26 Time allowed to Complete SRAM Cyclef, e Low Voltage Trigger Level n: Symbol Conditions Alt. tRESTORE tPDSTORE the power supply voltage must stay above 3.6 V for at least 10 ms after the start of the STORE operation tDELAY 4.0 VSWITCH tRESTORE starts from the time VCC rises above VSWITCH. March 31, 2006 STK Control #ML0052 Min. Max. Unit 650 μs 10 ms 1 μs 4.5 V IEC 7 Rev 1.0 U635H64 PowerStore and automatic Power Up RECALL VCC 5.0 V VSWITCH t PowerStore (25) tPDSTOREp Power Up RECALL (24) (24) tRESTORE tRESTORE W (26) tDELAY DQi POWER UP RECALL No. o: p: q: r: s: t: Software Controlled STORE/ RECALL Cyclek, o BROWN OUT NO STORE (NO SRAM WRITES) BROWN OUT PowerStore Symbol 25 35 45 Unit Alt. IEC Min. Max. Min. Max. Min. Max. 27 STORE/RECALL Initiation Time tAVAV tcR 28 Chip Enable to Output Inactivep tELQZ tdis(E)SR 600 600 600 ns 29 STORE Cycle Timeq tELQXS td(E)S 10 10 10 ms 30 RECALL Cycle Timer tELQXR td(E)R 20 20 20 μs 31 Address Setup to Chip Enables tAVELN tsu(A)SR 0 0 0 ns 32 Chip Enable Pulse Widths, t tELEHN tw(E)SR 20 25 35 ns 33 Chip Disable to Address Changes tEHAXN th(A)SR 0 0 0 ns 25 35 45 ns The software sequence is clocked with E controlled READs. Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit). An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly. Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. STK Control #ML0052 8 Rev 1.0 March 31, 2006 U635H64 Software Controlled STORE/RECALL Cycles, t, u, v (E = HIGH after STORE initiation) tcR (27) Ai tcR (27) ADDRESS 1 tw(E)SR E DQi (32) tsu(A)SR (31) (33) th(A)SR High Impedance ADDRESS 6 th(A)SR (33) tw(E)SR tdis(E)(5) (32) (31) tsu(A)SR VALID Output td(E)S (29) td(E)R (30) VALID tdis(E)SR (28) Software Controlled STORE/RECALL Cycles, t, u, v (E = LOW after STORE initiation) tcR (27) Ai E DQi Output ADDRESS 1 ADDRESS 6 th(A)SR (33) tw(E)SR tsu(A)SR (31) High Impedance (32) (31) (33) th(A)SR tsu(A)SR VALID td(E)S (29) td(E)R (30) VALID tdis(E)SR (28) u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U635H64 performs a STORE or RECALL. v: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles. March 31, 2006 STK Control #ML0052 9 Rev 1.0 U635H64 Test Configuration for Functional Check 5V DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 E W G ment of all 8 output pins VIL DQ0 Simultaneous measure- VIH A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 relevant test measurement Input level according to the VCCx 480 VO 30 pF w 255 VSS w: In measurement of tdis-times and ten-times the capacitance is 5 pF. x: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances. Capacitancee Conditions VCC VI f Ta Input Capacitance Output Capacitance Symbol = 5.0 V = VSS = 1 MHz = 25 °C Min. Max. Unit CI 8 pF CO 7 pF All pins not under test must be connected with ground by capacitors. Ordering Code Example U635H64 S C 25 G1 Type Leadfree Option blank = Standard Package G1 = Leadfree Green Package y ESD Class blank > 2000 V B > 1000 V Package D1 = PDIP28 (600 mil) S = SOP28 (330 mil) Type 1 S2 = SOP28 (330 mil) Type 2 Access Time 25 = 25 ns 35 = 35 ns y 45 = 45 ns y Operating Temperature Range C = 0 to 70 °C K = -40 to 85 °C y: on special request Device Marking (example) Product specification ZMD U635H64S2C 25 Z 0425 G1 Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package Internal Code STK Control #ML0052 10 Rev 1.0 March 31, 2006 U635H64 Device Operation The U635H64 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. STORE cycles may be initiated under user control via a software sequence and are also automatically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power up and may occur also when VCC rises above VSWITCH after a low power condition. RECALL cycles may also be initiated by a software sequence. matic STORE will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. Automatic RECALL During power up an automatic RECALL takes place. After any low power condition (VCC < VSWITCH) an internal RECALL request may be latched. When VCC once again exceeds the sense voltage of VSWITCH, a requested RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the U635H64 is in a WRITE state at the end of a power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 KΩ resistor should be connected between W and system VCC. SRAM READ Software Nonvolatile STORE The U635H64 performs a READ cycle whenever E and G are LOW and W are HIGH. The address specified on pins A0 - A12 determines which of the 8192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Automatic STORE The U635H64 uses the intrinsic system capacitance to perform an automatic STORE on power down. As long as the system power supply take at least tPDSTORE to decay from VSWITCH down to 3.6 V the U635H64 will safely and automatically STORE the SRAM data in EEPROM on power down. In order to prevent unneeded STORE operations, auto- March 31, 2006 STK Control #ML0052 11 The U635H64 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U635H64 implements nonvolatile operation while remaining compatible with standard 8K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is performed first, followed by a parallel programming of all nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 1555 0AAA 1FFF 10F0 0F0F (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles are used in the sequence, although it is not necessary that G is LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Rev 1.0 U635H64 Software Nonvolatile RECALL Hardware Protection A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: The U635H64 offers hardware protection against inadvertent STORE operation through VCC Sense. When VCC < VSWITCH all software controlled STORE operations will be inhibited. Low Average Active Power 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 1555 0AAA 1FFF 10F0 0F0E (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. The U635H64 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the VCC level The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. STK Control #ML0052 12 Rev 1.0 March 31, 2006 U635H64 LIFE SUPPORT POLICY Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Simtek product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However, Simtek makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms and conditions of sale. Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. March 31, 2006 Change record Date/Rev Name Change 01.11.2001 Ivonne Steffens format revision and release for „Memory CD 2002“ 25.09.2002 Matthias Schniebel Adding „Type 1“ to SOP28 (330mil) 20.04.2004 Matthias Schniebel adding „Leadfree Green Package“ to ordering information adding „Device Marking“ 7.4.2005 Stefan Günther adding RoHS compliance and Pb- free, S2 for chippack and delete PDIP28 (300mil) 31.3.2006 Troy Meester changed to obsolete status Simtek Assigned Simtek Document Control Number 1.0