STK16C88 32K x 8 AutoStorePlus™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM FEATURES DESCRIPTION • Transparent Data Save on Power Down • Internal Capacitor Guarantees AutoStore™ Regardless of Power-Down Slew Rate • Nonvolatile Storage without Battery Problems • Directly Replaces 32K x 8 Static RAM, BatteryBacked RAM or EEPROM • 25ns, 35ns and 45ns Access Times • STORE to EEPROM Initiated by Software or AutoStorePlus™ on Power Down • No Data Loss from Undershoot • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to EEPROM • 100-Year Data Retention over Full Industrial Temperature Range • Commercial and Industrial Temperatures • 28-Pin PDIP Package The STK16C88 is a fast SRAM with a nonvolatile EEPROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) can take place automatically on power down. An internal capacitor guarantees the STORE operation regardless of power-down slew rate. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. The STK16C88 is pin-compatible with 32k x 8 SRAMs and battery-backed SRAMs, allowing direct substitution while enhancing performance. The STK14C88, which uses an external capacitor, and the STK15C88, which uses charge stored in system capacitance, are alternatives for systems needing AutoStorePlus™ operation. BLOCK DIAGRAM PIN CONFIGURATIONS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 INPUT BUFFERS A5 A6 A7 A8 A9 A11 A12 A13 A14 ROW DECODER EEPROM ARRAY 512 x 512 STORE STATIC RAM ARRAY 512 x 512 RECALL VCC STORE/ RECALL CONTROL POWER CONTROL INTERNAL CAPACITOR SOFTWARE DETECT A0 A1 A2 A3 A4A10 G E W February 2002 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 - 600 PDIP PIN NAMES COLUMN I/O COLUMN DEC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 5-65 A0 - A13 A0 - A14 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCC Power (+ 5V) VSS Ground STK16C88 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (VCC = 5.0V ± 10%) DC CHARACTERISTICS COMMERCIAL SYMBOL INDUSTRIAL PARAMETER UNITS MIN MAX MIN NOTES MAX ICC b Average VCC Current 97 80 70 100 85 70 mA mA mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns 1 ICC c Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max ICC b Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical 10 10 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels ISB d 1 Average VCC Current (Standby, Cycling TTL Input Levels) 30 25 22 31 26 23 mA mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH ISB d 2 VCC Standby Current (Standby, Stable CMOS Input Levels) 1.5 1.5 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) 2 3 IILK Input Leakage Current ±1 ±1 µA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±5 ±5 µA VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage V IOUT = – 4mA VOL Output Logic “0” Voltage 0.4 V IOUT = 8mA TA Operating Temperature 85 °C 2.4 2.4 0.4 0 70 –40 Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 Note c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL 5.0V (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 5 pF ∆V = 0 to 3V COUT Output Capacitance 7 pF ∆V = 0 to 3V Note e: These parameters are guaranteed but not tested. 480 Ohms OUTPUT 255 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading February 2002 5-66 STK16C88 (VCC = 5.0V ± 10%) SRAM READ CYCLES #1 & #2 SYMBOLS NO. STK16C88-25 STK16C88-35 STK16C88-45 PARAMETER #1, #2 Alt. UNITS MIN MAX MIN MAX 25 MIN 1 tELQV tACS Chip Enable Access Time 2 tAVAVf tRC Read Cycle Time 3 tAVQVg tAA Address Access Time 25 35 45 ns 4 tGLQV tOE Output Enable to Data Valid 10 15 20 ns 5 tAXQXg tOH Output Hold after Address Change 5 5 5 ns 6 tELQX tLZ Chip Enable to Output Active 5 5 5 ns 7 tEHQZh tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 25 35 MAX 45 10 0 9 tGHQZh tOHZ Output Disable to Output Inactive 10 tELICCHe tPA Chip Enable to Power Active 11 tEHICCLd, e tPS Chip Disable to Power Standby 45 35 13 0 10 0 13 0 25 35 SRAM READ CYCLE #1: Address Controlledf, g 2 tAVAV ADDRESS 3 tAVQV tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledf 2 tAVAV ADDRESS 1 tELQV 6 11 tEHICCL tELQX E 7 tEHQZ G 8 tGLQX 9 tGHQZ 4 tGLQV DQ (DATA OUT) DATA VALID 10 tELICCH ACTIVE ICC February 2002 STANDBY 5-67 ns ns 15 ns 45 ns 0 Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. 5 ns 15 0 ns ns STK16C88 (VCC = 5.0V ± 10%) SRAM WRITE CYCLES #1 & #2 SYMBOLS STK16C88-25 NO. STK16C88-35 STK16C88-45 PARAMETER #1 #2 Alt. UNITS MIN MAX MIN MAX MIN MAX 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 20 tWLQZh, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write Note i: Note j: 10 5 13 5 5 If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT February 2002 16 tEHDX DATA VALID HIGH IMPEDANCE 5-68 ns 15 ns ns STK16C88 (VCC = 5.0V ± 10%) AutoStorePlus™/POWER-UP RECALL SYMBOLS STK16C88 NO. PARAMETER UNITS NOTES Standard MIN 22 tRESTORE Power-up RECALL Duration 23 tstg Power-down AutoStore™ Slew Time to Ground 500 24 VSWITCH Low Voltage Trigger Level 4.0 25 VRESET Low Voltage Reset Level MAX 550 V 3.9 V AutoStorePlus™/POWER-UP RECALL VCC 5V 24 VSWITCH 25 VRESET 23 tstg AutoStore™ POWER-UP RECALL 22 tRESTORE W DQ (DATA OUT) February 2002 BROWN OUT NO STORE DUE TO NO SRAM WRITES BROWN OUT AutoStorePlus™ BROWN OUT AutoStorePlus™ NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH 5-69 l f, h 4.5 Note k: tRESTORE starts from the time VCC rises above VSWITCH. POWER-UP RECALL µs ns STK16C88 SOFTWARE STORE/RECALL MODE SELECTION E W A13 - A0 (hex) MODE I/O NOTES H 0E38 31C7 03E0 3C1F 303F 0FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z l, m H 0E38 31C7 03E0 3C1F 303F 0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z l, m L L Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note m: While there are 15 addresses on the STK16C88, only the lower 14 are used to control software modes. (VCC = 5.0V ± 10%) SOFTWARE STORE/RECALL CYCLEn, o NO. SYMBOLS STK16C88-25 STK16C88-35 STK16C88-45 MIN MIN MIN PARAMETER UNITS MAX MAX MAX 26 tAVAV STORE/RECALL Initiation Cycle Time 25 35 45 ns 27 tAVELn Address Set-up Time 0 0 0 ns 28 tELEHn Clock Pulse Width 20 25 30 ns 29 tELAXg, n Address Hold Time 20 20 20 30 tRECALL RECALL Cycle Duration 20 20 20 µs 31 tSTORE STORE Cycle Duration 10 10 10 ms ns Note n: The software sequence is clocked with E controlled reads. Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledo 26 26 tAVAV ADDRESS tAVAV ADDRESS #1 27 tAVEL ADDRESS #6 28 tELEH E 29 tELAX 31 tSTORE DQ (DATA February 2002 DATA VALID DATA VALID 5-70 30 / tRECALL HIGH IMPEDANCE STK16C88 DEVICE OPERATION The AutoStorePlus™ STK16C88 is a fast 32K x 8 SRAM that does not lose its data on power-down. The data is preserved in integral QuantumTrap™ EEPROM while power is unavailable. The nonvolatility of the STK16C88 does not require any system intervention or support: AutoStorePlus™ on powerdown and automatic RECALL on power-up guarantee data integrity without the use of batteries NOISE CONSIDERATIONS AutoStorePlus™ OPERATION The STK16C88’s automatic STORE on power-down is completely transparent to the system. The AutoStore™ initiation takes less than 500ns when power is lost (VCC < VSWITCH) at which point the part depends only on its internal capacitor for STORE completion. This safe transfer of data from SRAM to EEPROM takes place regardless of power supply slew rate. Note that the STK16C88 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. SRAM READ During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. The STK16C88 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. February 2002 POWER-UP RECALL If the STK16C88 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10kΩ resistor should be connected either between W and system VCC or between E and system VCC. SOFTWARE NONVOLATILE STORE The STK16C88 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 5-71 STK16C88 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvola- tile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. HARDWARE PROTECT The STK16C88 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCC < VSWITCH, all software STORE operations and SRAM WRITEs are inhibited. LOW AVERAGE ACTIVE POWER The STK16C88 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK16C88 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/ O loading. 100 Average Active Current (mA) Average Active Current (mA) 100 80 60 40 TTL 20 80 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 Cycle Time (ns) 50 200 Figure 3: ICC (max) Writes Figure 2: ICC (max) Reads February 2002 100 150 Cycle Time (ns) 5-72 200 STK16C88 ORDERING INFORMATION STK16C88 - W 25 I Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (–40 to 85°C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Package W = Plastic 28-pin 600 mil DIP February 2002 5-73 STK16C88 February 2002 5-74