STK16C88-3 32K x 8 AutoStorePlus™ nvSRAM 3.3V QuantumTrap™ CMOS Nonvolatile Static RAM FEATURES DESCRIPTION • Transparent Data Save on Power Down • Internal Capacitor Guarantees AutoStore™ Regardless of Power-Down Slew Rate • Directly Replaces 32K x 8 Static RAM, BatteryBacked RAM or EEPROM • 35 Access Time • STORE to Nonvolatile Elements Initiated by Software or AutoStorePlus™ • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to Nonvolatile Elements (Commercial/Industrial) • 100-Year Data Retention in nonvolatile elements (Commercial/Industrial) • Single 3.3V + 0.3V Operation • Commercial and Industrial Temperatures • 28-Pin PDIP Package The STK16C88-3 is a fast SRAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down. An internal capacitor guarantees the STORE operation regardless of power-down slew rate. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. The STK16C88-3 is pin-compatible with 32k x 8 SRAMs and battery-backed SRAMs, allowing direct substitution while providing superior performance. The STK14C88-3, which uses an external capacitor, is also available. PIN CONFIGURATIONS BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 INPUT BUFFERS A5 A6 A7 A8 A9 A11 A12 A13 A14 ROW DECODER QUANTUM TRAP 512 x 512 STORE STATIC RAM ARRAY 512 x 512 RECALL VCC STORE/ RECALL CONTROL POWER CONTROL INTERNAL CAPACITOR 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 - 600 PDIP PIN NAMES COLUMN I/O SOFTWARE DETECT COLUMN DEC A0 A1 A2 A3 A4A10 G E W March 2006 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 A0 - A13 A0 - A14 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCC Power (+ 3.3V) VSS Ground Document Control # ML0019 rev 0.2 STK16C88-3 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 4.5V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS (VCC = 3.0V-3.6V) COMMERCIAL SYMBOL UNITS MIN ICC1b INDUSTRIAL PARAMETER MAX MIN NOTES MAX Average VCC Current 50 52 mA tAVAV = 35ns ICC2 c Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max ICC3 b Average VCC Current at tAVAV = 200ns 3.3V, 25°C, Typical 8 8 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels 19 mA 1 1 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) ISB1d Average VCC Current (Standby, Cycling TTL Input Levels) ISB2d VCC Standby Current (Standby, Stable CMOS Input Levels) IILK Input Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage VOL Output Logic “0” Voltage TA Operating Temperature 18 2.4 2.4 0.4 0 70 –40 tAVAV = 35ns, E ≥ VIH V IOUT = – 4mA 0.4 V IOUT = 8mA 85 °C Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS 3.3V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe 317 Ohms (TA = 25°C, f = 1.0MHz) OUTPUT 351 Ohms SYMBOL PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 5 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V 30 pF INCLUDING SCOPE AND FIXTURE Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading March 2006 2 Document Control # ML0019 rev 0.2 STK16C88-3 SRAM READ CYCLES #1 & #2 (VCC = 3.0V-3.6V) SYMBOLS NO. STK16C88-3-35 PARAMETER #1, #2 1 tELQV 2 f tAVAV g 3 tAVQV 4 tGLQV 5 tAXQX 6 tELQX g h MIN Chip Enable Access Time 35 tRC Read Cycle Time tAA Address Access Time 35 ns tOE Output Enable to Data Valid 15 ns tOH Output Hold after Address Change 5 ns tLZ Chip Enable to Output Active 5 ns tHZ Chip Disable to Output Inactive 35 tEHQZ 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZh tOHZ Output Disable to Output Inactive tPA Chip Enable to Power Active tPS Chip Disable to Power Standby 10 tELICCH 11 tEHICCLd, e MAX tACS 7 e UNITS Alt. ns ns 13 0 ns ns 13 0 ns ns 35 ns Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledf 2 tAVAV ADDRESS 1 tELQV 6 11 tEHICCL tELQX E 7 tEHQZ G 8 tGLQX 9 tGHQZ 4 tGLQV DQ (DATA OUT) DATA VALID 10 tELICCH ACTIVE ICC March 2006 STANDBY 3 Document Control # ML0019 rev 0.2 STK16C88-3 SRAM WRITE CYCLES #1 & #2 (VCC = 3.0V-3.6V) SYMBOLS STK16C88-3-35 NO. PARAMETER #1 #2 Alt. UNITS MIN MAX 12 tAVAV tAVAV tWC Write Cycle Time 35 ns 13 tWLWH tWLEH tWP Write Pulse Width 25 ns 14 tELWH tELEH tCW Chip Enable to End of Write 25 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 12 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 25 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 ns 20 tWLQZ h, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write Note i: Note j: 13 5 ns ns If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT March 2006 16 tEHDX DATA VALID HIGH IMPEDANCE 4 Document Control # ML0019 rev 0.2 STK16C88-3 AutoStorePlus™/POWER-UP RECALL (VCC = 3.0V-3.6V) SYMBOLS STK16C88-3 NO. PARAMETER UNITS NOTES Standard MIN 22 tRESTORE Power-up RECALL Duration 23 tstg Minimum VCC Slew Time to Ground 500 24 VSWITCH Low Voltage Trigger Level 2.7 25 VRESET Low Voltage Reset Level MAX 550 μs k ns e, g 2.95 V 2.4 V e Note k: tRESTORE starts from the time VCC rises above VSWITCH. AutoStorePlus™/POWER-UP RECALL VCC 3.3V 24 VSWITCH 25 VRESET 23 tstg AutoStore™ 31 tSTORE POWER-UP RECALL 22 tRESTORE W DQ (DATA OUT) POWER-UP RECALL March 2006 BROWN OUT NO STORE DUE TO NO SRAM WRITES BROWN OUT AutoStorePlus™ BROWN OUT AutoStorePlus™ NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH 5 Document Control # ML0019 rev 0.2 STK16C88-3 SOFTWARE STORE/RECALL MODE SELECTION E L L W A13 - A0 (hex) MODE I/O NOTES H 0E38 31C7 03E0 3C1F 303F 0FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z l, m H 0E38 31C7 03E0 3C1F 303F 0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z l, m Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note m: While there are 15 addresses on the STK16C88-3, only the lower 14 are used to control software modes. SOFTWARE STORE/RECALL CYCLEn, o (VCC = 3.0V-3.6V) STK16C88-3-35 NO. SYMBOLS PARAMETER UNITS MIN MAX 26 tAVAV STORE/RECALL Initiation Cycle Time 35 ns 27 tAVELn Address Set-up Time 0 ns 28 tELEHn Clock Pulse Width 25 ns 29 tELAXg, n Address Hold Time 20 ns 30 tRECALL RECALL Cycle Duration 20 μs 31 tSTORE STORE Cycle Duration 10 ms Note n: The software sequence is clocked with E controlled reads. Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledo 26 26 tAVAV ADDRESS tAVAV ADDRESS #1 27 tAVEL ADDRESS #6 28 tELEH E 29 tELAX 31 tSTORE DQ (DATA March 2006 DATA VALID DATA VALID 6 30 / tRECALL HIGH IMPEDANCE Document Control # ML0019 rev 0.2 STK16C88-3 DEVICE OPERATION AutoStorePlus™ OPERATION The AutoStorePlus™ STK16C88-3 is a fast 32K x 8 SRAM that does not lose its data on power-down. The data is preserved in integral QuantumTrap™ Nonvolatile Elements while power is unavailable. The nonvolatility of the STK16C88-3 does not require any system intervention or support: AutoStorePlus™ on power-down and automatic RECALL on power-up guarantee data integrity without the use of batteries. The STK16C88-3’s automatic STORE on powerdown is completely transparent to the system. The AutoStore™ initiation takes less than 500ns when power is lost (VCC < VSWITCH) at which point the part depends only on its internal capacitor for STORE completion. If the power supply drops faster than 20μs/volt before Vccx reaches Vswitch, then a 2.2 ohm resistor should be inserted between Vccx and the system supply to avoid a momentary excess of current between Vccx and Vcap. NOISE CONSIDERATIONS Note that the STK16C88-3 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. SRAM READ POWER-UP RECALL The STK16C88-3 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK16C88-3 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10kΩ resistor should be connected either between W and system VCC or between E and system VCC. SOFTWARE NONVOLATILE STORE The STK16C88-3 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. March 2006 7 Document Control # ML0019 rev 0.2 STK16C88-3 To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) tile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times. Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle HARDWARE PROTECT The software sequence must be clocked with E controlled READs. The STK16C88-3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCC < VSWITCH, all software STORE operations and SRAM WRITEs are inhibited. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. LOW AVERAGE ACTIVE POWER The STK16C88-3 draws significantly less current when it is cycled at times longer than 55ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK16C88-3 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/ O loading. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvola- 50 Average Active Current (mA) Average Active Current (mA) 50 40 30 20 TTL 10 40 30 TTL 20 CMOS 10 CMOS 0 0 50 100 150 Cycle Time (ns) 50 200 200 Figure 3: ICC (max) Writes Figure 2: ICC (max) Reads March 2006 100 150 Cycle Time (ns) 8 Document Control # ML0019 rev 0.2 STK16C88-3 ORDERING INFORMATION STK16C88-3 W F 35 I Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (–40 to 85°C) Access Time 35 = 35ns Lead Finish F = 100% Sn (Matte Tin) Package W = Plastic 28-pin 600 mil DIP March 2006 9 Document Control # ML0019 rev 0.2 STK16C88-3 Document Revision History Revision Date Summary 0.0 December 2002 0.1 September 2003 Added lead-free lead finish 0.2 March 2006 Removed 45ns and 55ns speed grades, Removed Leaded lead finish. March 2006 10 Document Control # ML0019 rev 0.2 STK16C88-3 March 2006 11 Document Control # ML0019 rev 0.2