19-2093; Rev 1; 2/07 KIT ATION EVALU E L B AVAILA Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Video Application 48 TQFP-EP* MAX1181ECM+ -40°C to +85°C 48 TQFP-EP* *EP = Exposed paddle. +Denotes a lead-free package. 37 38 39 40 41 42 43 44 45 46 47 48 REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A Pin Configuration COM 1 36 D1A VDD GND INA+ 2 35 D0A 3 34 4 33 INAVDD GND 5 32 OGND OVDD OVDD OGND INB- 8 29 INB+ GND VDD 9 28 10 27 CLK 12 6 31 MAX1181 7 30 D0B D1B 26 D2B D3B D4B 25 D5B 24 23 22 21 20 19 18 17 EP* 11 16 Instrumentation PIN-PACKAGE -40°C to +85°C 15 Multichannel IF Undersampling PART VDD GND T/B SLEEP PD OE D9B D8B D7B D6B I/Q Channel Digitization TEMP RANGE MAX1181ECM 14 High-Resolution Imaging Ordering Information 13 Applications ♦ Single 3V Operation ♦ Excellent Dynamic Performance 59dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz ♦ Low Power 82mA (Normal Operation) 2.8mA (Sleep Mode) 1µA (Shutdown Mode) ♦ 0.02dB Gain and 0.25° Phase Matching (typ) ♦ Wide ±1VP-P Differential Analog Input Voltage Range ♦ 400MHz, -3dB Input Bandwidth ♦ On-Chip 2.048V Precision Bandgap Reference ♦ User-Selectable Output Format—Two’s Complement or Offset Binary ♦ 48-Pin TQFP Package with Exposed Pad for Improved Thermal Dissipation ♦ Evaluation Kit Available GND VDD The MAX1181 is a 3V, dual 10-bit, analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, ninestage ADCs. The MAX1181 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation, and digital communication applications. The MAX1181 operates from a single 2.7V to 3.6V supply, consuming only 246mW, while delivering a typical signal-to-noise ratio (SNR) of 59dB at an input frequency of 20MHz and a sampling rate of 80Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1181 features a 2.8mA sleep mode, as well as a 1µA power-down mode to conserve power during idle periods. An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or external reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1181 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1181 is available in a 7mm ✕ 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. Pin-compatible higher and lower speed versions of the MAX1181 are also available. Please refer to the MAX1180 datasheet for 105Msps, the MAX1182 datasheet for 65Msps, the MAX1183 datasheet for 40Msps, and the MAX1184 datasheet for 20Msps. In addition to these speed grades, this family includes a 20Msps multiplexed output version (MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port. Features 48 TQFP-EP Functional Diagram appears at end of data sheet. NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED BY A "+" SIGN. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX1181 General Description MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, CLK, COM to GND ...........................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A–D0A, D9B–D0B to OGND ..............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP-EP (derate 30.4mW/°C above +70°C) ...2430mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL fIN = 7.47MHz ±0.6 ±2.2 Differential Nonlinearity DNL fIN = 7.47MHz, no missing codes guaranteed ±0.4 ±1.0 LSB +2 % FS ±2 % FS Offset Error -2 Gain Error 0 LSB ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range VCM Input Resistance RIN Input Capacitance CIN Differential or single-ended inputs Switched capacitor load ±1.0 V VDD/2 ± 0.5 V 25 kΩ 5 pF CONVERSION RATE Maximum Clock Frequency fCLK 80 Data Latency MHz 5 Clock Cycles DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio (Note 3) SNR Signal-to-Noise And Distortion (Note 3) SINAD Spurious-Free Dynamic Range (Note 3) SFDR Third-Harmonic Distortion (Note 3) HD3 2 fINA or B = 7.47MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 39.9MHz fINA or B = 7.47MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 39.9MHz fINA or B = 7.47MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 39.9MHz fINA or B = 7.47MHz 56.5 56 56 55.3 65 64 59.5 59 59 59 58.5 58.5 75 73 71 -76 fINA or B = 20MHz -76 fINA or B = 39.9MHz -75 _______________________________________________________________________________________ dB dB dBc dBc Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Total Harmonic Distortion (First Four Harmonics) (Note 3) Intermodulation Distortion (First Five Odd-Order IMDs) SYMBOL THD IMD Small-Signal Bandwidth Full-Power Bandwidth FPBW TYP MAX fINA or B = 7.47MHz, TA = +25°C CONDITIONS MIN -73 -64 fINA or B = 20MHz, TA = +25°C -70 -63 fINA or B = 39.9MHz -70 UNITS dBc fINA or B = 38.1546MHz at -6.5dBFS fINA or B = 41.9532MHz at -6.5dBFS (Note 4) -73.5 dBc Input at -20dBFS, differential inputs 500 MHz Input at -0.5dBFS, differential inputs 400 MHz Aperture Delay tAD 1 ns Aperture Jitter tAJ 2 psRMS 2 ns Overdrive Recovery Time For 1.5 x full-scale input ±1 % ±0.25 degrees 0.2 LSBRMS REFOUT 2.048 ±3% V TCREF 60 ppm/°C 1.25 mV/mA Differential Gain Differential Phase Output Noise INA+ = INA- = INB+ = INB- = COM INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) REFIN Input Voltage VREFIN 2.048 V Positive Reference Output Voltage VREFP 2.012 V Negative Reference Output Voltage VREFN 0.988 V Differential Reference Output Voltage Range ΔVREF REFIN Resistance RREFIN > 50 MΩ ISOURCE >5 mA ISINK 250 µA ISOURCE 250 µA ISINK >5 mA Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current ΔVREF = VREFP - VREFN 0.95 1.024 1.10 V UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN and COM ) REFP, REFN Input Resistance RREFP, RREFN Measured between REFP and COM and REFN and COM 4 kΩ _______________________________________________________________________________________ 3 MAX1181 ELECTRICAL CHARACTERISTICS (continued) MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL Differential Reference Input Voltage ΔVREF COM Input Voltage CONDITIONS MIN TYP MAX UNITS 1.024 ± 10% V VCOM VDD / 2 ± 10% V REFP Input Voltage VREFP VCOM + ΔVREF / 2 V REFN Input Voltage VREFN VCOM - ΔVREF / 2 V ΔVREF = VREFP - VREFN DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) Input High Threshold Input Low Threshold Input Hysteresis Input Leakage Input Capacitance CLK 0.8 x VDD PD, OE, SLEEP, T/B 0.8 x OVDD VIH V CLK 0.2 x VDD PD, OE, SLEEP, T/B 0.2 x OVDD VIL VHYST 0.1 V IIH VIH = OVDD or VDD (CLK) ±5 IIL VIL = 0 ±5 CIN V 5 µA pF DIGITAL OUTPUTS (D9A–D0A, D9B–D0B) Output-Voltage Low VOL ISINK = 200µA Output-Voltage High VOH ISOURCE = 200µA Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT OE = OVDD 0.2 OVDD - 0.2 V V ±10 5 µA pF POWER REQUIREMENTS Analog Supply Voltage Range VDD 2.7 3.0 3.6 V Output Supply Voltage Range OVDD 1.7 2.5 3.6 V Operating, fINA or B = 20MHz at -0.5dBFS 82 97 Sleep mode 2.8 Analog Supply Current Output Supply Current IVDD IOVDD Shutdown, clock idle, PD = OE = OVDD 1 Operating, CL = 15pF , fINA or B = 20MHz at -0.5dBFS 13 Sleep mode 100 Shutdown, clock idle, PD = OE = OVDD Power Dissipation PDISS 10 Operating, fINA or B = 20MHz at -0.5dBFS 246 291 Sleep mode 8.4 3 _______________________________________________________________________________________ µA mA 2 Shutdown, clock idle, PD = OE = OVDD 4 15 mA 45 µA mW µW Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL Power Supply Rejection PSRR CONDITIONS MIN TYP MAX UNITS Offset ±0.2 mV/V Gain ±0.1 %/V TIMING CHARACTERISTICS CLK Rise to Output Data Valid Figure 3 (Note 5) 5 Output Enable Time tENABLE tDO Figure 4 10 8 ns ns Output Disable Time tDISABLE Figure 4 1.5 ns CLK Pulse-Width High tCH Figure 3 clock period: 12ns 6 ±1 ns CLK Pulse-Width Low tCL Figure 3 clock period: 12ns 6 ±1 ns Wakeup from sleep mode 0.28 Wakeup from shutdown 1.5 fINA or B = 20MHz at -0.5dBFS -70 Gain Matching fINA or B = 20MHz at -0.5dBFS 0.02 Phase Matching fINA or B = 20MHz at -0.5dBFS 0.25 Wake-Up Time (Note 6) tWAKE µs CHANNEL-TO-CHANNEL MATCHING Crosstalk dB ±0.2 dB degrees Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization. Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS, referenced to a +1.024V full-scale input voltage range. Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Typical Operating Characteristics (VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) -30 -40 -50 -60 fINA = 6.0449MHz fINB = 7.5099MHz fCLK = 80.0006MHz AINB = -0.52dBFS CHB -20 AMPLITUDE (dB) AMPLITUDE (dB) -20 0 -10 -30 0 -40 -50 -60 -20 -30 -40 -50 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90 -100 -100 -100 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) 40 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) 40 fINA = 19.9123MHz fINB = 24.9123MHz fCLK = 80.0006MHz AINA = -0.52dBFS CHA -10 MAX1181 toc03 fINA = 6.0449MHz fINB = 7.5099MHz fCLK = 80.0006MHz AINA = -0.46dBFS FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) AMPLITUDE (dB) CHA MAX1181 toc01 0 -10 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1181 toc02 FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) 0 5 10 15 20 25 30 35 40 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX1181 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) -40 -50 -60 -20 -30 CHA 0 -40 -50 -60 -20 -30 -40 -50 -60 -70 -70 -80 -80 -80 -90 -90 -90 -100 -100 -100 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 CHB fINA = 40.4202MHz fINB = 47.0413MHz fCLK = 80.0006MHz AINB = -0.53dBFS -10 -70 0 40 0 5 10 15 20 25 30 35 40 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TWO-TONE IMD PLOT (8192-POINT RECORD, COHERENT SAMPLING) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY -30 61 fIN2 59 SNR (dB) -40 -50 -60 2nd ORDER IMD -70 CHA 60 -80 61 60 SINAD (dB) -20 fIN1 MAX1181 toc08 fIN1 = 38.1546MHz fIN2 = 41.9632MHz fCLK = 80.0006MHz AIN1 = AIN2 = -6dBFS MAX1181 toc07 0 CHB 58 CHA MAX1181 toc09 ANALOG INPUT FREQUENCY (MHz) -10 AMPLITUDE (dB) fINA = 40.4202MHz fINB = 47.0413MHz fCLK = 80.0006MHz AINA = -0.52dBFS AMPLITUDE (dB) -30 0 -10 AMPLITUDE (dB) AMPLITUDE (dB) -20 CHB FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1181 toc05 fINA = 19.9123MHz fINB = 24.9123MHz fCLK = 80.0006MHz AINB = -0.53dBFS MAX1181 toc04 0 -10 FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1181 toc06 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) 59 58 57 57 56 56 CHB -90 55 -100 5 10 15 20 25 30 35 55 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED) CHB CHA 77 6 MAX1181 toc12 80 MAX1181 toc10 -65 -68 40 MAX1181 toc11 0 4 CHA -74 74 GAIN (dB) -71 SFDR (dBc) 2 THD (dBc) MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs 71 0 -2 CHB -4 -77 68 -6 -80 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) 6 -8 65 0 0 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) 1 10 100 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 1000 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs VIN = 100mVP-P 4 60 58 SNR (dB) 0 -2 -4 SINAD (dB) 60 2 GAIN (dB) SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT POWER (fIN = 20MHz) MAX1181 toc14 65 MAX1181 toc13 6 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 20MHz) 55 MAX1181 toc15 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED) 50 56 54 52 -6 1 10 100 -8 -7 -6 -5 -4 -3 -2 -1 0 -9 -8 -7 -6 -5 -4 -3 -2 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT POWER (dBFS) ANALOG INPUT POWER (dBFS) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 20MHz) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 20MHz) INTEGRAL NONLINEARITY (BEST-STRAIGHT-LINE FIT) -55 85 -60 80 -70 -75 70 65 60 -85 -90 -95 -100 55 50 45 40 -8 -7 -6 -5 -4 -3 -2 -1 MAX1181 toc18 0.6 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 128 256 384 512 640 768 896 1024 ANALOG INPUT POWER (dBFS) ANALOG INPUT POWER (dBFS) DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) 0.6 GAIN ERROR (LSB) 0.4 3 0.2 0 -0.2 -0.4 -0.6 CHB 2 1 0 5 CHB 3 OFFSET ERROR (LSB) 0.8 CHA MAX11811 toc21 4 MAX1181 toc19 1.0 MAX1181 toc20 -9 0 0.4 75 -80 0.8 INL (LSB) -65 -1 1.0 MAX1181 toc17 MAX1181 toc16 100 95 90 SFDR (dBc) THD (dBc) -9 1000 -40 -45 -50 DNL (LSB) 50 45 -8 1 -1 CHA -3 -1 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -2 -40 -5 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX1181 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) 90 IVDD (mA) 80 OE = PD = OVDD 1.6 80 IVDD (μA) 90 2.0 MAX11811 toc23 100 MAX1181 toc22 100 ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY ANALOG SUPPLY CURRENT vs. TEMPERATURE 1.2 70 70 0.8 60 60 0.4 0 50 50 2.85 3.00 3.15 3.30 3.45 -40 3.60 -15 10 35 60 2.70 85 3.15 3.30 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 2.075 MAX1181 toc26 fINA = 24.9123MHz SFDR MAX1181 toc25 80 2.065 70 VREFOUT (V) SNR/SINAD, -THD/SFDR (dB, dBc) 3.00 VDD (V) SNR/SINAD, -THD/SFDR vs. CLOCK DUTY CYCLE 75 2.85 TEMPERATURE (°C) VDD (V) -THD 65 SNR 2.055 2.045 60 SINAD 55 2.035 50 2.025 35 40 45 50 55 60 65 2.70 2.85 3.00 CLOCK DUTY CYCLE (%) 3.15 3.30 3.45 3.60 VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE OUTPUT NOISE HISTOGRAM (DC INPUT) 140000 MAX11811 toc27 2.10 2.08 MAX1181 toc28 2.70 MAX1181 toc24 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE IVDD (mA) 129377 120000 100000 2.06 COUNTS VREFOUT (V) MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs 2.04 80000 60000 40000 2.02 20000 0 2.00 -40 -15 10 35 TEMPERATURE (°C) 8 60 85 0 965 N-2 N-1 N 730 0 N+1 N+2 DIGITAL OUTPUT NOISE _______________________________________________________________________________________ 3.45 3.60 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs PIN NAME 1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor. FUNCTION 2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. The analog supply voltage accepts a 2.7V to 3.6V input range. 3, 7, 10, 13, 16 GND Analog Ground 4 INA+ Channel ‘A’ Positive Analog Input. For single-ended operation, connect signal source to INA+. 5 INA- Channel ‘A’ Negative Analog Input. For single-ended operation, connect INA- to COM. 8 INB- Channel ‘B’ Negative Analog Input. For single-ended operation, connect INB- to COM. 9 INB+ Channel ‘B’ Positive Analog Input. For single-ended operation, connect signal source to INB+. 12 CLK Converter Clock Input 17 T/B T/B selects the ADC digital output format. High: Two’s complement. Low: Straight offset binary. 18 SLEEP 19 PD Power-Down Input. High: Power-down mode. Low: Normal operation. 20 OE Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. 21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B 22 D8B Three-State Digital Output, Bit 8, Channel B 23 D7B Three-State Digital Output, Bit 7, Channel B 24 D6B Three-State Digital Output, Bit 6, Channel B 25 D5B Three-State Digital Output, Bit 5, Channel B 26 D4B Three-State Digital Output, Bit 4, Channel B 27 D3B Three-State Digital Output, Bit 3, Channel B 28 D2B Three-State Digital Output, Bit 2, Channel B 29 D1B Three-State Digital Output, Bit 1, Channel B 30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B 31, 34 OGND Output Driver Ground 32, 33 OVDD Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. The digital supply voltage accepts a 1.7V to 3.6V input range. 35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A 36 D1A Three-State Digital Output, Bit 1, Channel A 37 D2A Three-State Digital Output, Bit 2, Channel A 38 D3A Three-State Digital Output, Bit 3, Channel A 39 D4A Three-State Digital Output, Bit 4, Channel A Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. _______________________________________________________________________________________ 9 MAX1181 Pin Description Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1181 Pin Description (continued) PIN NAME FUNCTION 40 D5A Three-State Digital Output, Bit 5, Channel A 41 D6A Three-State Digital Output, Bit 6, Channel A 42 D7A Three-State Digital Output, Bit 7, Channel A 43 D8A Three-State Digital Output, Bit 8, Channel A 44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A 45 REFOUT 46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 1nF capacitor. 47 REFP Positive Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 48 REFN Negative Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. — EP Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. Exposed Paddle. Connect to analog ground. Detailed Description The MAX1181 uses a nine-stage, fully-differential pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Counting the delay through the output latch, the clockcycle latency is five clock cycles. 1.5-bit (two-comparator) flash ADCs convert the heldinput voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held-input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track-andhold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a and S5b are closed. The fully-differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on 10 capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1181 to track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD / 2) for optimum performance. Analog Inputs and Reference Configurations The full-scale range of the MAX1181 is determined by the internally generated voltage difference between REFP (V DD / 2 + V REFIN / 4) and REFN (V DD / 2 VREFIN / 4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD / 2) and REFN are internally buffered low-impedance outputs. The MAX1181 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In the internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor divider, if an application requires a reduced full-scale range. ______________________________________________________________________________________ Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Σ T/H FLASH ADC x2 VIN VOUT Σ T/H FLASH ADC DAC 1.5 BITS x2 VOUT DAC 1.5 BITS 2-BIT FLASH ADC STAGE 1 STAGE 8 STAGE 2 2-BIT FLASH ADC STAGE 9 STAGE 1 DIGITAL CORRECTION LOGIC T/H VINA MAX1181 VIN D9A–D0A STAGE 8 STAGE 9 DIGITAL CORRECTION LOGIC T/H 10 STAGE 2 VINB 10 D9B–D0B VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED) Figure 1. Pipelined Architecture––Stage Blocks For stability and noise filtering purposes, bypass REFIN with a > 10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become lowimpedance outputs. In the buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a > 10kΩ resistor. In the unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources. Clock Input (CLK) The MAX1181’s CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNR = 20 ✕ log10 (1 / [2π x fIN ✕ tAJ]), where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1181 clock input operates with a voltage threshold set to VDD / 2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics table. System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1181 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B. Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE) All digital outputs, D0A–D9A (Channel A) and D0B–D9B (Channel B), are TTL/CMOS logic-compatible. There is a ______________________________________________________________________________________ 11 MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b INTERNAL BIAS COM HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 OUT INBS4b MAX1181 C2b C1b S3b S5b S2b INTERNAL BIAS COM Figure 2. MAX1181 T/H Amplifiers five clock cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A–D9A and D0B–D9B should 12 be kept as low as possible (< 15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1181, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance ______________________________________________________________________________________ Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1181 5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT tCLK CLOCK INPUT tD0 tCH tCL DATA OUTPUT D9A–D0A N-6 N-5 N-4 N-3 N-2 N-1 N N+1 DATA OUTPUT D9B–D0B N-6 N-5 N-4 N-3 N-2 N-1 N N+1 Figure 3. System Timing Diagram Table 1. MAX1181 Output Codes For Differential Inputs STRAIGHT OFFSET BINARY T/B = 0 DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT VREF ✕ 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111 VREF ✕ 1/512 + 1 LSB 10 0000 0001 00 0000 0001 0 Bipolar Zero 10 0000 0000 00 0000 0000 -VREF ✕ 1/512 -VREF ✕ 511/512 - 1 LSB - FULL SCALE + 1 LSB - FULL SCALE 01 1111 1111 00 0000 0001 00 0000 0000 11 1111 1111 10 0000 0001 10 0000 0000 -VREF ✕ 512/512 TWO’S COMPLEMENT T/B = 1 *VREF = VREFP - VREFN of the MAX1181 small-series resistors (e.g., 100Ω), add to the digital output paths, close to the MAX1181. Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid. Power-Down (PD) and Sleep (SLEEP) Modes The MAX1181 offers two power-save modes; sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled) and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power-down. Pulling OE high, forces the digital outputs into a high-impedance state. Applications Information Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a VDD / 2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed operational amplifiers. The user may select the RISO and CIN values to optimize the filter performance to suit a particular application. For the application in Figure 5, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. ______________________________________________________________________________________________________ 13 MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs The 22pF C IN capacitor acts as a small bypassing capacitor. OE Using Transformer Coupling An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully-differential signal, required by the MAX1181 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. In general, the MAX1181 provides better SFDR and THD with fully-differential input signals, than a singleended drive, especially for high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only require half the signal swing compared to single-ended mode. Single-Ended AC-Coupled Input Signal Figure 7 shows an AC-coupled, single-ended application. Amplifiers, like the MAX4108, provide high-speed, high bandwidth, low-noise, and low distortion to maintain the integrity of the input signal. Typical QAM Demodulation Application The most frequently used modulation technique for digital communications application is the Quadrature Amplitude Modulation (QAM). QAMs are typically found in spread-spectrum based systems. A QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 degrees phase-shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 8 displays the demodulation process performed in the analog domain, using the dual-matched, 3V, 10-bit ADCs, MAX1181 and the MAX2451 quadrature demodulators, to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1181, the mixed-down signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters which remove any unwanted images from the mixing process, enhances the overall signal-to-noise (SNR) performance, and minimizes intersymbol interference. 14 tDISABLE tENABLE OUTPUT D9A–D0A HIGH IMPEDANCE OUTPUT D9B–D0B HIGH IMPEDANCE VALID DATA VALID DATA HIGH IMPEDANCE HIGH IMPEDANCE Figure 4. Output Timing Diagram Grounding, Bypassing, and Board Layout The MAX1181 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separate ground and power planes, produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADCs package. The two ground planes should be joined at a single point, such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channelto-channel crosstalk. Keep all signal lines short and free of 90 degree turns. ______________________________________________________________________________________ Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1181 +5V 0.1μF LOWPASS FILTER INA+ MAX4108 RISO 50Ω 0.1μF 300Ω CIN 22pF 0.1μF -5V 600Ω 600Ω 300Ω COM 0.1μF +5V +5V 0.1μF 600Ω INPUT 0.1μF LOWPASS FILTER MAX4108 300Ω -5V 0.1μF INA- MAX4108 RISO 50Ω 300Ω CIN 22pF 0.1μF -5V 300Ω 300Ω +5V 600Ω MAX1181 0.1μF LOWPASS FILTER INB+ MAX4108 RISO 50Ω 0.1μF 300Ω CIN 22pF 0.1μF -5V 600Ω 600Ω 300Ω 0.1μF +5V +5V 0.1μF 600Ω INPUT 0.1μF LOWPASS FILTER MAX4108 300Ω -5V 0.1μF INB- MAX4108 RISO 50Ω 300Ω -5V CIN 22pF 0.1μF 300Ω 300Ω 600Ω Figure 5. Typical Application for Single-Ended-to-Differential Conversion ______________________________________________________________________________________ 15 MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Dynamic Parameter Definitions 25Ω Aperture Jitter INA+ 22pF Figure 9 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. 0.1μF 1 VIN N.C. T1 6 Aperture Delay 5 2 3 4 Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9). COM 2.2μF 0.1μF MINI-CIRCUITS TT1–6 Signal-to-Noise Ratio (SNR) 25Ω INA22pF MAX1181 25Ω INB+ 22pF 1 N.C. T1 6 2 5 3 4 2.2μF The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N-Bits): SNR[max] = 6.02 ✕ N + 1.76 In reality, there are other noise sources besides quantization noise; thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. 0.1μF VIN For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). 0.1μF MINI-CIRCUITS TT1–6 25Ω INB22pF Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Figure 6. Transformer-Coupled Input Drive Effective Number of Bits (ENOB) Static Parameter Definitions ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from: Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1181 are measured using the best straight-line fit method. ENOB = SINAD −1.76 6.02 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. 16 ⎛ V2 2 + V3 2 + V4 2 + V5 2 THD = 20 × log10 ⎜ ⎜⎜ V1 ⎝ ______________________________________________________________________________________ ⎞ ⎟ ⎟⎟ ⎠ Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1181 REFP VIN 0.1μF 1kΩ RISO 50Ω INA+ MAX4108 100Ω CIN 22pF 1kΩ COM REFN 0.1μF RISO 50Ω INA- 100Ω CIN 22pF REFP VIN 0.1μF MAX1181 1kΩ RISO 50Ω INB+ MAX4108 100Ω CIN 22pF 1kΩ REFN 0.1μF RISO 50Ω INB- 100Ω CIN 22pF Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive MAX2451 INA+ INA0° 90° MAX1181 DSP POST PROCESSING INB+ INBDOWNCONVERTER ÷8 Figure 8. Typical QAM Application, Using the MAX1181 ______________________________________________________________________________________ 17 MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. CLK Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. ANALOG INPUT tAD tAJ Intermodulation Distortion (IMD) SAMPLED DATA (T/H) T/H TRACK HOLD The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale. TRACK Figure 9. T/H Aperture Timing Functional Diagram VDD OGND OVDD GND INA+ PIPELINE ADC T/H 10 DEC OUTPUT DRIVERS 10 D9A–D0A INA- CONTROL CLK OE INB+ T/H PIPELINE ADC 10 DEC OUTPUT DRIVERS 10 D9B–D0B INB- REFERENCE MAX1181 REFOUT REFN COM REFP 18 REFIN ______________________________________________________________________________________ T/B PD SLEEP Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs 48L,TQFP.EPS PACKAGE OUTLINE, 48L TQFP, 7x7x1.0mm EP OPTION 21-0065 G 1 2 ______________________________________________________________________________________ 19 MAX1181 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX1181 Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 48L TQFP, 7x7x1.0mm EP OPTION 21-0065 G 2 2 Revision History Pages changed at Rev 1: 1–19 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.