STSLVDSP27
8-bit low voltage serializer with 1.8V high speed
dual differential line drivers and embedded DPLL
Features
■
Sub-low voltage differential signaling:
VOD = 150mV with RT = 100Ω, CL = 10pF
■
Clock range: 4 to 27 MHz in parallel mode,
BYP = Gnd
■
Operative frequency serial mode, BYP = VDD;
DIN0 to DOUT, CLKIN to CLKOUT,
fOPR = 1 to 208 MHz max
Flip-Chip20
■
Embedded DPLL requires no external
components
■
Output voltage rise and fall times
trVOD = tfVOD = 610ps typ at fOPR = 208MHz
■
High speed propagation delay times
tpLH~tpHL= 2.1ns typ at VDD = 3.0V; VIO = 1.8V
■
Operating voltage range:
VDD (OPR) = 2.5V to 3.6V
VIO (OPR) = 1.65V to 1.95V
■
High impedance on driver outputs
IOZ = 1µA max; EN = Gnd; VO = Gnd or VIO
■
Low voltage CMOS input threshold
(DIN0-DIN7, CLKIN, EN, BYP, DVO, DV1)
VIL = 0.3 x VDD max; VIH = 0.7 x VDD min
■
3.6V tolerant on all inputs
(DIN0-DIN7, CLKIN, EN, BYP, DV0, DV1)
■
Lead-free Flip-Chip package
■
SMIA CCP1 (MIPI CSI-1) compatible PHY
Description
The STSLVDSP27 is an 8:1 bit serializer with
embedded DPLL. The dual differential line drivers
implement the electrical characteristics of sub-low
voltage differential signaling (subLVDS), bringing
out the serialized data and related synchronous
clock signal. The STSLVDSP27
serializer IC is provided with two power supply
rails, VDD and VIO. The first supply is related to
the logic levels of the input data (DIN0-DIN7,
CLKIN) and Enables (EN, BYP, DV0, DV1) pins.
VIO provides the power supply to the output
current drivers in the device. VIO is always
expected to be a nominal 1.8V. VDD depends on
the application, but will always be equal to or
higher than VIO. In order to minimize static current
consumption, it is possible to shut down the
transmitters when the interface is not used by
setting a power-down (EN) pin. This operation
reduces the maximum current consumption to
20µA, making this device ideal for portable
applications like mobile phones and portable
battery equipment. Simplified functionality can be
reached using the BYP select pin, which disables
the internal DPLL circuitry. When this pin is High
the device can work with serialized signals from
DIN0 input only. A synchronous CLKIN signal
must be provided and it will be put-out using subLVDS level by CLKOUT port; the sub-LVDS data
will be put-out by DOUT port at a maximum
frequency of 208Mhz. This innovative device
provides an optimized high-speed link solution
from different CMOS sensor devices (parallel or
serial outputs) to more advanced graphic
controllers in mobile phone applications. All inputs
and outputs are equipped with protection circuits
against static discharge, providing ESD immunity
from transient excess voltage. The STSLVDSP27
is designed for operation over the commercial
temperature range -40°C to 85°C.
Order code
Part number
Temperature range
Package
Packaging
STSLVDSP27BJR
-40 to 85 °C
Flip-Chip20 (Tape & Reel)
3000 parts per reel
June 2007
Rev. 1
1/23
www.st.com
23
STSLVDSP27
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Test circuits and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
STSLVDSP27
1
Block diagram
Figure 1.
Simplified block diagram typical application
Block diagram
3/23
Pin configuration
STSLVDSP27
2
Pin configuration
Figure 2.
Pin configuration and logic diagram (Top view - Bumps are on the other side)
Table 1.
Pin description
PlN N°
Symbol
B1
DIN0
A1, A2, A3, A4, B4, C4, D4
DIN1-DIN7
D1, C1
DOUT+, DOUT-
B3
CLKIN
D3, C3
CLKOUT+, CLKOUT-
C2, D2
DV0, DV1
B2
GND
Ground
E1
VDD
Main power supply voltage
E2
VIO
SubLVDS bus output supply voltage
E3
EN
CMOS main chip enable input
E4
BYP
CMOS by-pass select input
4/23
Name and function
CMOS parallel/serial data inputs
CMOS parallel data inputs
SubLVDS driver data outputs
CMOS parallel/serial clock input
SubLVDS driver clock outputs
CMOS data valid inputs
STSLVDSP27
Table 2.
Pin configuration
Truth table (bypass functionality: DIN0 => DOUT, CLKIN => CLKOUT; main chip
Enable(1) functionality)
Controls
Input
Differential outputs
EN
BYP
DV0
DV1
DIN0
DIN1-7 CLKIN
DOUT+
DOUT-
CLKOUT+
CLKOUT-
L
X
X
X
X
X
X
Z
Z
Z
Z
H
H
X
X
L
X
L
L
H
L
H
H
H
X
X
L
X
H
L
H
H
L
H
H
X
X
H
X
L
H
L
L
H
H
H
X
X
H
X
H
H
L
H
L
1. All differential outputs are put in high impedance vs gnd only; the internal DPLL circuit is put in shutdown mode to obtain
minimum power consumption.
Note:
n:0..1; Z = High Impedance, X = Don’t care
Table 3.
Truth table (data valid functionality)
Controls
Input
Differential outputs
EN
BYP
DV0(1)
DV1(1)
DIN0
H
L
L
X
X
X
H
L
X
L
X
X
DIN1-7 CLKIN
DOUT+
DOUT-
CLKOUT+
CLKOUT-
X
H
L
H
L
X
H
L
H
L
1. An AND gate is designed on Data Valid Inputs (DV0, DV1) to enable the standard functionality; only when the
DV0=DV1="H" the device will work according to description in main page
Note:
n:0..1; Z = High Impedance, X = Don’t care
5/23
Maximum ratings
STSLVDSP27
3
Maximum ratings
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
Supply voltage
-0.5 to 4.6
V
VIO
SubLVDS bus supply voltage
-0.5 to 4.6
V
VI
DC input voltage (DIN0-DIN7, BYP, CLKIN, EN, DV0, DV1)
-0.5 to 4.6
V
VO
DC output voltage (DOUT+,DOUT-,CLKOUT+,CLKOUT-)
-0.5 to (VIO + 0.5)
V
±2
KV
-65 to +150
°C
ESD
Electrostatic discharge protection
IEC61000-4-2 Contact R = 330Ω, C = 150pF (All Pins vs GND)
TSTG
Storage temperature range
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these condition is not implied.
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD
Main supply voltage (1) (2)
VIO
SubLVDS bus supply voltage
VDD_NOISE Peak-to-peak permitted main supply voltage noise
Min.
Typ.
Max.
Unit
2.5
3.0
3.6
V
1.65
1.80
1.95
V
100
mV
120
Ω
(2)
RT
Termination resistance (per pair differential output line)
CL
Termination capacitance (per line vs GND Pin)
TA
Operating ambient temperature range
-40
85
°C
TJ
Operating junction temperature range
-40
125
°C
10
ns
tR, tF
Rise and fall time (DIN0-DIN7, BYP, CLKIN, EN, DV0,
DV1; 10% to 90%; 90% to 10%)
80
100
10
pF
1. VDD Main supply voltage in serial mode (BYP = VDD) can be reduced down to 1.65V for typical 1.8V input signals
2. VDD Main supply voltage in parallel mode (BYP = GND) can reach 2.5V when VDD_NOISE = 100mV and VDD = 2.55V
6/23
STSLVDSP27
Electrical characteristics
4
Electrical characteristics
Table 6.
Electrical characteristics (over recommended operating conditions unless otherwise
noted. All typical values are at TA = 25°C, and VDD = 3.0V, VIO = 1.8V)
Symbol
Min.
Typ.
Max.
Unit
RT = 100Ω ± 1%
VIO/20.1
VIO/2
VIO/2+
0.1
V
Common mode output
voltage change between
VCM(SS)
logic state ("L" and "H")
(Figure 5.)
RT = 100Ω ± 1%
-20
20
mV
Common mode peak-topeak output voltage change
VCM(PP)
between logic state
("L" and "H") (Figure 5.)
RT = 100Ω ± 1%
-40
40
mV
200
mV
20
mV
VCM
Parameter
Common mode output
voltage (Figure 3.)
Test conditions
|VOD|
Differential output voltage
(Figure 3.)
RT = 100Ω ± 1%
100
ΔVOD
Differential output voltage
change between logic state
("L" and "H")
RT = 100Ω ± 1%
-20
RT = 100Ω ± 1% BYP=VDD; EN=VDD
fCLKIN = 208MHz, fDIN0 = 208MHz
45
50
55
%
Clock duty cycle@208MHz
differential output voltage
DCVOD
CLKOUT+, CLKOUT-,
DOUT+, DOUT-
150
IIO
Driver output current
CLKOUT+, CLKOUT-,
DOUT+, DOUT-
RT = 100Ω ± 1%
1
1.5
2
mA
RO
Driver output impedance
(Single ended)
CLKOUT+, CLKOUT-,
DOUT+, DOUT- (Figure 8.)
VCM = VIO/2 + 100mV and
VIO/2 -100mV
40
100
140
Ω
DRO
Driver output impedance
mismatch between RODOUT,
ROCLKOUT
10
%
7/23
Electrical characteristics
Table 6.
Symbol
STSLVDSP27
Electrical characteristics (over recommended operating conditions unless otherwise
noted. All typical values are at TA = 25°C, and VDD = 3.0V, VIO = 1.8V)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
EN=VDD, BYP=VDD or GND,
DIN0-DIN7=VDD or GND
No load (RT = ∞)
15
EN=VDD, BYP=VDD or GND,
DIN0-DIN7=VDD or GND
RT = 100Ω ± 1%
15
EN=VDD, BYP=VDD(DPLL="OFF")
RT = 100Ω ± 1%, CL = 10pF per line,
DV0=DV1=VDD,
fDIN0 and CLKIN = 208 MHz
(VIL and VIH levels)
12
EN=VDD, BYP=Gnd(DPLL="ON") RT
= 100Ω ± 1%, CL = 10pF per line,
DV0 = DV1= VDD, fCLKOUT = 160MHz
fDIN0-DIN7,CLKIN = 22 MHz
(VIL and VIH levels)
20
ISOFF
Shutdown supply current
(IIO + IDD)
EN = GND, VDD = 2.7V to 3.6V
VIO = 1.65V to 1.95V
DIN0-DIN7, CLKIN, BYP = GND or
VDD
20
µA
VIH
High level input voltage
(DIN0-DIN7, BYP, CLKIN,
EN, DV0, DV1)
VDD = 2.7V to 3.6V,
VIO = 1.65V to 1.95V
0.7xVDD
3.6
V
VIL
Low level input voltage
(DIN0-DIN7, BYP, CLKIN,
EN, DV0, DV1)
VDD = 2.7V to 3.6V,
VIO = 1.65V to 1.95V
0
0.3xVDD
V
IIH
High level input current
(DIN0-DIN7, BYP, CLKIN,
EN, DV0, DV1)
VIH = 0.7 x VDD
±1
µA
IIL
Low level input current
(DIN0-DIN7, BYP, CLKIN,
EN, DV0, DV1)
VIL = 0.3 x VDD
±1
µA
IOZ
High impedance output
current CLKOUT+,CLKOUT-, VO = 0 or VCC
DOUT+, DOUT-
±1
µA
IS
8/23
Supply current (IIO + IDD)
mA
STSLVDSP27
Table 7.
Electrical characteristics
Serial switching characteristics (DPLL = "OFF", RT = 100Ω ±1%, CL = 10pF, over
recommended operating conditions unless otherwise noted. Typical values are referred to
TA = 25°C and VDD = 3.0V, VIO = 1.8V)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
trVOD
Rise time
differential output voltage
(20% to 80%) (Figure 4.)
trDIN = 4.9ns (10% to 90%);
fDIN = 10MHz, PulseWidthDIN = 50ns
400
610
1000
ps
tfVOD
Fall time
differential output voltage
(80% to 20%) (Figure 4.)
trDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
400
610
1000
ps
tPLHD
Differential propagation
delay time (DIN to DOUT)
(Low to High) (Note: 1)
(Figure 4.)
trDIN = 4.9ns (10% to 90%);
tfDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
1.0
2.1
2.8
ns
tPHLD
Differential propagation
delay time (DIN to DOUT)
(Low to High) (Note: 1)
(Figure 4.)
tfDIN = 4.2ns (10% to 90%);
fDIN = 10MHz, PulseWidthDIN = 50ns
1.0
2.1
2.8
ns
tEN
Enable delay time
(EN to DOUT: tPLZ, tPHZ)
(Figure 7.)
trEN = 2.0ns (10% to 90%);
tfEN = 2.0ns (90% to 10%)
20
µs
tDIS
Disable delay time
(EN to DOUT: tPLZ, tPHZ)
(Figure 7.)
trEN = 2.0ns (10% to 90%);
tfEN = 2.0ns (90% to 10%)
1000
ns
fOPR
BYP = VDD
trDIN0,CLKIN=1ns (10% to 90%);
Operating frequency serial
tfDIN0,CLKIN=1ns (90% to 10%)
mode without DPLL
fDIN0,CLKIN = 208MHz
PulseWidthDIN0,CLKIN = 2.4ns
208
MHz
Differential skew between trDIN = 4.9ns (10% to 90%);
tSKEW1 signals on each differential tfDIN = 4.2ns (90% to 10%);
pair (tPLHD - tPHLD)
fDIN = 10MHz, PulseWidthDIN = 50ns
150
ps
Channel to channel skew
between any two signals
tSKEW2
on each different
differential pair (Figure 6.)
200
ps
Note:
1
trDIN = 4.9ns (10% to 90%);
tfDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
1
50% VDIN to 50% VDOUT
9/23
Electrical characteristics
Table 8.
Symbol
STSLVDSP27
Parallel switching characteristics (DPLL = "ON", RT = 100Ω ±1%, CL = 10pF, over
recommended operating conditions unless otherwise noted. Typical values are referred to
TA = 25°C and VDD = 3.0V, VIO = 1.8V)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
trVOD
Rise time
differential output voltage
(20% to 80%) (Figure 4.)
trDIN = 4.9ns (10% to 90%);
fDIN = 10MHz, PulseWidthDIN = 50ns
400
610
1000
ps
tfVOD
Fall time
differential output voltage
(80% to 20%) (Figure 4.)
trDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
400
610
1000
ps
Differential propagation
delay time DIN0 (CLKIN to
tPLHDIN0
DOUT) (Low to High)
(Note 2) (Figure 10.)
trDIN0-DIN7,CLKIN=4.9ns (10% to 90%);
tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%);
fDIN0-DIN7,CLKIN=22MHz,
PulseWidthDIN = 50ns
8
ns
Differential propagation
delay time DIN0 (CLKIN to
tPHLDIN0
DOUT) (High to Low)
(Note 2) (Figure 10.)
trDIN0-DIN7,CLKIN=4.2ns (90% to 10%);
tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%);
fDIN0-DIN7,CLKIN=22MHz,
PulseWidthDIN = 50ns
8
ns
Differential propagation
delay time DIN7 (CLKIN to
tPLHDIN7
DOUT) (Low to High)
(Note 2) (Figure 10.)
trDIN0-DIN7,CLKIN=4.9ns (10% to 90%);
tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%);
fDIN0-DIN7,CLKIN=22MHz,
PulseWidthDIN = 50ns
53
ns
Differential propagation
delay time DIN7 (CLKIN to
tPHLDIN7
DOUT) (High to Low)
(Note 2) (Figure 10.)
trDIN0-DIN7,CLKIN=4.2ns (90% to 10%);
tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%);
fDIN0-DIN7,CLKIN=10MHz,
PulseWidthDIN = 50ns
53
ns
trDIN0-DIN7,CLKIN=4.9ns (10% to 90%);
tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%);
fDIN0-DIN7,CLKIN=10MHz,
PulseWidthDIN = 50ns
11
ns
tOCD
Differential propagation
delay time (CLKIN to
DOUT first positive edge)
(Low to High) (Figure 10.)
Set-up time (DIN0-DIN7,
DV to CLKIN) (LH or HL to
tSU_CLK
positive CLKIN edge)
(Figure 11.)
trDIN0-DIN7,CLKIN=4.9ns (10% to 90%);
tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%);
fDIN0-DIN7,CLKIN=4 to 22MHz,
PulseWidthDIN = 50ns
12
ns
Hold time (CLKIN to DIN0DIN7, DV) (positive CLKIN
edge to LH or HL DIN,DV
transition)
(Figure 11.)
trDIN0-DIN7,CLKIN=4.9ns (10% to 90%);
tfDIN0-DIN7,CLKIN=4.2ns (90% to 10%);
fDIN0-DIN7,CLKIN=4 to 22MHz,
PulseWidthDIN = 50ns
10
ns
tEN
Enable delay time
(EN to DOUT: tPLZ, tPHZ)
(Figure 7.)
trEN = 2.0ns (10% to 90%);
tfEN = 2.0ns (90% to 10%)
20
µs
tDIS
Disable delay time
(EN to DOUT: tPLZ, tPHZ)
(Figure 7.)
trEN = 2.0ns (10% to 90%);
tfEN = 2.0ns (90% to 10%)
1000
ns
fOPR
Operating frequency
parallel mode with DPLL
BYP = GND, fDIN0-DIN7,CLKIN=4 to
27MHz PulseWidthDIN0,CLKIN = 50%
trDIN0,CLKIN=3ns (10% to 90%);
tfDIN0,CLKIN=3ns (90% to 10%)
27
MHz
tH_CLK
10/23
4
STSLVDSP27
Table 8.
Electrical characteristics
Parallel switching characteristics (DPLL = "ON", RT = 100Ω ±1%, CL = 10pF, over
recommended operating conditions unless otherwise noted. Typical values are referred to
TA = 25°C and VDD = 3.0V, VIO = 1.8V)
Symbol
Parameter
Max.
Unit
216
MHz
Differential skew between trDIN = 4.9ns (10% to 90%);
tSKEW1 signals on each differential tfDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
pair (tPLHD - tPHLD)
150
ps
Channel to channel skew
between any two signals
tSKEW2
on each different
differential pair (Figure 6.)
200
ps
CLKOUT frequency
fCLKOUT
parallel mode with DPLL
Test Conditions
BYP = GND, fDIN0-DIN7,CLKIN=4 to
27MHz PulseWidthDIN0,CLKIN = 50%
trDIN0,CLKIN=3ns (10% to 90%);
tfDIN0,CLKIN=3ns (90% to 10%)
Min.
Typ.
32
trDIN = 4.9ns (10% to 90%);
tfDIN = 4.2ns (90% to 10%);
fDIN = 10MHz, PulseWidthDIN = 50ns
tDV
BYP = GND, fDIN0-DIN7,CLKIN=4 to
Data valid before CLKOUT 27MHz PulseWidthDIN0,CLKIN = 50%
time (Figure 12.)
trDIN0,CLKIN=3ns (10% to 90%);
tfDIN0,CLKIN=3ns (90% to 10%)
1
ns
tDH
Data valid hold after
CLKOUT time (Figure 12.)
BYP = GND, fDIN0-DIN7,CLKIN=4 to
27MHz PulseWidthDIN0,CLKIN = 50%
trDIN0,CLKIN=3ns (10% to 90%);
tfDIN0,CLKIN=3ns (90% to 10%)
2
ns
tPLLS
DPLL settling time (EN to
CLKOUT) 50% LH EN to
50% CLKOUT (first
negative edge) (Figure 9.)
trEN =2.0ns (10% to 90%)
tfEN =2.0ns (90% to 10%)
DV0=DV1=VDD; BYP= Gnd; DIN1DIN7=VDD or Gnd;
fCLKIN =4 to 27MHz
70
RMS cycle-to-cycle jitter
between CLKIN and
CLKOUT signals
trCLKIN = 4.9ns (10% to 90%);
tfCLKIN = 4.2ns (90% to 10%);
fCLKIN = 4 to 27MHz,
PulseWidthCLKIN =50%
100
Peak cycle-to-cycle jitter
between CLKIN and
CLKOUT signals
trCLKIN = 4.9ns (10% to 90%);
tfCLKIN = 4.2ns (90% to 10%);
fCLKIN = 4 to 27MHz,
PulseWidthCLKIN =50%
600
JCY-CY
Note:
µs
ps
1
50% VDIN to 50% VDOUT
2
50% CLKIN (positive edge) to 50% VDOUT (DIN0 will be referred to CLKOUT first positive
edge; DIN7 will be referred to CLKOUT eighth positive edge)
3
Power down can be guaranteed when VIO =1.8V, EN = GND, if low impedance < 1MΩ vs
GND is guaranteed on VDD pin
11/23
Electrical characteristics
Table 9.
STSLVDSP27
Capacitive characteristics
Test condition
Symbol
CIN
12/23
Parameter
Input capacitance (DIN0-DIN7,
CLKIN, EN, BYP, DV0, DV1)
TA = 25°C
VDD
(V)
2.7 to 3.6
Value
Min.
VIO = 1.65V to 1.95V,
VI = GND or VDD
Typ.
4
Unit
Max.
pF
STSLVDSP27
Test circuits and timing diagram
5
Test circuits and timing diagram
Figure 3.
Voltage and input current definition
VCM = (VD+ + VD-)/2
Note:
RT = 100 Ω ±1%
Figure 4.
Test circuit, timing and voltage definitions for differential output signal
Note:
RT = 100 Ω ±1%; CL = 10pF; trDIN = 4.9ns; tfDIN = 4.2ns; fDIN = 10MHz; PulseWidthDIN =
50ns.
13/23
Test circuits and timing diagram
STSLVDSP27
Figure 5.
Test circuit and definitions for the driver common mode output voltage
Note:
RT = 100 Ω ±1%; CL = 10pF; trDIN = 4.9ns; tfDIN = 4.2ns; fDIN = 10MHz; PulseWidthDIN =
50ns.
Figure 6.
tSKEW2
Note:
RT = 100 Ω ±1%; CL = 10pF; trDIN = 4.9ns; tfDIN = 4.2ns; fDIN = 10MHz; PulseWidthDIN =
50ns
14/23
STSLVDSP27
Test circuits and timing diagram
Figure 7.
tEN (tPZL, tPZH); tDIS (tPHZ, tPLZ)
Note:
RT = 100 Ω ±1%; CL = 10pF; trDIN = 2.0ns; tfDIN = 2.0ns; fEN = 1MHz; PulseWidthDIN =
500ns
Figure 8.
RO: Driver output impedance
Note:
RT = 100 Ω ±1%; CL = 10pF
ΔVX+ = VD+(VCM=1.0V) - VD+(VCM=0.8V); ΔVX- = VD-(VCM=1.0V) - VD-(VCM=0.8V);
R0+ = (RT/2 x ΔVX+)/(200mV - ΔVX+); R0- = (RT/2 x ΔVX-)/(200mV - ΔVX-)
15/23
Test circuits and timing diagram
Figure 9.
tPLLS
Note:
During tPLLS test DV0=DV1=VDD
16/23
STSLVDSP27
DOUT
CLKOUT
DV[0..1]
DIN[0..7]
CLKIN
P1
P1:
D0
Tocd
P 1:
D1
P1:
D3
P 1:
D4
P1:
D5
P2
P1:
D6
0 < Tocd < Tclkin
P1:
D2
Tclkin
P1:
D7
P2:
D0
P2:
D1
PN-1
P2:
D2
P2:
D3
PN-1:
D4
PN-1:
D5
PN
PN-1:
D6
PN-1:
D7
PN:
D0
PN:
D1
PN:
D2
PN:
D3
PN:
D4
PN:
D5
PN:
D6
PN:
D7
PN+1 data does not appear
in the output stream
PN+1
STSLVDSP27
Test circuits and timing diagram
Figure 10. General timing diagram (parallel mode)
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Test circuits and timing diagram
Figure 11. tCLKIN
Note:
tCLKIN
Figure 12. tCLKOUT
Note:
18/23
tCLKOUT
STSLVDSP27
STSLVDSP27
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
19/23
Package mechanical data
STSLVDSP27
Flip-Chip20 Mechanical Data
mm.
mils.
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.81
0.89
1.00
31.9
35.0
39.4
A1
0.15
0.24
0.35
5.9
9.4
13.8
A2
0.65
25.6
b
0.25
0.30
0.35
9.8
11.8
13.8
D
2.41
2.46
2.51
94.9
96.9
98.8
D1
E
2.00
1.93
1.98
78.7
2.03
76.0
78.0
E1
1.5
59.1
e
0.50
19.7
SE
0.25
9.8
79.9
7487339-D
20/23
STSLVDSP27
Package mechanical data
Tape & Reel Flip-Chip20 Mechanical Data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
180
13.2
7.086
C
12.8
D
20.2
0.795
N
60
2.362
T
Max.
0.504
0.519
14.4
0.567
Ao
2.13
2.23
2.33
0.084
0.088
0.092
Bo
2.62
2.72
2.82
0.103
0.107
0.111
Ko
1.05
1.15
1.25
0.041
0.045
0.049
Po
3.9
4.1
0.153
0.161
P
3.9
4.1
0.153
0.161
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Revision history
STSLVDSP27
7
Revision history
Table 10.
Revision history
Date
Revision
01-Jun-2007
1
22/23
Changes
Initial release.
STSLVDSP27
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