SUMMIT SMS47 MICROELECTRONICS, Inc. PRELIMINARY INFORMATION 1 (SEE LAST PAGE) Quad Programmable Precision Cascade Sequencer and Supervisory Controller FEATURES INTRODUCTION z Operational from any of four Voltage Monitoring Inputs z Programmable Power-up Cascade Sequencing z Programmability allows monitoring any voltage between 0.6V and 5.6V with no external components z Programmable 5mV steps in the low range z Programmable Watchdog Timer z Programmable Reset Pulse Width z Programmable Nonvolatile Combinatorial Logic for generation of Reset z Fault Status Register APPLICATIONS z Desktop/Notebook/Tablet Computers z Multi-voltage Systems z Telecom/Network Servers z Portable Battery-powered Equipment z Set-top Boxes z Data-storage Equipment The SMS47 is a nonvolatile user-programmable voltage supply cascade sequencer and supervisory circuit designed specifically for advanced systems that need to monitor multiple voltages. The SMS47 can monitor four separate voltages without the need of any external voltage divider circuitry unlike other devices that need factorytrimmed threshold voltages and external components to accommodate different supply voltages and tolerances. The SMS47 can also be used to enable DC/DC converters or LDOs to provide a closed loop cascading of the supplies during power-up. The SMS47 watchdog timer has a user programmable time-out period and it can be placed in an idle mode for system initialization or system debug. All of the functions are user accessible through an industry standard I2C 2-wire serial interface. Programming of configuration, control and calibration values by the user is simplified with the SMX3200 programming adapter and Windows GUI software obtainable from Summit Microelectronics. SIMPLIFIED APPLICATION DRAWING 5V I2C 7 0.1µF Reset# 6 9 10 12 VDD_CAP A2 A1 SDA SCL PUP#1 16 V0 2 V1 3 V2 14 V3 SMS47 PUP#2 1 MR# 15 WLDI GND 8 RESET# PUP#3 4 DC/DC 5 13 3.3V 2.5V DC/DC LDO 1.8V 11 2047 SAD 2.0 Applications Schematic using the SMS47 Controller to provide closed loop power-up cascade sequencing and supervisory functions. NOTE: THIS IS AN APPLICATIONS EXAMPLE ONLY. SOME PINS, COMPONENTS AND VALUES ARE NOT SHOWN. ©SUMMIT MICROELECTRONICS, Inc., 2005 Characteristics subject to change without notice • 1717 Fox Dr. • San Jose, CA 95131 • Phone 408-436-9890 • FAX 408-436-9897 • 2087 1.1 04/11/05 www.summitmicro.com 1 SMS47 Preliminary Information INTERNAL BLOCK DIAGRAM VDD_CAP CONFIGURATION REGISTER 50kΩ 11 RESET# MR# 1 V0 16 PROGRAMMABLE RESET PULSE GENERATOR NV DAC + – REF 4 PUP#1 PROGRAMMABLE POWER CASCADING V1 2 5 PUP#2 13 PUP#3 NV DAC + – REF NV DAC + 10 SCL 7 A2 6 A1 PROGRAMMABLE WATCHDOG TIMER – REF 9 SDA SERIAL BUS CONTROL LOGIC V2 3 V3 14 NV DAC + VDD_CAP – REF 50kΩ V0 V1 V2 V3 15 WLDI CONFIGURATION REGISTER SUPPLY ARBITRATION 12 8 VDD_CAP GND CASCADE SEQUENCING Time based sequencing has the ability to turn supplies on in a specific order. However, it cannot guarantee that each supply has reached valid voltage levels before the next supply is sequenced on. Cascade sequencing guarantees the supplies are enabled a programmed period of time after the previous voltage has reached its minimum programmed valid level. Figure 1 shows that each succeeding voltage must reach its minimum valid level before the timer is started to time the interval, t, for the next voltage. The duration of each t is programmable for each supply to supply transition. The next supply is not enabled until the timer has elapsed. See also Figure 5. 6V 5V 5V Valid 4V 3.3V Valid 3.3V V 2.5V 2V 1.8V 2.5V Valid 0V t t t T 2047 Fig01 Figure 1. Cascading Power Supplies 2 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information PIN CONFIGURATION MR# V1 V2 PUP#1 PUP#2 A1 A2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PIN NAMES V0 WLDI V3 PUP#3 VDD_CAP RESET# SCL SDA 2047 PCon 2.0 Pin Name 1 MR# 2 V1 Voltage supply and monitor input 3 V2 Voltage supply and monitor input 4 PUP#1 Power up permitted output 5 PUP#2 Power up permitted output 6 A1 Address input 7 A2 Address input 8 GND Power supply return 9 SD A Serial data I/O 10 SC L Serial data clock 11 RESET# 12 Function Manual reset input Reset out VDD_CAP Power supply output 13 PUP#3 14 V3 15 WLDI 16 V0 Power up permitted Voltage supply and monitor input Watchdog Timer interrupt Voltage supply and monitor input 2047 Pins Table 2.0 SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 3 SMS47 Preliminary Information ABSOLUTE MAXIMUM RATINGS* RECOMMENDED OPERATING CONDITIONS Temperature Under Bias ...................... –55°C to 125°C Storage Temperature ............................. –65°C to 150°C Lead Solder Temperature (10s) ........................... 300 °C Terminal Voltage with Respect to GND: V0, V1, V2, and V3 ......... –0.3V to 6.0V All Others ....................... –0.3V to 6.0V Junction Temperature.......................…….....…...150°C ESD Rating per JEDEC……………………..….…..2000V Latch-Up testing per JEDEC………..…….......…±100mA Industrial Temperature Range............... –40ºC to +85ºC. Commercial Temperature Range..............–5ºC to +70ºC. VSUPPLY Supply Voltage............................2.7V to 5.5V *Note - Stresses beyond the listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Data Retention………………….…………..…..100 Years Endurance……………………….…..…….100,000 Cycles VSUPPLY = Device supply voltage provided by the highest VX input. Package Thermal Resistance (θJA) 16 Lead SSOP…………………….………….…23oC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND) Symbol Parameter VSUPPLY Operating supply voltage ICC Supply current Notes Min. 1V Min. refers to a valid reset output being generated Read/Write operations: at least one of the VX inputs must be at or above VSUPPLY min. Max. Unit 1.0 5.5 V 2.7 5.5 V 400 µA 3 mA VDD_CAP = 5.5V; V0 trip point 4.7V; V1, V2, V3 = GND; MR# = VCC; all outputs floating Typ. 200 Configuration register access VPTH Programmable threshold Range range (low range) Reset threshold voltage range V0 to V3 (5mV increments) 0.6 1.875 V VPTH Programmable threshold Range range (high range) Reset threshold voltage range V0 to V3 (15mV increments) 1.8 5.625 V 1.0 % VPTHACC VHYST VOL VIL VIH Programmable threshold Accuracy VRST hysteresis Low voltage output VPTH is the programmed threshold setpoint within the VPTH Range –1.0 See Note 1 below VPTH 30 mV ISINK = 1mA, VVDD_CAP ≥ 2.7V 0.3 V ISINK = 200µA, VVDD_CAP = 1.0V 0.3 V 0.6 V Input threshold 0.7 ´ VCC V Note 1: Low Range Hysteresis = 4.2 X (Vtrip - 0.5 volts) mV. For Vtrip = 1.0 volts, Hysteresis = 2.1 mV (0.21 %), High Range Hysteresis = 12.6 X (Vtrip -0.5 volts) mV. For Vtrip = 5.0 volts, Hysteresis = 56.7 mV (1.13%). 4 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information AC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND, also see configuration registers) Symbol tPWDTO tPDLYX Parameter Programmable Watchdog timer period MR# pullup current TMR MR# input pulse width TDMRRST Delay from MR# low to RESET# low tDRST SUMMIT MICROELECTRONICS, Inc. Typ. Max. WD 1 WD 0 0 0 X 0 1 1 300 400 500 1 0 0 600 800 1000 1 0 1 1200 1600 2000 1 1 0 2400 3200 4000 1 1 1 4800 6400 8000 PUP#X-1 PUP#X-0 0 0 0 1 19 25 31 1 0 38 50 63 1 1 75 100 125 OFF Unit — 0ms Minimum ms — ms 100 µA 300 ns 200 ns RTO1 RTO0 0 0 19 25 31 ms 0 1 38 50 63 ms 1 0 75 100 125 ms 1 1 150 200 250 ms Programmable reset pulse width V in to RESET# delay Min. WD2 Programmable delay from VPTH to PUP# out IMR tPRTO Notes 100mV overdrive 2087 1.0 04/11/05 20 µs 5 SMS47 Preliminary Information PIN DESCRIPTIONS V0, V1, V2, V3 (16, 2, 3, 14) These inputs are used as the voltage monitor inputs and as the voltage supply for the SMS47. Internally they are diode ORed and the input with the highest voltage potential will be the default supply voltage (VDD_CAP). VPTH-UV V0 — V 3 The sensing threshold for each input is independently programmable in 5mV increments from 0.6V to 1.875V or 15mV increments from 1.8V to 5.625V. Also, the occurrence of an under- or over-voltage condition that is detected as a result of the threshold setting can be used to generate a RESET#. The programmable nature of the threshold voltage eliminates the need for external voltage divider networks. GND Power supply return. MR# (1) The manual reset input always generates a RESET# output whenever it is driven low. The duration of the RESET# output pulse will be initiated when MR# goes low and it will stay low for the duration of MR# low plus the programmed reset time-out period (tPRTO). If MR# is brought low during a power-on cascade of the PUP#s the cascade will be halted for the reset duration, and will then resume from the point at which it was interrupted. MR# must be held low during a configuration register write. This signal is pulled up internally through a 50kΩ resistor. RESET# (11) The reset output is an active low open drain output. It will be driven low whenever the MR# input is low or whenever an enabled under-voltage or over-voltage condition exists. The four voltage monitor inputs are always functioning, but their ability to generate a reset is programmable (configu- RESET# Figure 3. RESET# Timing ration register 4). Refer to Figures 2 and 3 for a detailed illustration of the relationship between MR#, RESET# and the VIN levels. VDD_CAP (12) The VDD_CAP pin connects to the internal supply voltage for the SMS47. A capacitor is placed on this pin to filter supply noise as well as hold up the device in the event of power failure. The voltage on this node is determined by the highest input voltage. Loading of this pin should be minimized to prevent excessive power dissipation in the part. WLDI (15) Watchdog timer input. A high-to-low transition on the WLDI input will clear the watchdog timer, effectively starting a new time-out period. This signal is pulled up internally through a 50kΩ resistor. If WLDI is stuck low and no high-to-low transition is received within the programmed tPWDTO period (programmed watchdog time-out) RESET# will be driven low. Refer to Figure 4 for a detailed illustration. Holding WLDI low will not block the watchdog from timing out and generating a reset. Refer to Figure 4 for a detailed illustration of the relationship between RESET# and WLDI. t0 tPWDTO t0 t0 MR# t0 t0 tPRTO RESET# tDMRRST RESET# tDRST tPRTO The RESET# output will be valid if any one of the four inputs is above 1V. However, for full device operation at least one of the inputs must be at 2.7V or higher. tPRTO tPRTO tPWDTO WLDI 2047 Fig04 3.0 Figure 4. Watchdog and WLDI Timing Figure 2. RESET# Timing with MR# 6 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information PIN DESCRIPTIONS (CONTINUED) A1,A2 (6, 7) A1 and A2 are the address inputs. When addressing the SMS47 configuration registers the address inputs distinguish which one of four possible devices sharing the common bus is being addressed. SDA (9) SDA is the serial data input/output pin. It should be tied to VDD_CAP through a pull-up resistor. SCL (10) SCL is the serial clock input. It should be tied to VDD_CAP through a pull-up resistor. PUP#1, PUP#2, PUP#3 (4, 5, 13) These are the power-up permitted (PUP) active low open drain outputs. The PUP pins are used when the SMS47 is programmed to provide the cascade sequencing of LDOs or DC/DC converters (see Figures 1 and 5 for illustrations of cascading). Each delay is independently enabled and programmable for its duration (configuration register 7). If all PUP# outputs are enabled the order of events would be as follows: V0 above threshold then delay to PUP#1 turning on; V1 above threshold then delay to PUP#2 turning on; V2 above threshold then delay to PUP#3 turning on. The delays are programmable. SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 7 SMS47 Preliminary Information DEVICE OPERATION VPTH0 V0 tPRTO RESET# tPDLY1 PUP1# VPTH1 V1 tPDLY2 PUP2# VPTH2 V2 tPDLY3 PUP3# V3 2047 Fig05 Figure 5. VX Input and Resulting PUP# Cascade (RESET# set to trip on V3 Undervoltage) VPTH0 V0 50ms PUP1# V1 PUP2# VPTH2 V2 50ms PUP3# 2047 Fig06 Figure 6. Timing with Register 7 Contents 22HEX 8 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information DEVICE OPERATION (CONTINUED) Cascading Enabled V0 >VPTH? No Yes tPDLY1 Turn On PUP#1 V1 >VPTH? No Yes tPDLY2 Turn On PUP#2 V2 >VPTH? No Yes tPDLY3 Turn On PUP#3 2047 Fig07 Figure 7. Cascade Flow Chart SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 9 SMS47 Preliminary Information CONFIGURATION REGISTERS SUPPLY AND MONITOR FUNCTIONS The V0, V1, V2, and V3 inputs are internally diode-ORed so that any one of the four can act as the device supply. The RESET# output will be guaranteed true so long as one of the four pins is at or above 1V. Note: for performing a Read or Write to the configuration register contents, at least one supply input must be above 2.7V. Read/Write operations require a 0.1µF capacitor from the VDD_CAP node to GND. For optimum performance connect capacitors from each of the Vx inputs to GND. Locate the capacitors as physically close to the SMS47 as possible. If cascading is enabled, the designer must insure V0 is the primary supply and is the first to become active. Associated with each input is a comparator with a programmable threshold for detection of under-voltage or overvoltage conditions on any of the four supply inputs. The threshold can be programmed in 5mV increments anywhere within the range of 0.6V to 1.875V or 15mV increments within the range of 1.8V to 5.625V. Configuration registers 0, 1, 2, and 3 adjust the thresholds for V0, V1, V2, and V3 respectively. If the value contained in any register is all zeroes, the corresponding threshold will be 0.6V. If the contents were low range 05HEX the threshold would then be 0.625V [0.6V + (5 × 0.005V)]. All four registers are configured as 8-Bit registers. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB 1 1 1 1 1 1 1 1 Highest threshold adjustment = 5.625V (High Range) 0 0 0 0 0 0 0 0 Lowest threshold adjustment = 0.6V (Low Range) 0 0 0 0 0 1 1 0 Threshold = 0.6V + (6×0.005V) = 0.625V (e.g.) Action Table 1. Configuration Registers 0, 1, 2, and 3 RESET FUNCTION AND THRESHOLD RANGE The reset output has four programmable sources for activation. Configuration register 4 is used for selecting the activation source (D7:4), which can be any combination of V0, V1, V2 and V3. A monitor input can be programmed to activate on either an under-voltage or over-voltage condition. The low-order four bits of configuration register 5 program these options. The reset threshold voltage range for V0 to V3 can be set for 5mV increments below 1.875V (low Range = "0") or for 15mV increments above 1.8V (high range = "1") using Bits D3:0. condition on V1. When this condition ceases, the RESET# output will remain active for tPRTO (programmable reset time-out). This reset time-out interval takes priority over the PUP outputs for use of the timer. The RESET# output will become active when triggered by a selected activation source such as an under-voltage Refer to Figures 2, 3 and 4 for a detailed illustration of the relationships among the affected signals. D7 MSB D6 D5 D4 X X X X D3 D2 D1 D0 LSB V3 V2 V1 V0 Action Voltage Threshold Range Select RESET Trigger Enable The RESET# output has two hardwired sources for activation: the MR# input, and the expiration of the Watchdog timer. RESET# will remain active so long as MR# is low, and will continue driving the RESET# output for tPRTO (programmable reset time out) after MR# returns high. The MR# input cannot be bypassed or disabled. 0 0 0 0 Low Range 1 1 1 1 High Range The status of the four supplies is available at any time over the I2C bus in the high order configuration bits of register 5 (Table 3). A "1" in a bit location indicates a fault on that supply. Table 2. Configuration Register 4 10 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Action D3 MSB D2 D1 D0 LSB V3 V2 V1 V0 D7 MSB 0 Read1 RTO1 RTO0 Only Writing a 0 enables undervoltage detection for the selected V input 0 Writing a 1 enables overvoltage detection for the selected V input 1 0 1 0 1 1 Table 3. Configuration Register 5 (D0 through D3) WATCHDOG TIMER The Watchdog Timer will generate a reset if it times out. It can be cleared by a high-to-low transition on WLDI and restarted. If the Watchdog times out RESET# will be driven low until tPRTO at which time it will return high. Refer to Figure 4 which illustrates the action of RESET# with respect to the Watchdog timer and the WLDI input. D6 D5 D4 LSB V3 V2 V1 V0 0 0 0 0 1 1 1 1 D5 D4 D3 Read Only Read Only Action 0 0 0 x x tPRTO = 25ms 0 0 1 x x tPRTO = 50ms 0 1 0 x x tPRTO = 100ms 0 1 1 x x tPRTO = 200ms Table 5. Configuration Register 6 (D3 through D7) Note 1 - Read Only bit D7 is set to a 0. Read only bits D4 and D3 are revision control and the value indicates the status code of the device (ie. 01 is status code 1). If WLDI is held low the timer will free-run generating a series of resets. D7 MSB D6 D2 D1 D0 LSB WD2 WD1 WD0 OFF 0 0 0 400ms 0 1 1 800ms 1 0 0 1600ms 1 0 1 3200ms 1 1 0 6400ms 1 1 1 Action Action Reading a 1 indicates a supply fault Table 6. Configuration Register 6 (D0, D1, D2) Table 4. Configuration Register 5 (D4 through D7) When the Watchdog times out RESET# will be generated. When RESET# returns high (after tPRTO) the timer is reset to time zero. Register 6 is also used to set the programmable reset timeout period (tPRTO) and to select the cascade option. The delay from VPTH0 until PUP#1 low is tPDLY1. There is a similar tPDLYX delay for V1 to PUP#2 and for V2 to PUP#3. They are programmed in register 7. Cascading will always occur as indicated in the flow chart (Figure 7). Cascade Delay Programming The cascade delays are programmed in register 7. Bit 7 of register 6 must be set to a 0 in order to enable the cascading of the PUP# outputs. Cascading will not commence until V0 is above its programmed threshold. Each PUP# (-3, -2 and -1) is delayed according to the states of its Bit 1 and Bit 0 as indicated in Table 9. Refer to Figures 1 and 5 for the detailed timing relationship of the programmable power-on cascading. SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 11 SMS47 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) D7 MSB D5 D6 D4 D3 PUP#3 Action Bit 1 Lock AS0 x x 0 x Config. Reg. Read/Write enabled 1 x Config. Reg. Read/Write locked out 1 Bit 0 D2 PUP#2 Bit 1 D0 LSB D1 PUP#1 Bit 0 Bit 1 Bit 0 2047 Table08 3.0 Table 8. Configuration Register 7 (D5 through D0) Note 1 - Setting this bit will cause a permanent Read/Write Lock out. Table 7. Configuration Register 7 (D7, D6) Bit 1 Bit 0 tPDLYX 0 0 0ms (no) Delay 0 1 25ms Delay 1 0 50ms Delay 1 1 100ms Delay 2047 Table09 1.0 Table 9. PUP Delays, Configuration Register 7 DEVELOPMENT HARDWARE & SOFTWARE SMX3200 PROGRAMMER The end user can use the summit SMX3200 programming cable and software that have been developed to operate with a standard personal computer. The programming cable interfaces directly between a PC’s parallel port and the target application. The application’s values are entered via an intuitive graphical user interface employing dropdown menus. The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMS47 via the programming Dongle and cable. An example of the connection interface is shown in Figure 8. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (www.summitmicro.com). Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. D1 Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL 1N4148 VDD_CAP SMS47 MR# SDA SCL 10 8 6 4 2 9 7 5 3 1 Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND C1 0.1µF GND Figure 8. SMX3200 Programmer I2C serial bus connections to program the SMS47. 12 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information I2C PROGRAMMING INFORMATION CONFIGURATION REGISTER OPERATION Input Data Protocol Data for the configuration registers is read and written via the I2C industry standard two-wire interface. The bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA) and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pullup resistor, located somewhere on the bus. See Operating Characteristics: Table 10 and Figure 9 below. The protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. The device controlling data transmission is called the Master and the controlled device is called the Slave. In all cases the SMS47 will be a Slave device, since it never initiates any data transfers. Symbol Parameter One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time because changes on the data line while SCL is high will be interpreted as start or stop condition. Conditions MIN TYP 0 MAX Units 100 kHz fSCL SCL clock frequency tLOW Clock low period 4.7 µs tHIGH Clock high period 4.0 µs tBUF Bus free time (1) 4.7 µs tSU:STA Star t condition setup time 4.7 µs tHD:STA Star t condition hold time 4.0 µs tSU:STO Stop condition setup time 4.7 µs tAA Clock edge to valid output SCL low to valid SDA (cycle n) 0.2 tDH Data Out hold time SCL low (cycle n+1) to SDA change 0.2 tR SCL and SDA rise time (1) 1000 ns tF SCL and SDA fall time (1) 300 ns tSU:DAT Data In setup time 250 ns tHD:DAT Data In hold time 0 ns TI Noise filter SCL and SDA tWR Write cycle time Before new transmission 3.5 µs µs Noise suppression 100 ns 5 ms Note (1): These values are guaranteed by design. Table 10. I2C Operating Characteristics tR tF tHIGH tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tBUF SDA In tAA tDH SDA Out 2047 Fig09 Figure 9. I2C Operating Characteristics SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 13 SMS47 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) START and STOP Conditions When both the data and clock lines are high the bus is said to be not busy. A high-to-low transition on the data line, while the clock is high, is defined as the Start condition. A low-to-high transition on the data line, while the clock is high, is defined as the Stop condition. See Figure 10. D7 MSB D6 D5 D4 D1 D0 LS B MSB R/W x x D2 Address Bits Device Type Bus SMS47 1 START Condition D3 0 0 x 1 x Configuration Register STOP Condition Table 11. Slave Addresses SCL 2047 Table11 1.0 Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to 1 a Read operation is selected; when set to 0 a Write operation is selected. SDA In 2047 Fig10 Figure 10. START and STOP Conditions WRITE OPERATIONS Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the Master or the Slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to Acknowledge that it received the eight bits of data. The Master will leave the SDA line high (NACK) when it terminates a read function. The SMS47 will respond with an Acknowledge after recognition of a Start condition and its slave address byte. If both the device and a write operation are selected the SMS47 will respond with an Acknowledge after the receipt of each subsequent 8-Bit word. In the READ mode the SMS47 transmits eight bits of data, then releases the SDA line, and monitors the line for an Acknowledge signal. If an Acknowledge is detected and no Stop condition is generated by the Master, the SMS47 will continue to transmit data. If a NACK is detected the SMS47 will terminate further data transmissions and await a Stop condition before returning to the standby power mode. Device Addressing Following a Start condition the Master must output the address of the Slave it is accessing. The most significant four bits of the Slave address are the device type identifier/address. For the SMS47 the default is 1001BIN. The next two bits are the Bus Address. The next bit (the 7th) is the MSB of the configuration register address. 14 The SMS47 uses byte Write operations. A byte Write operation writes a single byte during the nonvolatile write period (tWR). Byte Write After the Slave address is sent (to identify the Slave device and select either a Read or Write operation), a second byte is transmitted which contains the low order 8 bit address of any one of the 256 words in the array. Upon receipt of the word address the SMS47 responds with an Acknowledge. After receiving the next byte of data it again responds with an Acknowledge. The Master then terminates the transfer by generating a Stop condition, at which time the SMS47 begins the internal Write cycle. While the internal Write cycle is in progress the SMS47 inputs are disabled and the device will not respond to any requests from the Master. Acknowledge Polling When the SMS47 is performing an internal Write operation it will ignore any new Start conditions. Since the device will only return an acknowledge after it accepts the Start the part can be continuously queried until an acknowledge is issued, indicating that the internal Write cycle is complete. See the flow chart for the proper sequence of operations for polling. 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) READ OPERATIONS Write Cycle In Progress Read operations are initiated with the R/W bit of the identification field set to 1. There are two different Read options: 1. Current Address Byte Read, and 2. Random Address Byte Read. Issue Start Issue Stop Random Address Read Random address Read operations allow the Master to access any register location in a random fashion. This operation involves a two-step process. First, the Master issues a write command which includes the start condition and the Slave address field (with the R/W bit set to Write), followed by the address of the word it is to Read. This procedure sets the internal address counter of the SMS47 to the desired address. After the word address acknowledge is received by the Master it immediately reissues a Start condition, followed by another Slave address field with the R/W bit set to READ. The SMS47 will respond with an Acknowledge and then transmit the 8 data bits stored at the addressed location. At this point the Master sets the SDA line to NACK and generates a Stop condition. The SMS47 discontinues data transmission and reverts to its standby power mode. Issue Slave Address and R/W = 0 No ACK Returned Yes Next Operation a Write? No Yes Issue Stop Issue Address Proceed With Write Await Next Command Figure 12. Write Flow Chart Master S T A R T SDA 1 00 1 R B B A A X / W 2 1 Master SDA A C K Slave B B R A A X / 2 1 W A C K S T A A C R K T Reading the Configuration Register 1 00 1 D D D D D D D D 7 6 5 4 3 2 1 0 C C C C C C C C 7 6 5 4 3 2 1 0 A C K Slave S T A R T S T O P Writing Configuration Registers C C C C C C C C 7 6 5 4 3 2 1 0 N A S C T K O P 1 00 1 B B R A A X / 2 1 W D D D D D D D D 7 6 5 4 3 2 1 0 A C K A C K Figure 11. Read and Write Operations SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 15 SMS47 Preliminary Information APPLICATIONS MR# VDD_CAP VDD_CAP D6 DIODE J1 1 3 5 7 9 Gnd SCL Gnd3 SDA Rsrv 5 MR# +10V Rsrv 8 +5V Rsrv 10 2 4 6 8 10 R4 10K RESET# WLDI I2C SMX3200 C2 0.01uF C3 0.01uF C4 0.01uF 15 WLDI 1 11 RESET# R1 10K PUP#1 PUP#2 PUP#3 4 5 13 R2 10K R3 10K PUP#1 PUP#2 PUP#3 8 GND SM S47 12 C1 0.01uF MR# 9 10 V0 V1 V2 V3 VDD_CAP 16 2 3 14 V0 V1 V2 V3 SDA SCL A1 A2 U1 6 7 VDD_CAP VDD_CAP 0.1uF C5 Figure 13. Typical applications schematic, the SMX3200 programmer has internal SDA and SCL pull-up resistors. 16 2087 1.1 04/11/05 SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information DEFAULT CONFIGURATION REGISTER SETTINGS - SMS47GC-359 R eg ister C o n ten ts F u n ctio n R 00 56 V 0 thresho ld set to 3 .09 0V R 01 28 V 1 thresho ld set to 2 .40 0V R 02 A0 V 2 thresho ld set to 1 .40 0V R 03 14 V 3 thresho ld set to 0 .70 0V R 04 F3 R eset T rigger source set for all ch an nels, V 0, V 1 set to hig h ran ge and V 2, V 3 set to lo w ra nge R 05 X0 U pper b its are vola tile statu s ind ication of input supp ly conditio n. V 0, V 1, V 2 and V 3 set to m onitor U V U nder V oltag e. R 06 4D R eset tim eout set to 100m s, W atchdog T im er set to 1.6s. B its D 4 and D 3 ind icate revisio n contro l. R 07 6A C onfigura tio n reg isters are unlock ed, cascading de la ys are a ll 50m s The default device ordering number is SMS47GC-359, is programmed as described above and tested over the commercial temperature range. SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 17 SMS47 Preliminary Information PACKAGE 16 PIN SSOP PACKAGE 0.189 - 0.197 (4.80 - 5.00) Ref. JEDEC MO-137 0.228 - 0.244 (5.79 - 6.20) Pin 1 Inches (Millimeters) 0.150 - 0.157 (3.81 - 3.99) 0.053 - 0.069 (1.35 - 1.75) 0.059 MAX (1.50) 0.007 - 0.010 (0.18 - 0.25) 0” Min to 8” Max 0.016 - 0.050 (0.41 - 1.27) 18 2087 1.1 04/11/05 0.025 0.008 - 0.012 (0.635) (0.20 - 0.31) 0.004 - 0.010 (0.10 - 0.25) 16 Pin SSOP SUMMIT MICROELECTRONICS, Inc. SMS47 Preliminary Information PART MARKING SUMMIT SMS47G Summit Part Number Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) xx Annn AYYWW Pin 1 Identifier Date Code (YYWW) Lot tracking code (Summit use) Part Number suffix (Contains Customer specific ordering requirements) Drawing not to scale Product Tracking Code (Summit use) ORDERING INFORMATION SM S47 G S u m m it P a r t Num ber Package G =16 Lead SSO P C nnn P a r t N u m b e r S u ffix (s e e p a g e 1 7 ) S p e c if ic r e q u ir e m e n t s a r e c o n t a in e d in t h e s u f f ix s u c h a s H e x c o d e , H e x c o d e r e v is io n , e t c . Tem p Range C = C o m m e r c ia l B la n k = I n d u s t r ia l NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 1.1 - This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site at www.summitmicro.com for data sheet updates. © Copyright 2005 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE ANALOG FOR A DIGITAL WORLD™ I2C is a trademark of Philips Corporation. SUMMIT MICROELECTRONICS, Inc. 2087 1.0 04/11/05 19