LITEON AP3216C

LSC
L
SC 敦 南 科 技
AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Features
Descriptions
2
The AP3216C is an integrated ALS & PS module
I C interface (up to 400k Hz, contact factory for
3.4M Hz)
proximity sensor [PS], and an IR LED in a single
Mode Select: ALS, PS+IR, ALS+PS+IR, PD,
package.
ALS once, SW Reset, PS+IR once and
ALS+PS+IR once.
廖
R
that includes a digital ambient light sensor [ALS], a
Built-in temperature compensation circuit
linear
Wide operating temperature range (-30°C to
365/1460/5840/23360
a
and
dynamic
is
well
range
suited
to
+80°C)
51
8
over
Ambient Light Photo Sensor
applications under clear glass or darkened glass.
y
response
19
，
This device provides a multiple gain function with
16-bit effective linear output (0~65535)
4 user selectable dynamic range
towards near field application and detects external
Anti-flicker rejection (reject 50/60Hz)
output, this device is designed specially to fix low
High sensitivity @ darkened glass
Window loss compensation
QQ
:
multiple IR LED current control and 10-bit ADC
ar
registers. With multiple proximity gain control,
Proximity Detector
10 bit effective linear output (0~1023)
58
5
object with simple configurable zone controlled by
71
44
The proximity function is targeted specifically
4 programmable IR LED current output
in
reflection objects, such as black hair.
the
occurrence
of
false
triggering.
34
1
Form factor 4.1mm x 2.4 mm x 1.35 mm
18
minimize
Cross talk compensation
66
4
system efficiency and several features that help to
High ambient light suppression
The device supports an interrupt feature to improve
RoHS compliant
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im
Through internal calibration and CMOS design, the
l:
AP3216C is designed to minimize device-to-device
Mobile phone, Pad
Personal Navigation Device
Notebook/Ultrabook
LCD/PDP TV backlight systems
Digital Photo Frame
Applications with Capacitive Touch Panel
技
有
限
公
司
，
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variations for ease of manufacturability.
Applications
Pr
讯
科
Ordering Information
Packing Type
Package
Quantity
AP3216C
Tape and Reel (MSL3)
8Ld Chipled
4.1 x 2.4 x 1.35mm
1,000
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合
Part No.
Please be aware that an Important Notice concerning availability, disclaimers, and use in critical
applications of LSC products is at the end of this document.
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Function Block Diagram
INT
LDR
LEDC
廖
R
SDA
SCL
51
8
y
71
44
GND
LEDA
66
4
34
1
in
VDD
58
5
IREF FOSC
QQ
:
Timming_ctl
IR_LED
ar
PS
I2C
Interface
IRDR
Control logic
ALS/PS
ADC
19
，
Upper / lower
Threshold
ALS
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合
Pr
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技
有
限
公
司
，
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l:
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im
18
Typical Application Circuit
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Recommended Application Circuit Components
Recommended Value
Condition / Range
Depends on system design, connect to VDD or VBatt
Rp1, Rp2
Depends on system design(*1)
廖
R
VLED
Depends on system design
C1
0.1uF, ±20%
C2
2.2 uF, ±20%
1~4.7 uF
C3
1 uF, ±20%
Optional
y
51
8
Rp3
19
，
Component
71
44
*Note 1: I2C Pull up resistor for standard protocol format. For the complete description of maximum pull up resistor and minimum pull up
Pin Name
1
VDD
O
I2C serial clock signal (open drain)
GND
Ground
LEDA
LED anode
LEDC
LED cathode
I
LDR
7
O
INT
8
I/O
l:
6
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im
5
SCL
34
1
3
I
Digital/Analog Power Supply
in
I
4
Description
66
4
2
QQ
:
I/O Type
18
Pin Number
58
5
Pin Descriptions
ar
resistor, please refer to: http://www.semiconductors.philips.com.
Interrupt pin
I2C serial data signal (open drain)
司
，
SDA
LED driver for proximity emitter
Symbol
Value
Unit
VDD
4.5
V
Supply Voltage 2
VLED
4.5
V
I2C Bus Pin Voltage
SCL, SDA
-0.2 to 4.5
V
SCL, SDA
10
mA
Tope
-40 to +85
℃
Tstg
-40 to +100
℃
Pr
讯
科
技
有
Supply Voltage 1
限
Parameter
公
Absolute Maximum Ratings*
2
合
I C Bus Pin Current
市
金
Operating Temperature
Storage Temperature
out of the specified terminal.
深
圳
*Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to ground. Currents are positive into, negative
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Recommended Operation Conditions
Max.
Unit
Condition
VBus≦VDD
VDD
2.4
3.6
I2C Bus Pin Voltage Note2
VBus
1.7
VDD
V
V
Operating Temperature
Tope
-30
80
℃
I2C Bus Input High Voltage Note3
VIH_SCL,
VIH_SDA
1.4
I2C Bus Input Low Voltage Note3
VIL_SCL,
VIL_SDA
SDA Output Low Voltage
VOL_SDA
0.5
0
0.4
0
0.6
0
0.4
19
，
V
y
VOL_INT
V
V
3mA sinking current
V
6mA sinking current
V
3mA sinking current
QQ
:
INT Output Low Voltage
廖
R
Typ.
51
8
Min.
ar
Supply Voltage
Symbol
Note1
71
44
Description
34
1
66
4
If VDD and VBUS are supplied by different power source, please ensure the power sequence to avoid the
reverse-voltage issue due to ESD protective diode.
Pr
讯
科
技
有
限
公
司
，
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18
2.
in
58
5
Notes:
1. Considering VDD rising time, please make sure a VDD slew rate at least 0.6V/ms. When the supply voltage drops
out 10% of the recommended operation voltage range, please consider the low voltage detector that it is built-in IC
internal to be brown out reset protection. When the VDD drops below 1.4V under room temp, the POR would be
triggered and system will be reset. Then power of the chip will be recovered at the requirement slew rate, and write
registers to the desired values.
The specs are defined under VDD=2.8V, T=25°C
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合
3.
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Electrical & Optical Specifications
Parameter
Symbol
Active Supply Current
Note1
, white light LED, unless otherwise noted.
MIN
Idd
Shutdown Current
TYP
MAX
160
Ipd
Notes
UNIT
Ev=0
uA
2
2
Ev=0, I C inactive
uA
0.36 lux/count (Default)
Range 2
5840
0.089 lux/count
Range 3
1460
0.022 lux/count
Range 4
365
Range 1
360
Range 3
Range 4
51
8
y
71
44
Ev=128lux
lux
count
1438
Ev=128lux
count
5750
Ev=128lux
count
23000
Ev=128lux
count
Ev=0, Range 4
count
5
Proximity Sensor
1.3
ms
IF=20mA
V
850
IF=20mA
nm
40
IF=20mA
nm
1.45
LED Spectral Bandwidth
∆λ
l:
λp
160
司
，
Te
LED Peak Wavelength
Active Supply Current @ LED
Pulse on Note2
限
公
PS Sensing Full Scale ADC
Count (delta value)
IR sensing Full Scale ADC Count
uA
1023
count
1023
count
100
16.7
%
33.3
%
66.7
%
Pr
Detection distance
讯
科
技
有
1.6
18
VF
16bit ADC count
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im
LED Forward Voltage
34
1
100
66
4
Conversion Time
合
LED Driver Current
市
金
100% = 110mA @ Typ.
圳
lux
0.0056 lux/count
in
Dark Count
深
lux
QQ
:
Range 2
(@ ambient light)
lux
ar
ALS ADC Count
23360
58
5
Dynamic Range
Range 1
19
，
Ambient Light Sensor
廖
R
All specifications are at VDD=2.8V, Tope=25
100
Test condition : TBD
Default
mm
%
Notes:
1. The current consumption is tested under 0x10=0x00, 0x20=0x7c, 0x21=0x12, 0x23=0x00, 0x24=0x07 respectively,
excluding LED current.
2.
The current consumption is tested under 0x20=0x7c, 0x21=0x12, 0x23=0x00, 0x24=0x07 respectively, excluding
LED current.
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Typical Performance Charts
Active Current (IDD) v.s VDD
200
180
160
180
160
100
80
60
40
20
140
廖
R
140
120
120
100
19
，
Active Current (uA)
80
60
20
0
-5
5
15 25 35
Temp. (C)
45
55
65
75
85
2.2
2.4
2.8
3
VDD (V)
3.2
3.4
3.6
3.8
Fig.2 Active Current vs VDD
QQ
:
ALS Output Code Ratio vs Temp. (VDD=2.8V / 64Lux)
ALS Output Code Ratio vs VDD (Temp=25C / 64Lux)
1.2
1.15
58
5
1.1
in
Ratio
1.05
34
1
1
0.95
66
4
0.9
0.85
0.8
-5
5
15 25 35
Temp. (C)
45
55
65
75
85
2.2
l:
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im
-45 -35 -25 -15
18
Ratio
2.6
ar
Fig.1 Active Current vs Temp
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
y
0
-45 -35 -25 -15
51
8
40
71
44
Active Current (uA)
Active Current (IDD) v.s Temp
200
2.6
2.8
3
3.2
VDD (V)
3.4
3.6
3.8
Fig.4 ALS Output Code Ratio vs VDD
Fig.5 Angular Response of ALS
Fig.6 Angular Response of PS
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，
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Fig.3 ALS Output Code Ratio vs Temp
2.4
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
Fig.8 LED Emitting Angle
QQ
:
Definition of timing for I2C devices
ar
71
44
y
Fig.7 Spectrum Response
51
8
19
，
廖
R
LITE-ON SEMICONDUCTOR CORP.
This section will describe the main protocol of the I2C bus. For more details and timing diagrams, please refer to
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im
18
66
4
34
1
in
58
5
the I2C specification.
，
The device can operate at the standard mode I2C bus line or the fast mode I2C bus line. The characteristics of the
深
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合
Pr
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技
有
限
公
司
I2C bus for difference modes are as bellow.
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Characteristics of the SDA and SCL bus lines for I2C bus devices
Fast mode
Symbol
Min
Max
Unit
f SCL
1
400
kHz
Bus free time between a STOP and START
condition
t BUF
1.3
--
us
0.6
---
HIGH period of the SCL clock
t HIGH
0.6
Set-up time for a repeated START condition
t SU ;STA
0.6
Set-up time for STOP condition
t SU ; STO
tf
Pulse width of spikes which must be
suppressed by the input filter
--
us
ns
300
ns
50
--
ns
100
--
ns
0
50
ns
Te
l:
el
im
t SP
Note1: Cb (capacitance of one bus line) = 10~400(pF)
us
300
34
1
18
66
4
tSU;DAT
Data setup time
--
us
20 + 0.1Cb
(note1)
20 + 0.1Cb
(note1)
t HD;DAT
Data hold time
us
--
in
Fall time of both SDA and SCL signals
tr
0.6
58
5
Rise time of both SDA and SCL signals
51
8
1.3
y
t LOW
ar
LOW period of the SCL clock
us
71
44
t HD ;STA
QQ
:
Hold time (repeated) START condition. After
this period, the first clock pulse is generated
19
，
SCL clock frequency
，
(*) Specified by design and characterization; not production tested.
技
有
限
公
司
℃, unless otherwise noted.
(**) All specifications are at VBus = 3.3V, Tope=25℃
I2C Protocols
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合
Pr
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．I2C Write Protocol (type 1):
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Parameter (*)
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
2
QQ
:
ar
71
44
y
51
8
19
，
廖
R
．I C Write Protocol (type 2):
技
有
限
公
司
，
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l:
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im
18
66
4
34
1
in
58
5
I2C Read Protocol:
深
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合
Pr
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．I2C Read (Combined format) Protocol:
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
Start condition
P
Stop condition
W
Write (0 for writing)
Non-Acknowledge(1 for an NACK)
Sr
Repeated Start condition
Read (1 for read)
34
1
R
Master-to-Slave
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im
18
66
4
Slave-to-master
QQ
:
S
N
58
5
Acknowledge (0 for an ACK)
in
A
ar
71
44
y
51
8
19
，
廖
R
LITE-ON SEMICONDUCTOR CORP.
A read/write bit should be appended to the slave address by the master device to
Te
The slave addresses have 7 bits.
l:
I2C Slave Address
深
圳
市
金
合
Pr
讯
科
技
有
限
公
司
，
properly communicate with the device. The slave address of this device is 0x1E.
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AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
Register Table List
System Register Table
REGISTER NAME
DESCRIPTION
0x00
System Configuration
Control of basic functions
0x01
Interrupt Status
ALS and PS interrupt status output
0x02
INT Clear Manner
Auto/semi clear INT pin selector
0x0A
IR Data Low
Lower byte for IR ADC channel output
0x0B
IR Data High
Higher byte for IR ADC channel output
0x0C
ALS Data Low
Lower byte for ALS ADC channel output
0x0D
ALS Data High
Higher byte for ALS ADC channel output
0x0E
PS Data Low
Lower byte for PS ADC channel output
0x0F
PS Data High
Higher byte for PS ADC channel output
QQ
:
ar
71
44
y
51
8
19
，
廖
R
ADDR (HEX)
58
5
ALS Register Table
REGISTER NAME
DESCRIPTION
0x10
ALS Configuration
0x19
ALS Calibration
0x1A
ALS Low Threshold(7:0)
0x1B
ALS Low Threshold (15:8)
0x1C
ALS High Threshold (7:0)
0x1D
ALS High Threshold(15:8)
34
1
in
ADDR (HEX)
66
4
Control of gain, conversion time of persist for ALS
ALS window loss calibration
18
Lower byte of ALS low threshold
Te
0x20
PS Configuration
技
有
PS INT Form
Interrupt algorithms style select of PS
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Control of LED pulses number and driver current
PS average time selector
PS LED Waiting Time
Control PS LED waiting time
0x28
PS Calibration L
Offset value to eliminate cross talk
0x29
PS Calibration H
Offset value to eliminate cross talk
0x2A
PS Low Threshold (2:0)
Lower byte of PS low threshold
0x2B
PS Low Threshold (10:3)
Higher byte of PS low threshold
0x2C
PS High Threshold (2:0)
Lower byte of PS high threshold
0x2D
PS High Threshold (10:3)
Higher byte of PS high threshold
合
市
金
圳
Control of gain, integrated time and persist for PS
PS Mean Time
0x24
深
DESCRIPTION
PS LED Driver
Pr
0x23
Higher byte of ALS high threshold
，
公
REGISTER NAME
限
ADDR (HEX)
0x21
Lower byte of ALS high threshold
司
PS Register Table
0x22
l:
el
im
Higher byte of ALS low threshold
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3-in-1 Digital ALS + PS + IRLED Module
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System Register Descriptions
REGISTER
COMMAND
System Mode
(Default : 000)
Bits
FUNCTIONS/DESCRIPTION
System Configuration
(Default : 0x00)
2:0
INT Status
1
PS Int (Read only)
(Default : 0)
0
ALS Int (Read only)
(Default : 0)
Clear Manner
(Default : 0)
000: Power down (Default)
001: ALS function active
010: PS+IR function active
011: ALS and PS+IR functions active
100: SW reset
101: ALS function once
110: PS+IR function once
111: ALS and PS+IR functions once
0: Interrupt is cleared or not triggered yet
1: Interrupt is triggered
Note1
0: Interrupt is cleared or not triggered yet
1: Interrupt is triggered
Note1
0: INT is automatically cleared by reading
data registers
1: Software clear after writing 1 into
address 0x01 each bit
0: Valid IR and PS data
1: Invalid IR and PS data
廖
R
REGISTER NAME
IR Data High
IR overflow
(Read only)
1:0
(Read only)
7:0
(Read only)
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0x0B
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71
44
QQ
:
7
ar
IR Data Low
58
5
0x0A
34
1
0
in
INT Clear Manner
66
4
0x02
18
0x01
51
8
19
，
ADDR
(Hex)
0x00
IR lower byte of ADC output
IR higher byte of ADC output
ALS Data Low
7:0
(Read only)
ALS lower byte of ADC output
0x0D
ALS Data High
7:0
0x0E
PS Data Low
7
l:
0x0C
ALS higher byte of ADC output
Object detect
(Read only)
0: The object leaving
1: The object closed
6
IR overflow
(Read only)
0: Valid IR, PS data and object detected
1: Invalid IR, PS data and object detected
3:0
(Read only)
PS lower byte of ADC output
7
Object detect
(Read only)
0: The object leaving
1: The object closed
6
IR overflow
(Read only)
(Read only)
0: Valid IR, PS data and object detected
1: Invalid IR, PS data and object detected
PS higher byte of ADC output
PS Data High
5:0
合
Pr
讯
科
技
有
0x0F
限
公
司
，
Te
(Read only)
User can clear INT bit and individual status bits when reading the register 0xD(ALS) , 0xF(PS) and
0xD+0xF(ALS+PS) respectively.
深
圳
市
金
Note1. The INT pin will be set low and set INT status bit when ALS or PS or (ALS+PS) interrupt event occurrence.
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3-in-1 Digital ALS + PS + IRLED Module
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System Configuration Register
System Configuration (Default = 0x00)
BIT
B7
R/W
Reserved
B6
B5
B4
B3
B2
B1
B0
廖
R
0x00
19
，
System Mode
The SYSTEM CONFIGURATION register is used to power up/down the device and to select the ALS and/or PS
y
Description
000: Power down (Default)
001: ALS function active
010: PS+IR function active
011: ALS and PS+IR functions active
100: SW reset
101: ALS function once
110: PS+IR function once
111: ALS and PS+IR functions once
71
44
BITS
2:0
34
1
in
58
5
QQ
:
ar
Field
System mode
51
8
feature of the device.
66
4
For power down (000)
18
The device will stop operation. The register will keep previous settings although the device sleeps. The ALS, PS
l:
el
im
and IR will be cleared.
Te
For ALS function active (001)
，
The device will operate only for ALS function. The typical conversion time of ALS is 100ms. The PS data will not
Pr
讯
科
技
有
限
公
司
work at this mode. The operation time is showed as below :
For PS+IR function active (010)
市
金
合
The device will operate only for PS+IR function. The typical conversion time of IR is 12.5ms, and the PS is
decided by the PS waiting time. The ALS data will not work at this mode. The operation time is showed as below (PS
深
圳
waiting time = 0):
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3-in-1 Digital ALS + PS + IRLED Module
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For ALS and PS+IR functions active (011)
The device will operate the ALS and PS+IR function alternately. The conversion time will be double at this mode.
19
，
廖
R
The operation time is showed as below (PS waiting time = 0) :
51
8
The conversion time of difference modes are listed as below.
71
44
y
Conversion Time (Typical Value)
System Mode
ALS
PS
IR
ALS
100ms
~
PS+IR
~
( PS wait time + 1 ) * 12.5ms
12.5ms
ALS+PS+IR
112.5ms
( PS wait time + 1 ) * 112.5ms
112.5ms
58
5
QQ
:
ar
~
34
1
in
For SW reset (100)
When the host writes this setting, the all registers of device will become the default value after 10ms. Please don’t
Te
l:
el
im
18
66
4
force command during these period of 10ms to avoid abnormal operation
，
For ALS function once (101)
司
When the host writes this setting, the device will work at ALS mode in a short time. Then the device will become
公
power down automatically after the device gets the ALS data. This time is typically 2.5 conversion time. If the device is
市
金
合
Pr
讯
科
技
有
限
slept by the ALS once command, the ALS data will be kept and not cleared.
深
圳
For PS+IR function once (110)
When the host writes this setting, the device will work at PS mode in a short time. Then the device will become
power down automatically after the device gets the PS and IR data. This time is typically 2.5 conversion time and is not
affected by the PS waiting. If the device is slept by the PS once command, the PS and IR data will be kept and not
cleared.
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For ALS and PS + IR function once (111)
51
8
When the host writes this setting, the device will operate the ALS and PS+IR function alternately in a short time.
71
44
y
Then the device will become power down automatically after the device gets the ALS, PS and IR data. This time is
typically 232ms and is not affected by the PS waiting. If the device is slept by this once command, the ALS, PS and IR
66
4
34
1
in
58
5
QQ
:
ar
data will be kept and not cleared.
el
im
18
INT Status Register
ALS and PS Interrupt Status Register (Default = 0x00)
BIT
B7
W/R
Reserved
B5
B4
B3
B2
B1
B0
PS INT
ALS INT
，
Te
B6
l:
0x01
司
The ALS INT bit register is used to indicate the ALS interrupt be triggered (set to 1) or not (set to 0). It will be
公
cleared after 0x0D register be read or write 0x01 to clear (depend on INT Clear Manner flag).
限
The PS INT bit register is used to indicate the PS interrupt be triggered (set to 1) or not (set to 0). It will be cleared
技
有
after 0x0F register be read or write 0x02 to clear (depend on INT Clear Manner flag).
Pr
讯
科
INT Clear Manner Register
市
金
BIT
合
0x02
深
圳
W/R
INT Clear Manner Register (Default = 0x00)
B7
B6
B5
B4
B3
B2
B1
Reserved
B0
CLR_MNR
In order to provide the multiple control flow with interrupt flag handling, The CLR_MNR bit used to assign two
manners of interrupt status flag de-asserted. It is set to 0, the interrupt flag be automatic cleared by reading data
registers (0x0C, 0x0D, 0x0E, 0x0F). On the other hand, the interrupt flag is cleared by write 1. For example, if PS_INT
asserted, it can be cleared after I2C write address 0x01 with 0x02.
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IR Data Register
IR Data Low
BIT
B7
B6
W/R
IR_OF
Reserved
0x0B
IR Data High
BIT
B7
RO
IR Data High
B5
B4
B3
B2
B1
B0
廖
R
0x0A
B4
B3
B2
B1
B0
y
B5
71
44
B6
51
8
19
，
IR Data Low
QQ
:
ar
The ADC channel data for IR is expressed as 10-bit data spreading across two registers, IR Data Low and ID Data
High. These two will provide the lower and higher bytes of the ADC value respectively. The IR DATA can show the
intensity of environment IR. All channel data registers are read-only.
58
5
If the IR is high intensity, it will affect the PS data and cause the PS data invalid. There is an overflow flag (IR_OF)
34
1
in
to indicate the PS data to see if it is valid or not in high IR light. If the IR_OF is set to 1, the device will force the PS
66
4
object status as away state..
The higher byte registers can be read after reading the lower byte register. When the lower byte register is read, the
18
higher byte is stored in a temporary register, which is read by a subsequent read to the higher byte. The higher byte
el
im
register will read the correct value even if additional integration cycles end between the reading of the lower and higher
Te
l:
byte data registers.
ALS Data Low
BIT
B7
RO
ALS Data Low
合
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金
BIT
圳
深
B4
B3
B2
B1
B0
B5
B4
B3
B2
B1
B0
讯
科
Pr
0x0D
RO
B5
技
有
限
B6
公
0x0C
司
，
ALS Data Register
ALS Data High
B7
B6
ALS Data High
The ADC channel data for ALS is expressed as 16-bit data spread across two registers, ALS Data Low and ALS
Data High. These two will provide the lower and higher bytes of the ADC value respectively.
All channel data
registers are read-only.
The higher byte registers can be read after reading the lower byte register. When the lower byte register is read, the
higher byte is stored in a temporary register, which is read by a subsequent read to the higher byte. The higher byte
register will read the correct value even if additional integration cycles end between the reading of the lower and higher
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byte data registers.
PS Data Low
BIT
B7
B6
B5
B4
B3
RO
OBJ
IR_OF
Reserved
Reserved
PS Data Low
0x0F
PS Data High
BIT
B7
B6
B5
B4
B3
RO
OBJ
IR_OF
PS Data High
B1
B0
71
44
y
51
8
B2
19
，
0x0E
廖
R
PS Data Register
B1
B0
QQ
:
ar
B2
The ADC channel data for PS is expressed as 10-bit data spread across two registers, PS Data Low and PS Data
58
5
High. These two will provide the lower and higher bytes of the ADC value respectively.
34
1
in
The PS object status (OBJ) bit shows the position of object. When object is away from sensor and the count of PS
66
4
across the threshold of PS, the OBJ bit will be reset to 0. On other way, the object is near the sensor and OBJ bit set to 1
to indicate object closed.
18
The IR overflow flag (IR_OF) indicates the PS data valid or not. If this bit is set to 1, it indicates that the data of
el
im
PS is invalid in high intensive IR light. Please refer to description of IR data register.
l:
The higher byte registers can be read after reading the corresponding lower byte register. When the lower byte
Te
register is read, the higher byte is stored in a temporary register, which is read by a subsequent read to the higher byte.
，
The higher byte register will read the correct value even if additional integration cycles end between the reading of the
深
圳
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合
Pr
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技
有
限
公
司
lower and higher byte data registers. All channel data registers are read-only.
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ALS Register Descriptions
Bit
ALS Configuration
(Default : 0x00)
5:4
REGISTER
COMMAND
ALS dynamic range
(Default : 00)
ALS persist
(Interrupt filter)
(Default : 0000)
00: 23360 lux / Resolution bit (Default)
01: 5840 lux / Resolution bit
10: 1460 lux / Resolution bit
11: 365 lux / Resolution bit
ALS interrupt is triggered after N
conversion time
0000: 1 conversion time (Default)
0001: 4 conversion time
0010: 8 conversion time
0011: 12 conversion time
0100: 16 conversion time
……
1111: 60 conversion time
0x00: calibration factor = 0/64
……
0x40: calibration factor = 64/64
……
0xFF: calibration factor = 255/64
0x1A
ALS Low Threshold L
(Default : 0x00)
7:0
0x1B
ALS Low Threshold H
(Default : 0x00)
7:0
ALS window loss
calibration
(Default : 0x40)
18
66
4
34
1
Lower byte of low interrupt threshold for
ALS
el
im
ALS High Threshold L
(Default : 0xFF)
7:0
0x1D
ALS High Threshold H
(Default : 0xFF)
7:0
Lower byte of high interrupt threshold for
ALS
Higher byte of high interrupt threshold for
ALS
公
限
ALS Configuration (Default = 0x00)
BIT
B7
技
有
0x10
讯
科
B6
Pr
Reserved
B5
B4
B3
ALS Gain
B2
B1
B0
ALS Interrupt Filter
合
R/W
Higher byte of low interrupt threshold for
ALS
司
，
Te
l:
0x1C
ALS Configuration Register
QQ
:
7:0
58
5
ALS Calibration
(Default : 0x40)
in
0x19
ar
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44
y
51
8
3:0
FUNCTIONS/DESCRIPTION
廖
R
REGISTER NAME
19
，
ADDR
(Hex)
0x10
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The ALS Configuration register is used to set ALS gain and ALS interrupt filter (persist).
深
圳
1.
ALS Gain (Ambient light detectable range). There are 4 ranges below for AP3216C.
A.
Range 1 (B5B4=’00’): 0 ~ 23360 Lux. Resolution = 0.36 lux/count.
B.
Range 2 (B5B4=’01’): 0 ~ 5840 Lux. Resolution = 0.089 lux/count.
C.
Range 3 (B5B4=’10’): 0 ~ 1460 Lux. Resolution = 0.022 lux/count.
D.
Range 4 (B5B4=’11’): 0 ~ 365 Lux. Resolution = 0.0056 lux/count
ALS ADC data to Lux conversion formula as below
Ambient Light (lux) = 16 bit ALS ADC data * Resolution
2.
ALS Interrupt Filter: Configurable interrupt filtering is to provide hardware interrupt to be generated after
interrupts trigger for N consecutive numbers of conversion time. The ALS interrupt filter bits determine N.
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2.
B3B2B1B0=’0001’, N = 4
3.
B3B2B1B0=’0010’, N = 8
4.
B3B2B1B0=’0011’, N = 12
5.
B3B2B1B0=’0100’, N = 16
6.
B3B2B1B0=’1111’, N = 60
19
，
B3B2B1B0=’0000’, N = 1
51
8
1.
廖
R
There are 4 bits settings could be selected, for example :
B7
R/W
ALS Calibration
B5
B4
B3
B2
B1
B0
58
5
B6
71
44
BIT
QQ
:
ALS Calibration (Default = 0x40)
ar
0x19
y
ALS Calibration Register
in
To compensate ALS window loss induced from assembly, the device provide a parameter port to setup a value to
34
1
eliminate the difference between each component. It is a floating point number with effective range from 0 ~3.98. The
66
4
8bits register presents 00.000000(0.00) ~11.111111 (3.98) and it’s resolution is 1/64. If it is wrote by 0x50 then it is
equivalent to 1.25 (80* 1/64).
el
im
18
For example :
Original ALS data (component level) = 1000 counts
2.
After assembly ALS data = 800 counts
3.
Window loss should be compensated = 1000/800=1.25
4.
The register should be set to 0x50 (80*1/64=1.25)
公
司
，
Te
l:
1.
技
有
限
ALS ADC Low Threshold Register (Read/Write)
0x1A
ALS Low Threshold Lower Byte (Default = 0x00)
BIT
B7
B5
B4
B3
B2
B1
B0
B3
B2
B1
B0
Pr
讯
科
B6
ALS Low Threshold Lower byte
深
圳
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金
合
R/W
0x1B
ALS Low Threshold Higher Byte (Default = 0x00)
BIT
B7
R/W
ALS Low Threshold Higher byte
B6
B5
B4
The ALS Low Threshold registers store the values of the low threshold data. An interrupt is triggered when ALS
ADC (Registers 0CH & 0DH) < ALS ADC Low Threshold.
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ALS ADC High Threshold Register (Read/Write)
0x1C
ALS High Threshold Lower Byte (Default = 0xFF)
BIT
B7
R/W
ALS High Threshold Lower byte
0x1D
ALS High Threshold Higher Byte (Default = 0xFF)
BIT
B7
R/W
ALS High Threshold Higher byte
B4
B3
B2
B1
B0
廖
R
B5
y
B4
B3
71
44
B5
B2
B1
B0
QQ
:
ar
B6
51
8
19
，
B6
The ALS High Threshold registers store the values of the high threshold data. An interrupt is triggered when ALS
58
5
ADC (Registers 0CH and 0DH) > ALS ADC High Threshold.
PS Configuration
(Default : 0x05)
7:4
REGISTER
COMMAND
PS / IR Integrated
time select
(Default : 0000)
34
1
Bit
66
4
REGISTER NAME
el
im
18
ADDR
(Hex)
0x20
in
PS Register Descriptions
PS gain
(Default : 01)
，
Te
l:
3:2
PS persist
(Interrupt filter)
(Default : 01)
5:4
LED pulse
(Default : 01)
1:0
LED driver ratio
Typ. 100% = 110mA
(Default : 11)
技
有
限
公
司
1:0
PS LED Control
(Default : 0x13)
0x22
PS INT Mode
(Default : 0x01)
0
0x23
PS mean time
(Default : 0x00)
1:0
0x24
PS LED Waiting
(Default : 0x00)
5:0
深
圳
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金
合
Pr
讯
科
0x21
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PS_Algo
(Default : 1)
Edit PS mean time
(Default : 00)
PS LED waiting
(Default : 0x00)
20/31
FUNCTIONS/DESCRIPTION
0000: 1T (Default)
0001: 2T
……
1111: 16T
00: 1
01: 2 (Default)
10: 4
11: 8
PS interrupt is triggered after N conversion
time
00: 1 conversion time
01: 2 conversion time (Default)
10: 4 conversion time
11: 8 conversion time
00: 0 pulse
01: 1 pulse (Default)
10: 2 pulses
11: 3 pulses
00: 16.7%
01: 33.3%
10: 66.7%
11: 100% (Default)
0: PS INT Mode 1 (Zone type)
1: PS INT Mode 2 (Hysteresis type, default)
00 : mean time=12.5ms (Default)
01 : mean time=25ms
10 : mean time=37.5ms
11 : mean time=50ms
0x0 : 0, no waiting (Default)
0x1 : 1 mean time
0x2 : 2 mean times
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……
0x3F : 63 mean times
PS Calibration L
(Default : 0x00)
0
PS calibration
Lower byte of PS calibration
0x29
PS Calibration H
(Default : 0x00)
7:0
PS calibration
Higher byte of PS calibration
0x2A
PS Low Threshold L
(Default :0x00)
1:0
Lower byte of low interrupt threshold for
PS
0x2B
PS Low Threshold H
(Default :0x80)
7:0
Higher byte of low interrupt threshold for
PS
0x2C
PS High Threshold L
(Default :0x00)
1:0
Lower byte of high interrupt threshold for
PS
0x2D
PS High Threshold H
(Default :0x80)
7:0
19
，
51
8
y
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44
QQ
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ar
0x20
PS Configuration (Default = 0x05)
BIT
B7
B5
B4
B3
l:
el
im
B6
66
4
34
1
in
58
5
Higher byte of high interrupt threshold for
PS
18
PS Configuration Register
PS/IR Integration time
PS Gain
B2
B1
B0
PS Interrupt Filter
Te
R/W
廖
R
0x28
，
The PS Configuration register is used to set PS integration time, PS gain, LED waiting time and PS interrupt filter.
司
The PS integration time sets ADC’s sample/conversion time and it will affect both resolution and sensitivity. Longer
公
integration time increases IR ADC&PS ADC resolution and sensitivity.
PS ADC and IR ADC resolution
0000 (1T) (Default)
X1
0001 (2T)
X2
讯
科
技
有
限
PS integration time (bits 7:4)
X15
1111 (16T)
X16
市
金
合
Pr
1110 (15T)
深
圳
The PS gain setting can be used to increase/decrease the OBJ’s detection distance. Higher gain can increase
detection distance but also increase noise or cross talk signal. The IR ADC will not be affected.
PS gain (bits 3:2)
PS resolution
00
X1
01 (Default)
X2
10
X4
11
X8
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The PS interrupt filter prevents the interrupt triggered by noises. The interrupt is triggered when the PS object
status has changed and keeps the change for M consecutive number of conversion time. The PS interrupt filter bits
Number of “M” conversion time
00
1
01 (Default)
2
10
4
11
8
BIT
B7
R/W
Reserved
B5
B4
51
8
y
71
44
B3
B2
B1
in
B6
QQ
:
PS LED Control (Default = 0x13)
58
5
0x21
ar
PS LED Control Register
19
，
PS interrupt filter (bits 1:0)
廖
R
determine the M.
Reserved
34
1
LED pulse
Max LED driver ratio
66
4
The PS LED Control register is used to control IR LED.
B0
18
The LED pulse bits set the number of PS pulses that will be transmitted in one PS conversion time. More pulses
el
im
increase LED current consumption but also increase the PS detection distance.
Number of pulse(s)
l:
LED pulse selection (bits 5:4)
Te
00
，
01 (Default)
司
10
1
2
3
限
公
11
0
技
有
The LED driver ratio sets the max current on the LED driver. Higher ratio increases LED current consumption
讯
科
but also increase the PS detection distance.
Percentage of max LED current
00
16.7%
01
33.3%
10
66.7%
11 (Default)
100%
深
圳
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Pr
Max LED driver ratio (bits 1:0)
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PS Interrupt Mode Register
PS Interrupt Mode (Default = 0x01 )
BIT
B7
R/W
Reserved
B6
B5
B4
B3
B2
B1
B0
51
8
The PS_Algo bit is used to set PS interrupt mode. There are two behavior algorithms can be selected.
19
，
PS_Algo
廖
R
0x22
PS Interrupt mode
0
PS INT Mode 1 (Zone type)
1 (Default)
PS INT Mode 2 (Hysteresis type)
ar
71
44
y
B0
QQ
:
Mode 1 interrupt behavior is shown as Fig1. High/low absolute threshold are set at beginning. If PS DATA is
increased/decreased cross the high/low threshold and kept over N(1~8) persist times, an interrupt will be triggered.
58
5
When each interrupt is asserted, the host can de-assert INT pin by read E/F register and then host shall set another new
in
high/low absolute threshold specified for next time interrupts. The PS threshold is set by the register 0x2A / 0x2B /
Fig1. The behavior of PS INT mode 1 with control flow diagram.
Pr
讯
科
技
有
限
公
司
，
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l:
el
im
18
66
4
34
1
0x2C / 0x2D.
合
Mode 2 performs a hysteresis behavior. Assume the PS object status is “near”, PS interrupt will be triggered only
市
金
if the PS data is cross below the PS low threshold (The interrupt is triggered when PS object status changed). On the
PS high threshold. The PS threshold can be set by the register 0x2A / 0x2B / 0x2C / 0x2D.
深
圳
other hand, assume the PS object status is “away”, PS interrupt will be triggered only if the PS data is cross above the
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5
QQ
:
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44
y
51
8
19
，
廖
R
LITE-ON SEMICONDUCTOR CORP.
PS Mean Time Register
18
PS Mean Time (Default=0x00)
el
im
0x23
66
4
34
1
in
Fig2. The behavior of PS INT mode 2 with control flow diagram.
R/W
Reserved
B5
B4
B3
B2
l:
B6
B1
B0
Mean_time
Te
B7
，
BIT
司
This control bits are used to setup the PS integrated time.
B1B0=’00’, 1 time (mean time =12.5ms) (Default)
2.
B1B0=’01’, 2 time (mean time =25ms)
3.
B1B0=’10’, 3 time (mean time =37.5ms)
4.
B1B0=’11’, 4 time (mean time =50ms)
讯
科
技
有
限
公
1.
合
Pr
PS LED Waiting Time Register
PS LED Waiting Time (Default=0x00)
BIT
B7
R/W
Reserved
B6
B5
B4
B3
B2
B1
B0
PS LED Waiting
深
圳
市
金
0x24
The PS waiting time sets LED’s ON/OFF time and it also affects proximity sensor’s response time. It can save
system’s power consumption by setting longer waiting time but it increases response time to the system as well. The
timing chart of PS waiting time is showed as below.
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l:
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im
18
66
4
34
1
in
58
5
QQ
:
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51
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19
，
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R
LITE-ON SEMICONDUCTOR CORP.
司
Longer PS waiting time increases the PS conversion time as well. Table for PS waiting time vs conversion time is
公
showed as below. The PS conversion time will be set by the PS waiting time (base on PS mean time setting=50ms).
Conversion time for PS
Conversion time for ALS + PS
0 (Default, no waiting)
50ms
150ms
1 (1 PS mean time)
100ms
300ms
2 (2 PS mean time)
150ms
450ms
…
…
…
63 (63 PS mean time)
3200ms
9600ms
深
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合
Pr
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技
有
限
PS waiting time (bits 4:0)
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25/31
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LSC
L
SC 敦 南 科 技
AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
PS Calibration Register
PS Calibration Lower Byte (Default=0x00)
BIT
B7
R/W
Reserved
0x29
PS Calibration Higher Byte (Default=0x00)
BIT
B7
R/W
PS_Cal[8:1]
B6
B5
B4
B3
B2
B1
B0
y
B4
B3
B2
B1
71
44
B5
B0
QQ
:
ar
B6
51
8
19
，
PS_Cal[0]
廖
R
0x28
Similar to ALS calibration for window loss compensation, the device also has PS calibration which could be used
to eliminate the differences of cross talk which is induced from top cover/glass after assembly. Total 9bits dynamic
58
5
range is available for resetting the cross talk to let the PS count indicates the distance directly. It is convenient for users
34
1
in
to set the same PS high/low threshold regardless individual difference between each device.
18
PS Low Threshold Lower Byte (Default = 0x00)
el
im
0x2A
66
4
PS Low Threshold Register
R/W
Reserved
B5
B4
B3
l:
B6
B2
B1
B0
PS Low Threshold Lower
Te
B7
Byte
公
司
，
BIT
PS Low Threshold Higher Byte (Default = 0x80)
BIT
B7
R/W
PS Low Threshold Higher Byte
技
有
限
0x2B
B5
B4
B3
B2
B1
B0
合
Pr
讯
科
B6
0x2C
PS High Threshold Lower Byte (Default = 0x00)
BIT
B7
R/W
Reserved
B6
B5
B4
B3
深
圳
市
金
PS High Threshold Register
B2
B1
B0
PS High Threshold
Lower Byte
Lite-On Semi. Corp. Confidential
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LSC
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AP3216C
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
0x2D
PS High Threshold Higher Byte (Default = 0x80)
BIT
B7
R/W
PS High Threshold Higher Byte
B5
B4
B3
B2
B1
B0
廖
R
B6
Rev0.80
19
，
The PS Threshold registers store the values of the high and low trigger points for comparison against PS DATA
(Registers 0x0E and 0x0F). The host can decide what kind of the PS interrupt behavior by setting the PS INT FORM
51
8
(Register 0x22) and the PS High/Low Threshold (Register 0x2A / 0x2B / 0x2C / 0x2D).
71
44
y
The PS Low Threshold registers are expressed as 10-bit data spread across two registers, PS Low Threshold
Lower byte and PS Low Threshold higher byte.
ar
PS low threshold = Reg_0x2B * 4 + Reg_0x2A
Lower part and PS High Threshold higher part.
深
圳
市
金
合
Pr
讯
科
技
有
限
公
司
，
Te
l:
el
im
18
66
4
34
1
in
58
5
PS high threshold = Reg_0x2D * 4 + Reg_0x2C
QQ
:
The PS High Threshold registers are expressed as 10-bit data spread across two registers, PS High Threshold
Lite-On Semi. Corp. Confidential
27/31
A Part of
Group
LSC
L
SC 敦 南 科 技
AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
深
圳
市
金
合
Pr
讯
科
技
有
限
公
司
，
Te
l:
el
im
18
66
4
34
1
in
58
5
QQ
:
ar
71
44
y
51
8
19
，
廖
R
Package Outline Dimensions
Notes:
All dimensions are in millimeters.
Lite-On Semi. Corp. Confidential
28/31
A Part of
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LSC
L
SC 敦 南 科 技
AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
QQ
:
ar
71
44
y
51
8
19
，
廖
R
Recommended Land Pattern
市
金
合
Pr
讯
科
技
有
限
公
司
，
Te
l:
el
im
18
66
4
34
1
in
58
5
Stencil
+/-0.05mm offset).
深
圳
Note : The dimensions of stencil are designed base on the SMT process tolerance (less than +/-3° rotation and
Lite-On Semi. Corp. Confidential
29/31
A Part of
Group
LSC
L
SC 敦 南 科 技
AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
深
圳
市
金
合
Pr
讯
科
技
有
限
公
司
，
Te
l:
el
im
18
66
4
34
1
in
58
5
QQ
:
ar
71
44
y
51
8
19
，
廖
R
Package Dimension of Tape and Reel
Lite-On Semi. Corp. Confidential
30/31
A Part of
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LSC
L
SC 敦 南 科 技
AP3216C
Rev0.80
3-in-1 Digital ALS + PS + IRLED Module
LITE-ON SEMICONDUCTOR CORP.
el
im
18
66
4
34
1
in
58
5
QQ
:
ar
71
44
y
51
8
19
，
廖
R
Recommended Reflow Profile
l:
Note : The actual profile may need to be adjusted base on the actual layout. When parts are placed upside down, proper
司
，
Te
protection/support is recommended, max reflow should not exceed 2x max
限
公
Important Notice and Disclaimer
技
有
LSC reserves the right to make changes to this document and its products and specifications at
any time without notice. Customers should obtain and confirm the latest product information
and specifications before final design, purchase or use.
市
金
合
Pr
讯
科
LSC makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose, nor does LSC assume any liability for application assistance or customer
product design. LSC does not warrant or accept any liability with products which are purchased
or used for any unintended or unauthorized application.
LSC products are not authorized for use as critical components in life support devices or systems
without express written approval of LSC.
深
圳
No license is granted by implication or otherwise under any intellectual property rights of LSC.
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