Product Specification PE83512 Product Description The PE83512 is a high-performance static UltraCMOS™ prescaler with a fixed divide ratio of 4. Its operating frequency range is DC to 1500 MHz. The PE83512 operates on a nominal 3 V supply and draws only 14 mA. It is packaged in a small 8-lead plastic MSOP and is ideal for frequency scaling and clock generation solutions. DC - 1500 MHz Low Power UltraCMOS™ Divide-by-4 Prescaler Military Operating Temperature Range Features • DC to 1500 MHz operation • Fixed divide ratio of 4 • Low-power operation: 14 mA typical The PE83512 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. @ 3.0 V • Ultra small package: 8-lead MSOP Figure 2. Package Type Figure 1. Functional Schematic Diagram 8-lead MSOP Table 1. Electrical Specifications (ZS = ZL = 50 Ω) 2.85 V ≤ VDD ≤ 3.15 V; -55° C ≤ TA ≤ 125° C, unless otherwise specified Parameter Conditions Minimum Typical Maximum Units 2.85 3.0 3.15 V OUTB Disabled 7 12 mA OUTB Enabled 14 25 mA DC 1500 MHz -5 +10 dBm 0 +10 dBm +5 +10 dBm Supply Voltage Supply Current1 Input Frequency (FIN) Input Power (PIN) Output Power 100 MHz ≤ Fin ≤ 1200 MHz -55°C ≤ TA ≤ 85°C 100 MHz ≤ Fin ≤ 1200 MHz 85°C ≥ TA ≥ 125°C 1200 MHz < Fin ≤ 1500 MHz -55°C ≤ TA ≤ 85°C DC < Fin ≤ 1500 MHz Document No. 70-0117-03 │ www.psemi.com +2 dBm ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 7 PE83512 Product Specification Electrostatic Discharge (ESD) Precautions Figure 3. Pin Configuration (Top View) VDD 1 IN 2 8 GND 7 OUT When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. PE83512 N/C 3 6 CTL GND 4 5 OUT Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 2. Pin Descriptions Pin No. Pin Name Device Functional Considerations Description The PE83512 divides an input signal, up to a frequency of 1500 MHz, by a factor of four thereby producing an output frequency at one fourth the input frequency. To work properly at higher frequency, the input and output signals (pins 2 , 7 & optional 5) must be AC coupled via an external capacitor. The input may be DC coupled for low frequency operation with care taken to remain within the specified DC input range for the device. 1 VDD Power supply pin. Bypassing is required (eg 1000 pF & 100 pF). 2 IN Input signal pin. Should be coupled with a capacitor (eg 1000 pF). 3 N/C No connection. This pin should be left open. 4 GND Ground pin. Ground pattern on the board should be as wide as possible to reduce ground impedance. 5 OUTB Inverted divided frequency output. This pin should be coupled with a capacitor (eg 1000 pF). The ground pattern on the board should be made as wide as possible to minimize ground impedance. See Figure 8 for a layout example. 6 CTL Control pin. When grounded OUTB is enabled. OUTB Control 7 OUT Divided frequency output pin. This pin should be coupled with a capacitor (eg 1000 pF). 8 GND Ground Pin. Pin 6 controls whether OUTB is enabled or disabled. Pin 6 has an internal pull-up resistor. With no connection (floating), OUTB is disabled. By grounding pin 6, OUTB is enabled. By enabling OUTB, this part will use roughly 5 mA more current. Table 3. Absolute Maximum Ratings Symbol Parameter/Conditions VDD Supply voltage Pin Input Power Min Max Units 4.0 V 15 dBm V VIN Voltage on input -0.3 VDD +0.3 TST Storage temperature range -65 150 °C TOP Operating temperature range -55 125 °C VESD ESD voltage (Human Body Model, MIL-STD 883) 2000 V Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Exposure to absolute maximum ratings for extended periods may affect device reliability. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 7 Document No. 70-0117-03 │ UltraCMOS™ RFIC Solutions PE83512 Product Specification Typical Performance Data: VDD = 3.0 V Figure 4. Input Sensitivity Figure 5. Device Current (OUTB Enabled) Figure 6. Output Power (OUT or OUTB) Document No. 70-0117-03 │ www.psemi.com ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7 PE83512 Product Specification Evaluation Kit Evaluation Kit Operation The PE83512 EK board was designed to ease customer evaluation of Peregrine’s high performance Military Grade divide-by-4 Prescaler. On this board, the device input (pin 2) is connected via J1 and a 50 Ω transmission line. A series capacitor (C3) provides the necessary DC block for the device input. It is important to note that the value of this capacitance will impact the performance of the device. A value of 1000 pF was found to be optimal for this board layout; other applications may require a different value. The device output (pin 7) is connected to connector J3 through a 50 Ω transmission line. A series capacitor (C1) provides the necessary DC block for the device output. Note that this capacitor must be chosen to have low impedance at the desired output frequency the device. The value of 1000pF was chosen to provide a wide operating range for the evaluation board. The board is constructed of a two-layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide above ground plane model with trace width of 0.030”, trace gaps of 0.007”, dielectric thickness of 0.028”, metal thickness of 0.0014” and εr of 4.4. Note that the predominate mode for these transmission lines is coplanar waveguide. J2 provides DC power to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device VDD pin (1). Two decoupling capacitors (10pF, 1000pF) are included on this trace. It is the responsibility of the customer to determine proper supply decoupling for their design application. Applications Support If you have a problem with your evaluation kit or if you have applications questions call (858) 731-9400 and ask for applications support. You may also contact us by fax or e-mail: Fax: (858) 731-9499 E-Mail: [email protected] Figure 7. Evaluation Board Layouts Peregrine Specification 101/0190 Figure 8. Evaluation Board Schematic Peregrine Specification 102/0201 ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 7 Document No. 70-0117-03 │ UltraCMOS™ RFIC Solutions PE83512 Product Specification Figure 9. Package Drawing 8-lead MSOP TOP VIEW 0.65BSC .525BSC 8 7 6 5 2.45±0.10 2X 3.00±0.10 0.51±0.13 -B- 0.51±0.13 1 2 3 4 2.95±0.10 .25 A B C -C0.86±0.08 2.95±0.10 1.10 MAX -A0.10 A 0.33+0.07 -0.08 0.08 A B C 0.10±0.05 3.00±0.10 4.90±0.15 3.00±0.10 FRONT VIEW Document No. 70-0117-03 │ www.psemi.com SIDE VIEW ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7 PE83512 Product Specification Figure 10. Tape and Reel Specifications 8-lead MSOP Pin1 Table 4. Ordering Information Order Code Part Marking Description Package Shipping Method 83512-01 PE83512 PE83512-08MSOP-50A 8-lead MSOP 50 units / Tube 83512-02 PE83512 PE83512-08MSOP-2000C 8-lead MSOP 2000 units / T&R 83512-00 PE83512-EK PE83512-08MSOP-EK Evaluation Kit 1 / Box ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 7 Document No. 70-0117-03 │ UltraCMOS™ RFIC Solutions PE83512 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corporation Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor, Korea Peregrine Semiconductor Europe #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 South Asia Pacific Space and Defense Products Peregrine Semiconductor, China Americas: Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0117-03 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 7