XICOR X5114LI

X5114
System Controller
FEATURES
DESCRIPTION
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The X5114 is a single-chip system controller that is used
in applications such as multiprocessing, telecommunications, data communications, cable systems, set top
boxes, etc. The chip can implement features such as
backplane communication, hot docking, cable diagnostics, etc.
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Simplifies Backplane Communications
Monitor Fault and “Hot Docking” Conditions
Ten Level Selectable Input Threshold
Two Fully Redundant SPI Serial I/O Ports
Programmable Output or Input Port Pins
—16 General I/O pins
—8 bit Port with 4 Handshake Modes
• Single Read Input Mode
• Multiple Read Input Mode
• Output Mode
• Bidirectional Mode
—Port Tristate Control
Programmable Interrupt and Mask Options
8-bit Direct Address Decoder allows Cascaded
255+ devices on one SPI bus
4K bits of EEPROM with 32 byte page write
Default Output Data on Port at Power-up
High Reliability EEPROM
—Endurance - 105 Data Changes
—Data Retention - 100 years
44-Pin PLCC, 48-Lead TQFP
The X5114 makes extensive use of nonvolatile memory
with 4,096 bits of general purpose EEPROM, nonvolatile
configuration registers, and nonvolatile programming of
the port pins. The ports can be set up as sixteen general
I/Os with pin selectable data direction (including eight
inputs with nonvolatile threshold selections) or as an
eight bit port with handshake. The chip is controlled via
two redundant 2MHz SPI serial ports.
A sophisticated interrupt controller provides notification of
a failed SPI command, changing conditions on an input,
handshake status, and I/O errors. Interrupts are
maskable.
On-chip EEPROM provides nonvolatile storage of
system status, manufacturing information, board ID or
other parameters.
FUNCTIONAL DIAGRAM
Port A Each Pin
CSb
SIb
SOb
SCKb
A0
.
.
.
.
A7
Output
Port A
Latch
SPI_A
Input
Interrupt
Logic
SPI_B
Address
Select
Decode
Serial
Engine/
Data Flow
Controller
Threshold
Adjust
IRQA
IRQB
PCE
Interrupt
Control A/B
Port
Config
Regs
Interrupt
Logic
Handshake
Logic
(PB7-PB4)
256 X 8
Desired
Value
256 X 8
Output
Port A
Handshake
Port B
Latch
EEPROM
Input
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port B Each Pin
= EEPROM
Xicor, Inc. 1994 - 1997 Patents Pending
7054-1.2 10/29/00 T13/C8/D24 SH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Output
Tristate
CSa
SIa
SOa
SCKa
Desired
Value
Output
Tristate
CSO
CSC
1
Characteristics subject to change without notice
X5114
PIN CONFIGURATION
PIN NAMES
Symbol
19
20
21
22
23
24
25
26
27
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PCE
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VCC
NC
NC
CSb
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
VSS
CSC
CSa
SCKa
SIa
SOa
IRQA
VSS
IRQB
SOb
SIb
SCKb
5
4
3
2
1
44
43
42
41
CSO
VCC
A7
A6
A5
A4
A3
A2
A1
A0
NC
44 Lead PLCC
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
SCKa, SCKb
SPI A, B Serial Clock
SIa, SIb, SOa, SOb
SPI A, B, Serial Data I/O
CSa, CSb
SPI A, B select
A7-A0
Device Address
IRQA, IRQB
Interrupt A, B Outputs
PCE
Port Chip Enable
PA7-PA0
Port A pins
PB7-PB0
Port B pins
CSO
Chip Select Output
CSC
Chip Select Cascade Output
VCC, VSS
System Supply, Ground
NC
No Connection
PIN DESCRIPTIONS
CSa /CSb (SPI A/B Chip Select)
A0
NC
PCE
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VCC
These are schmitt trigger input pins used by the host
system to select the X5114 SPI port. A HIGH to LOW
(falling) transition on CSa or CSb starts the X5114 serial
access. Both of these pins at logic “1” deselects the
device and places the SOa and SOb pins in a high
impedance state. In the event of a stuck LOW on either of
these pins, a HIGH to LOW transition on the other chip
select will override the inoperative serial port.
SCKa/SCKb (SPI A/B Serial Clock)
These are schmitt trigger input pins used by the host
system to supply the SPI serial clock. Only clock mode 3
is supported by X5114. When inactive, the SPI serial
clock is to be driven to a logic HIGH level.
NC
NC
CSb
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
VSS
CSa
SCKa
SIa
SOa
IRQA
NC
VSS
NC
IRQB
SOb
SIb
SCKb
47
46
45
44
43
42
41
40
39
38
CSC
NC
CSO
NC
VCC
A7
A6
A5
A4
A3
A2
A1
48 Lead TQFP
Function
SIa/SIb (SPI A/B Serial Input)
These are schmitt trigger, serial data inputs. They receive
device address, opcode, and data from the host system
at the rising edge of the serial clock (i.e. SCKa or SCKb).
SOa/SOb (SPI A/B Serial Output)
These are push-pull serial data outputs. They shift out
data after each falling edge of the serial clock and are
stable on the rising edge of the serial clock (i.e. SCKa or
SCKb). When the device is not outputting data or is in
standby, the serial data outputs will be in a high
impedance state.
2
X5114
IRQA/IRQB (Interrupt Outputs)
These are open-drain Interrupt Request output pins.
They are designed for multidrop wired ORing. Internal
registers control the operation of the IRQ lines. See
"CONTROL/STATUS REGISTERS" on page 12 for
information about the internal control registers. See
“INTERRUPT REQUESTS” on page 23. for an
operational description of the IRQ lines.
bank of devices while the device executing the NOP
ignores subsequent commands and data. The rising
edge of either the CSa or the CSb signal de-assertes the
CSC signal.
PCE (Port Chip Enable)
This is a dedicated active HIGH schmitt trigger input pin
to the X5114. The primary function of this input is to
inhibit the generation of interrupts via an external control
signal. When de-asserted (logic “0”), this input disables
the IRQA and IRQB outputs. This input may be
configured to both disable the IRQA and IRQB outputs
and tri-state all of the Port A and Port B output drivers
when de-asserted.
PA7-PA0/PB7-PB0 (Port A/Port B)
Each bit of these 8-bit ports can be programmed to act
as either an input or output. An 8-bit nonvolatile Data
Direction Control Register for each port (DDRA/DDRB)
controls the direction of each pin. All I/Os can enter a
high impedance state when PCE is inactive. This is a
configurable option (see "Port I/O Configuration Register
(PCR)" on page 14 for details). In addition to the I/O
programmability, Port A and Port B can be configured
with handshake to provide a high speed parallel data
transfer pathway. See "Handshake I/O subsystem" on
page 17 for details.
DEVICE ARCHITECTURE
The X5114 consists of two major sections. The first is a
dual independent SPI serial interface. This full duplex
interface provides seperate SPI ports for primary and
secondary host controllers, but does not support
simultaneous access. The SPI interface is compatible
with industry standard SPI hardware. The host uses a
command protocol to read the status of the X5114, to
read and write various function registers that control
device operation and to access the memory array.
A7-A0 (Device Address Inputs)
These inputs set a slave address for the X5114 (see
"Device Addressing" on page 3 for details about
addressing modes). These pins can be either hardwired
or actively driven. If hardwired, these pins need to be tied
to Vcc or Vss. If actively driven, the pins must be driven to
VIH or VIL and they must be constant and stable during
each transmission period.
The second section of the X5114 consists of a
sophisticated port structure. The dual 8 bit ports can be
configured in a number of ways to meet the specific
needs of the application. The port can serve as a general
I/O, with default outputs or default input compare values.
The port can also be configured with one of four different
handshake options.
VCC (System Supply)
This is the system supply voltage input for the device.
Two VCC pins are provided.
In addition to these two main sections, an interrupt
controller can be configured to report a number of
conditions back to the host microcontroller. See Figure 21
on page 23. These include failed SPI communications,
input changes, handshake conditions, or port interrupts.
VSS (System Ground)
This is the system ground voltage reference input for the
device. Two VSS pins are provided.
CSO (Chip Select Output)
This is an output pin to indicate that the host system is in
communication with the device. The CSO is asserted
active LOW (logic “0”) whenever the device is selected by
the host system. The CSO shall remain active during all
communications and shall be de-asserted with the rising
edge of either the CSa or the CSb signal. This signal
helps manage access to the SPI ports by two
independent host processors.
SERIAL COMMUNICATIONS
Two independent Serial Peripheral Interface (SPI) Ports
provide the primary communication connection to the
X5114.
Device Addressing
The X5114 supports a bidirectional bus oriented
protocol. This protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the transfer
is a master and the device being controlled is a slave.
CSC (Chip Select Cascade Output)
This is an output pin that enables device cascading.
When receiving a NOP instruction, the device asserts the
CSC signal active LOW (logic “0”). This enables another
3
X5114
The master will always initiate data transfers and provide
the clock for both transmit and receive operations. The
X5114 is considered a slave for all operations.
Software Device Addressing Mode
In this device addressing mode, each X5114 has a
unique slave address externally specified by the A7-A0
pins. The first byte transmitted to the device contains the
device address. This address is compared with the
external address pins, A7-A0. If matched, the device
performs the task specified by the Instruction opcode
sent in the next byte. If there is no match, the X5114
returns to the standby state.
The X5114 has special addressing mechanisms to allow
up to 255 devices (or more after using the NOP
command) to reside on one SPI communication bus.
This reduces the number of bus lines required to talk to
multiple X5114 devices.
Communication to the device begins with a start
condition. This consists of the falling edge of CSa or CSb.
Following a CSa/CSb HIGH to LOW, the master selects
one of many X5114 devices on the SPI bus, by
transmitting a slave address (Software Device
Addressing) or selects the only device on the bus using
the CSa/CSb signal (Hardware Device Addressing).
Device Address (Software Addressing only)
DA7
DA6
DA5
DA4
DA3
DA2
MSB
Software Addressed:
CSa/CSb
SCKa/SCKb
Instruction
SIa/SIb
D D D D D D D D O O O O O O O O
A A A A A A A A P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SOa/SOb
S S S S S S S S
7 6 5 4 3 2 1 0
Status
Data In
Don’t Care
Data Out
D D D D D D D D
7 6 5 4 3 2 1 0
CSO
Hardware Addressed:
CSa/CSb
SCKa/SCKb
Instruction
SIa/SIb
O O O O O O O O
P P P P P P P P
7 6 5 4 3 2 1 0
Status
SOa/SOb
S S S S S S S S
7 6 5 4 3 2 1 0
CSO
4
DA0
LSB
FIGURE 1. SPI Communications - Addressing Modes (Read example)
Device Address
DA1
Data In
Don’t Care
Data Out
D D D D D D D D
7 6 5 4 3 2 1 0
X5114
Hardware Device Addressing Mode
In this addressing mode, all the external address pins are
tied to logic “0”. The device is selected solely by the CSa
or CSb pins. As soon as the CSa or CSb pin goes LOW
and stays LOW, the device will be in the active state. No
slave address byte is needed in this mode.
“0101” = Port I/O Configuration Register operation,
“1100” = Port IRQ Error Register operation,
“1110” = Port IRQ Failed Command Register operation,
“1111” = Port Registers operation.
Chip Select Output/Device Cascade (CSO/CSC)
The CSO and CSC output pins have two major functions.
The CSO pin can be used as a chip select indicator. This
signal indicates that the host processor has selected this
device.
Each instruction must be proceeded with a HIGH to LOW
transition on CSa or CSb and be terminated by a LOW to
HIGH transition on CSa or CSb. There is no restriction as
to which of the two SPI interface ports receives an
instruction or combination of instructions.
The CSC signal allows the cascade of multiple banks of
X5114 devices. In a cascade mode, the CSC output of a
selected X5114 selects another external device by using
the NOP instruction. (see "NOP" on page 7 )
If the instruction initiates a nonvolatile write operation, as
indicated in Table 1, “Instruction Opcodes,” on page 6
and in the instruction definitions, the write cycle begins at
the rising edge of the CSa or CSb signals. However if the
CSa or CSb goes HIGH before the device address,
command, and data are sent completely (e.g. when the
clock is not a multiple of eight), then no nonvolatile write
cycle starts, the WEL will not reset, and there will be an
incomplete transmission (i.e. a failed command). In a
failed command, an interrupt signal informs the host
processor of a fault condition. After completion of a
nonvolatile write cycle, the circuitry automatically clears
the Write Enable Latch (WEL).
INSTRUCTION SUMMARY
Instruction Opcode
The second byte transmitted to the device (or the first
byte in hardware addressing mode) contains the
Instruction opcode that defines the operation to be
performed. All the opcode bits have been specially
arranged to achieve a 2-bit difference between opcodes
to reduce the possibility of inadvertent operations.
Instruction Opcode
OP7
OP6
OP5
OP4
OP3
MSB
OP2
OP1
The nonvolatile write typically takes much less than the
maximum time to complete. However, the Status
Register WIP bit indicates the nonvolatile wrte status.
After receiving a valid address, the X5114 returns the
status register contents so an host has an early end of
write cycle indication. If WIP is HIGH, the write is still in
progress. If WIP is LOW, the X5114 is available for
continued operations.
OP0
LSB
OP7, OP6
“00” = memory operation,
“01” = port A operation,
“10” = port B operation,
“11” = Control Register operation.
OP5, OP4
“01” = port-related read command,
“10” = port-related write command.
OP3, OP2, OP1, OP0
“0000” = Configuration Register operation,
“0001” = Port Latch operation,
“0010” = Port Desired Value Register operation,
“0100” = Port Data Direction Register operation,
“1000” = Port IRQ Mask Register operation,
“0011” = Port IRQ Configuration Register operation,
5
X5114
Table 1. Instruction Opcodes
Command
Operation
Opcode (3)
Operation
HV Write Cycle Bytes(2)
NOP
00h [0000 0000]
No Operation
2+
RML
05h [0000 0101]
Read Memory Low
4+
06h [0000 0110]
Read Memory High
4+
09h [0000 1001]
Write Memory Low
Y
4+
WMH
0Ah [0000 1010]
Write Memory High
Y
4+
SWEL
03h [0000 0011]
Set Write Enable Latch
2
RWEL
0Ch [0000 1100]
Reset Write Enable Latch
2
RMPR
DFh [1101 1111]
Read Multiple Port Registers
16
RPAL
51h [0101 0001]
Read Port A Latch
3
RPBL
91h [1001 0001]
Read Port B Latch
3
52h [0101 0010]
Read Desired Value Register Port A
3
92h [1001 0010]
Read Desired Value Register Port B
3
RMH
WML
RDVRA
Memory
Access
Read Port
RDVRB
RDDRA
54h [0101 0100]
Read Data Direction Register Port A
3
RDDRB
94h [1001 0100]
Read Data Direction Register Port B
3
WMPR
EFh [1110 1111]
Write Multiple Port Registers
WDVRA
WDVRB
62h [0110 0010]
Write Desired Value Register Port A
Y
Y
11
(1)
3
(1)
3
A2h [1010 0010]
Write Desired Value Register Port B
WDDRA
64h [0110 0100]
Write Data Direction Register Port A
Y
3
WDDRB
A4h [1010 0100]
Write Data Direction Register Port B
Y
3
5Ch [0101 1100]
Read IRQA Error Register
RIAE
RIBE
Write Port
Read
Error
Condition
Y
3
9Ch [1001 1100]
Read IRQB Error Register
3
DEh [1101 1110]
Read IRQ Failed Command Register
3
58h [0101 1000]
Read IRQ Mask Register Port A
3
98h [1001 1000]
Read IRQ Mask Register Port B
3
D3h [1101 0011]
Read IRQ Configuration Register
3
D5h [1101 0101]
Read Port I/O Configuration Register
3
RTBL
D0h [1101 0000]
Read Threshold/Block Lock Register
3
WIAM
68h [0110 1000]
Write IRQ Mask Register Port A
RFCR
RIAM
RIBM
RICR
RPCR
WIBM
WICR
WPCR
WTBL
Read
Configuration
Write
Configuration
Y
3
A8h [1010 1000]
Write IRQ Mask Register Port B
Y
3
E3h [1110 0011]
Write IRQ Configuration Register
Y
3
E5h [1110 0101]
Write Port I/O Configuration Register
Y
3
E0h [1110 0000]
Write Threshold/Block Lock Register
Y
3
Notes:
(1) In this condition, the HV Write Cycle will not proceed when the X5114 is configured in the handshake mode.
(2) The number of command bytes listed here is for software addressing mode. For memory sequential read and page write, the
minimum number is 4. The minimum number of bytes required for NOP is 2.
(3) All other possible instruction opcodes are illegal commands.
6
X5114
NOP
array boundary ($0FFh), the address counter continues
to the first address in the upper half of the memory
($100h). When reaching the upper address boundary
($1FFh), the address counter rolls over to address
$000h, allowing the read cycle to be continued
indefinitely. The read cycle is terminated by taking CSa or
CSb high.
No Operation
NOP is a special instruction opcode which accesses the
device without any operation. It is primarily used in
conjunction with the CSC output. After a NOP, CSC goes
LOW and the device goes into standby, ignoring any
subsequent data sent on the SI pin and putting the SO
pin in a high impedance state. With the NOP instruction,
the host processor can communicate with other SPI
devices (including other X5114s) in the system without
affecting the currently selected device. In this way, an
unlimited number of X5114s can reside in a system.
RMH
Read Memory High
The Read Memory High instruction allows users to read
the data in the upper half of the memory array from
$100h to $1FFh. Its function is similar to the RML
Command.
Memory Access Operations
To decode all 512 bytes in the memory array requires a
9-bit address. This would normally require a 2-byte
memory address. However, the X5114 uses two different
read opcodes (RMH and RML) and two different write
opcodes (WMH and WML) to reduce the number of
bytes in the command, with the most significant bit of the
address incorporated in the instruction opcode. The
RMH and WMH Opcodes access the upper half
($100h-$1FFh) of the array while the RML and WML
Opcodes access the lower half ($000h-$0FFh).
WML
Write Memory Low
The Write Memory Low instruction writes new data to the
lower half of the memory array from $000h to $0FFh.
Prior to any attempt to write data into the memory array,
the Write Enable Latch must first be set by issuing the
SWEL instruction. The user may write up to 32 bytes of
data to the memory in a single write instruction. The only
restriction is that the 32-byte data must reside on the
same page, i.e. the upper 3 address bits must be the
same for all of the bytes of data to be written. The lowest
5 address bits automatically increment after transmission
of each byte. After the lowest 5 address bits reach
$11111b, they roll over to $00000b while the 3 higher
order address bits remain unchanged. The 32-byte page
can be written with data and then over-written indefinitely.
In this case, only the last 32 bytes of data transmitted will
be written to the EEPROM during the nonvolatile write
cycle which follows.
RML
Read Memory Low
The Read Memory Low instruction reads the data in the
lower half of the memory array, from address $000h to
$0FFh. After sending the instruction opcode and byte
address, the data at the selected address shifts out on
the SO line. Continued clocking sequentially shifts out
data stored in memory at the next address and
automatically increments the address to the next location
after each byte of data. When reaching the lower half
Figure 2. NOP (No Operation)
CSa/CSb
SIa/SIb
SOa/SOb
Device
Address
NONVOLATILE
Instruction
Opcode
SR
Data
CSO
CSC
7
X5114
WMH
NONVOLATILE
register. Setting the Write Enable Latch sets the WEL flag
in the Status Register (SR) to “1”. The Write Enable Latch
remains set until a Reset WEL instruction, the device
powers down, or the completion of a nonvolatile write
operation.
Write Memory High
The Write Memory High instruction allows users to write
new data to the upper half of the memory array from
$100h to $1FFh. Its function is similar to Write Memory
Low.
SWEL
RWEL
VOLATILE
VOLATILE
Reset Write Enable Latch
The Reset Write Enable Latch instruction resets the
Write Enable Latch. Resetting the Write Enable Latch
resets the WEL flag in the Status Register (SR) to “0”.
The WEL bit LOW inhibits any nonvolatile memory write
operation.
Set Write Enable Latch
The Set Write Enable Latch instruction sets the Write
Enable Latch. This instruction must be completed before
any nonvolatile write cycle operation can begin. Setting
the WEL is not required prior to a write to a volatile
Figure 3. Read Memory (RML or RMH)
CSa/CSb
SIa/SIb
Device
Address
Instruction
Opcode
Memory
Address
SR
Data
SOa/SOb
Memory
Data-1st
Memory
• • • • • • • • Data-512nd
Figure 4. Write Memory (WML or WMH)
CSa/CSb
SIa, SIb
Device
Address
Instruction
Opcode
Memory
Address
Memory
Data-1st
SR
Data
SOa, SOb
Figure 5. Set/Reset Write Enable Latch (SWEL/RWEL)
CSa/CSb
SIa/SIb
Device
Address
Instruction
Opcode
SR
Data
SOa/SOb
8
••••••••
Nonvolatile
Memory
Data-32nd Write Cycle
X5114
Read Port Operations
In the handshake mode, the external strobe signal
(STRA) latches data into the PORT A Latch. The RPAL
instruction triggers the input handshake sequence and
reads data from the PORT A Latch.
RMPR
Read Multiple Port Registers
The RMPR Instruction allows the user to read all of the
Port-related registers, both volatile and non-volatile. See
Figure 6 on page 10. After the sending the instruction
opcode on the SIa or SIb line, the host reads data out on
the SOa or SOb line in the order as shown in Table 2,
“Multiple Register Read Order (RMPR),” on page 9.
Maintaining CSa or CSb LOW and clocking SCKa or
SCKb allows continuous reading of the registers. Once
the CSa or CSb goes HIGH, the command terminates.
For Port B, the data is always latched by the decoding of
the RPBL instruction.
RDVRA, RDVRB
Read Desired Value Register A, B
The RDVRA and RDVRB instructions read the contents
of the respective Desired Value Register (DVRA or
DVRB). See Figure 8 on page 10. In the general I/O
mode, the contents of DVRA or DVRB relate to fault
monitoring. In the handshake mode, the DVRA and
DVRB contain the status of the output pins.
Table 2. Multiple Register Read Order (RMPR)
Read
Order
Register
RDDRA, RDDRB
Description
1
PAL
Port A Latch
Read Data Direction Register A, B
2
PBL
Port B Latch
3
DDRA
Data Direction Reg. A
The RDDRA and RDDRB instructions read the current
settings of the Data Direction Register. See Figure 8 on
page 10.
4
DDRB
Data Direction Reg. B
5
IAM
IRQ Mask Register A
6
IBM
IRQ Mask Register B
WMPR
7
DVRA
Desired Value Register A
Write Multiple Port Registers
8
DVRB
Desired Value Register B
9
IAE
IRQA Error Register
10
IBE
IRQB Error Register
11
PCR
Port I/O Configuration Register
12
CR
Configuration Register
13
ICR
IRQ Configuration Register
14
FCR
IRQ Failed Command Register
The WMPR instruction writes to a number of Port-related
configuration registers in a single write operation. Figure
on page 10. After sending the device address and the
instuction opcode, data sent through the SI line will be
written successively to the registers. The data must be
written to the device in order, as shown in Table 3,
“Multiple Register Write Order (WMPR),” on page 11.
After the completing the sequence of data, a nonvolatile
write cycle begins after the CSa or CSb goes HIGH.
Write Port Operations
RPAL, RPBL
Read Port A, B Latch
The Port A Latch and Port B Latch are read only. The
RPAL and RPBL instructions read data from the Port A
Latch or Port B Latch.
In the General I/O mode, decoding of the RPAL
instruction latches data into the PORT A Latch. The data
returned from the Port A Latch provides a “snapshot” of
the conditions at the port pins when the RPAL instruction
was decoded.
9
NONVOLATILE
X5114
Figure 6. Read Multiple Port Registers (RMPR)
CSa/CSb
Device
Address
SIa, SIb
RMPR
Opcode
SR
Data
SOa/SOb
PBL
Data
PAL
Data
••••••••
FCR
Data
Figure 7. Write Multiple Port Registers (WMPR)
CSa/CSb
Device
Address
SIa/SIb
WMPR
Opcode
SR
Data
SOa/SOb
DVRA
Data
DVRB
Data
WMPR
Opcode
Figure 8. Read Register - Single
Figure 9. Write Register - Single
CSa/CSb
CSa/CSb
SIa/SIb
SOa/SOb
••••••••
Start
Nonvolatile
Write Cycle
ICR
Data
Device
Address
SIa/SIb
Instruction
Opcode
SR
Data
SOa/SOb
Register
Data
10
Device Instruction
Address Opcode
SR
Data
Register
Data
Instruction
Opcode
Start
Nonvolatile
Write
Cycle
X5114
Read Error Conditions
Table 3. Multiple Register Write Order (WMPR)
Write
Order
Register
RIAE, RIBE
Description
1
DVRA
Desired Value Reg. A
2
DVRB
Desired Value Reg. B
3
DDRA
Data Direction Reg. A
4
DDRB
Data Direction Reg. B
5
IAM
IRQ Mask Register A
6
IBM
IRQ Mask Register B
7
PCR
Port I/O Configuration Register
8
CR
Configuration Register
9
ICR
IRQ Configuration Register
WDVRA, WDVRB
Read IRQA, IRQB Error Register
The RIAE and RIBE instructions return the contents of
the IRQ Error Registers. See Figure 8 on page 10. This
provides status on port error conditions.
RFCR
Read Failed Command Register
The Read Failed Command Register instruction allows
the host to track the most recent bad command. A bad
command is defined as one with:
• an unknown or illegal instruction opcode
• an incomplete transmission of a command which can
be instruction opcode, address, or data. As an example, CSa or CSb goes HIGH when the clock count is
not a multiple of 8.
NONVOLATILE
Write Desired Value Register A, B
The WDVRA and WDVRB instructions write data to the
Desired Value Registers. See Figure 9 on page 10.
Detection of a bad command sets a Failed Command
(FC) flag in the Status Register (SR) and asserts the
IRQA or IRQB signal, if enabled. The Failed Command
Register contains the Error information. The host read of
the Failed Command Register clears IRQA and IRQB
signals and the FC flag. However, the RFCR instruction
will not clear the Failed Command Register.
In the general I/O mode, these instructions load the
Desired Value Registers with desired data to monitor the
input/output pin level (Fault Monitoring). This data value
compares with the signal on the corresponding input port
pins. Any differences can generate an interrupt. Taking
CSa or CSb HIGH following the WDVRA or WDVRB
instruction starts a nonvolatile write cycle that mirrors the
data into a nonvolatile location. Power cycling the device
restores the nonvolatile value to the DVRA and DVRB
registers.
The FCR will only store the most recent bad command if
there were more than one bad command in a sequence.
Also the information in the FCR is only updated when a
bad command is discovered.
In the handshake mode, the WDVRA instruction writes
data directly to the Port A output pins (i.e., no nonvolatile
write cycle) and triggers an output handshake sequence.
The WDVRB instruction writes data directly to the Port B
output pins 3-0 (pins 7-4 are not available since they are
part of the handshake mechanism). Data on Port B pins
3-0 are mirrored into a nonvolatile location by a
nonvolatile write cycle.
Read Configuration
WDDRA, WDDRB
RICR
RIAM, RIBM
Read IRQA, IRQB Mask Register
The RIAM and RIBM instructions return the contents of
the respective IRQ Mask Register. See Figure 8 on page
10.
NONVOLATILE
Read IRQ Configuration Register
Write Data Direction Register A, B
The RICR instruction returns the contents of the IRQ
Configuration Register. See Figure 8 on page 10.
The WDDRA and WDDRB instructions write new data to
the Data Direction Registers. See Figure 9 on page 10.
This selects the direction of each of the port pins.
RPCR
Read Port I/O Configuration Register
The RPCR instruction returns the contents of the PORT
I/O Configuration Register. See Figure 8 on page 10.
11
X5114
RTBL
Status Register (SR)
Read Threshold/Block Lock Register
WIP
The RTBL instruction returns the contents of the
Threshold/Block Lock Register. See Figure 8 on page 10.
FC
RDR XRE IRQA IRQB
Volatile
MSB
Write Configuration
WIAM, WIBM
WEL PCE
NONVOLATILE
WIP
Write IRQA, IRQB Mask Register
The WIAM and WIBM instructions write new data to the
respective IRQ Mask Register. See Figure 9 on page 10.
LSB
Write In Progress flag.
0
no nonvolatile write cycle in progress
1
nonvolatile write cycle is in progress
WEL Write Enable Latch flag
WICR
NONVOLATILE
Write IRQ Configuration Register
The WICR instruction writes new data into the IRQ
Configuration Register to change interrupt operations.
See Figure 9 on page 10.
WPCR
NONVOLATILE
write enable latch has not been set
1
write enable latch is set
PCE
PCE Pin Input Status
0
PCE pin is at Logic 0
1
PCE pin is at Logic 1
FC
Write Port I/O Configuration Register
The WPCR instruction writes new data into the Port I/O
Configuration Register to change the Port I/O
functionality. See Figure 9 on page 10.
WTBL
0
Failed Command flag—Power on
default = 1
0
no command failures
1
command failure (abnormal termination)
RDR Receive Data Ready flag
(Single Read Input and Bidirectional Modes)
NONVOLATILE
Write Threshold/Block Lock Register
The WTBL instruction writes new data to the
Threshold/Block Lock Register to select different modes
of operations. See Figure 9 on page 10.
0
no data is latched
1
latched data is ready for read at Port A
XRE
CONTROL/STATUS REGISTERS
The X5114 has a number of registers to monitor and
control the operation of the device. Access to the control
registers are via SPI Commands.
The status register contains the status of the most critical
operating conditions. The contents are placed on the
output pins in synchronization with the incoming op code
(providing the device is addressed correctly). The status
register cannot be written to directly.
Transmit Register Empty flag
(Output and Bidirectional Modes)
0
Port A data has not been read by the external
system and is not ready to accept new data
from the SPI interface
1
Port A is ready to accept the new data from the
SPI interface.
IRQA Interrupt Port A
0
Interrupt A is not asserted
1
Interrupt A is asserted
IRQB Interrupt Port B
12
0
Interrupt B is not asserted
1
Interrupt B is asserted
X5114
Threshold/Block Lock Register (TBL).
TU2
TU1
TU0
TL2
TL1
TL0
Port Desired Value Register (DVRA and DVRB)
AIN
BL
DVR
A7
Nonvolatile
MSB
DVR
A6
DVR
A5
DVR
A4
DVR
A3
DVR
A2
DVR
A1
General I/O = Nonvolatile, Handshake = Volatile
LSB
MSB
TU2,
TU1,
TU0
TL2,
TL1,
TL0
LSB
Input Threshold level upper bits
DVR
B7
These bits store the desired input threshold level
for the analog mode of pins PA7 to PA4
General I/O = Nonvolatile,
Handshake = Volatile
DVR
B6
DVR
B5
DVR
B4
DVR
B3
DVR
B2
DVR
B1
DVR
B0
Nonvolatile
MSB
LSB
Input Threshold level lower bits
The DVRA register has two functions. In the general I/O
mode, DVRA is nonvolatile and stores the desired output
data or the desired value for I/O monitoring. Writes to
DVRA in this mode generate a nonvolatile write cycle. In
the handshake mode, DVRA is volatile and there is no
nonvolatile write.
These bits store the desired input threshold level
for the analog mode of pins PA3 to PA0
ADS Analog/Digital Mode Select Bit
0
digital mode
1
analog mode
BL
DVR
A0
The DVRB Register bit3 to bit0 are always nonvolatile
regardless of the mode. DVRB7 to DVRB4 are
nonvolatile in the general I/O mode and store the Port B
output data or the desired value for I/O monitoring.
DVRB7 to DVRB4 are volatile in the handshake mode .
Block Lock Configuration
0
no memory block locked
1
address $000h to $1FFh locked (writes prohibited)
1 1 1 1
1 1 1 1
1 1 1 0
1 1 1 0
1 1 0 1
1 1 0 1
1 1 0 0
1 1 0 0
0
0
x
x
x
1 0 1 1
1 0 1 1
1 0 1 0
1 0 1 0
1 0 0 1
1 0 0 1
1 0 0 0
1 0 0 0
Vss
Vss
PA3-PA0
PA7-PA4
13
Internal Port Bus
x
Schmidt
Trigger
x
Filter
x
Vcc
Comparator
Vcc
ADS
TL2
TL1
TL0
ADS
TU2
TU1
TU0
Figure 10. Input Threshold Control Settings
X5114
Port I/O Configuration Register (PCR)
TRI
CEM
HS2
HS1
HS0
PLS
Port Latch (PAL and PBL)
EGA INVB
PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0
Nonvolatile
MSB
TRI
Volatile
LSB
MSB
PBL7 PBL6 PBL5 PBL4 PBL3 PBL2 PBL1 PBL0
Port tri-state configuration
(Output Mode only)
0
disables tri-state operation
1
enables tri-state operation
Volatile
MSB
PCE pin LOW disables IRQA and IRQB,
1
PCE pin LOW disables IRQA and IRQB and
tri-states all port outputs (regardless of the content of the DDR)
Decoding the SPI opcode always latches data into the
PORT B Latch, regardless of the I/O mode.
HS2,
HS1, General/Handshake Mode configuration
HS0
0xx
general I/O mode
100
Multiple Read Input Mode
(multiple read of the Port A Latch)
101
Single Read Input mode
(single read of the Port A Latch)
110
Output Mode
111
Bidirectional Mode
Port Data Direction Register (DDRA and DDRB)
DDR DDR DDR DDR DDR DDR DDR DDR
A7
A6
A5
A4
A3
A2
A1
A0
Nonvolatile
MSB
interlocked handshake mode
1
pulse handshake mode
EGA
LSB
DDR DDR DDR DDR DDR DDR DDR DDR
B7
B6
B5
B4
B3
B2
B1
B0
PLS Handshake Pulse/Interlocked Mode config.
0
LSB
Port Latches are read-only input registers. In the general
I/O mode, decoding the SPI opcode latches data into the
PORT A Latch. In the handshake mode, sensing the
STRA input latches input data into the PORT A Latch.
CEM Port Chip Enable Mode Configuration
0
LSB
Nonvolatile
MSB
LSB
Handshake strobe (STRA) active edge
0
falling edge active
1
rising edge active
DDRA7- Port A Data Direction Register
DDRA0
INVB Handshake ready (STRB, TDRE, RDRF) active
level
0
Logic ‘0’ is the active level
1
Logic ‘1’ is the active level
0
Port I/O in an input
1
Port I/O is an output
DDRB7- Port B Data Direction Register
DDRB0
0
Port I/O in an input
1
Port I/O is an output
During Handshake modes, all of DDRA and the upper
half of DDRB (DDRB7-DDRB4) are ignored.
14
X5114
IRQ Mask Register (IAM and IBM)
0
no, the Port B I/O has no error (Fault
Monitoring)
1
yes, the Port B I/O has an error (Fault
Monitoring)
IAM7 IAM6 IAM5 IAM4 IAM3 IAM2 IAM1 IAM0
Nonvolatile
MSB
LSB
IRQ Configuration Register (ICR)
IBM7 IBM6 IBM5 IBM4 IBM3 IBM2 IBM1 IBM0
0
ORAB ENFC ERDR EXRE EIOE ENA ENB
Nonvolatile
Fixed
Nonvolatile
MSB
LSB
IAM7IAM0
MSB
Port A Interrupt Mask
ORAB
0
Enables the Input/Output Error - Fault Monitoring on the corresponding Port A I/O pin
1
Disables the Input/Output Error - Fault
Monitoring on the corresponding Port A I/O
pin.
IBM7IBM0
Enables the Input/Output Error - Fault Monitoring on the corresponding Port B I/O pin
1
Disables the Input/Output Error - Fault
Monitoring on the corresponding Port B I/O
pin.
1
IRQA and IRQB provide redundancy and are
ORed together
IAE6
IAE5
IAE4
IAE3
IAE1
IAE0
IBE4
IBE3
1
enables interrupt generated by Failed Command
0
disables IRQA generated by the RDR flag
1
enables IRQA generated by the RDR flag.
IBE2
IBE1
IBE0
Volatile (Read only)
MSB
LSB
IAE7– Interrupt A Error Flags
IAE0
XRE interrupt configuration
0
disables IRQA generated by XRE flag
1
enables IRQA generated by XRE flag
EIOE
LSB
IBE5
disables interrupt generated by Failed Command
EXRE
IAE2
MSB
IBE6
0
ERDR Receive Data Ready interrupt configuration
Volatile (Read only)
IBE7
IRQA and IRQB individually represent Port A
and Port B interrupt status and are not ORed
together
ENFC Failed Command Interrupt configuration
IRQ Error Register (IAE and IBE)
IAE7
IRQA/IRQB Routing
0
Port B Interrupt Mask
0
LSB
Input/Output Error interrupt configuration
0
disables interrupt generated by Input/Output
Error
1
enables interrupt generated by Input/Output
Error
ENA
IRQA output configuration
0
disables IRQA interrupt output
1
enables IRQA interrupt output
0
no, the Port A I/O has no error (Fault
Monitoring)
ENB
IRQB output configuration
0
disables IRQB interrupt output
1
yes, the Port A I/O has an error (Fault
Monitoring)
1
enables IRQB interrupt output
IBE7– Interrupt B Error Flags
IBE0
15
X5114
Failed Command Register (FCR)
(DVRA/DVRB) and the Port Latch (PAL/PBL). The
DVRA/DVRB registers consist of a volatile and a
nonvolatile part.
FCR7 FCR6 FCR5 FCR4 FCR3 FCR2 FCR1 FCR0
Volatile
MSB
Port fault management logic allows each I/O the ability to
generate an interrupt condition. A mismatch between the
value at the pin and the Desired Value for that pin
generates a fault condition and sets a flag. The flag
triggers an output IRQA or IRQB signal when allowed to
by the EIOE and ENA/ENB bits in the IRQ Configuration
Register and by the PCE (Port Chip Enable) pin.
LSB
The Failed Command Register (FCR) contains an $FFh
if the bad command is unknown or is an incomplete
transmission of an opcode. The FCR contains the
corresponding instruction opcode, following an
incomplete transmission of the address or data.
The PCE pin can be configured so a LOW PCE disables
the output of interrupts. Or it will disable the output of
interrupts and force all port pins to a high impedance
state.
PORT I/O OPERATION
The X5114 has a total of 16 I/O pins equally divided
between Ports A and B. The functionality of the pins is
established by several non-volatile configuration
registers.
Port A and Port B pins configured as outputs power up
with a preset state. This is valuable if control of
peripherals is necessary before the host processor has
initialized after a power failure. Data written through the
SPI serial port to the DVRA or DVRB registers is latched
into both the volatile and nonvolatile parts of the register.
Upon a power up condition, the volatile part of the
Desired Value Register is restored by the contents of the
nonvolatile part and this restored data appears at the
output. At the same time, data is readable with the Read
Port instruction and the pin can generate an interrupt if
the output does not match the value in the desired value
register (for example, if the pin is shorted to ground and a
HIGH signal is expected).
The I/O Ports can be configured as General I/O or as one
of four Handshake Configurations.
Configured as general I/O, each of the pins of Port A and
Port B can be set as either an input or output via bits in a
nonvolatile Data Direction Register. In each of the four
handshake modes below, Port A provides an 8-bit
parallel data transfer with one, two or four of Port B’s pins
used for handshake signals (depending upon the
operational mode). Port B pins not used for handshake
are always used as general I/O.
General I/O
Ports A and B each consist of eight bidirectional pins
independently configured by a corresponding bit in a
non-volatile Data Direction Register (DDRA/DDRB). The
internal interface to Ports A and B consist of two
independent registers, the Desired Value Register
THRESHOLD CONTROL
Port A input pins can also be configured with an 10 level
analog threshold. The digital reference value was found
in the Desired Value Register with the compare threshold
set at VCC*0.5 by ADS bit LOW. Three nonvolatile bits in
the TBL and ADS HIGH select an analog reference level
Figure 11. General I/O and Fault Monitoring Configuration (Port A)
Bits From TBL Reg
TU2/TL2
TU1/TL1
TU0/TL0
AIN
Threshold
Control
Comp
Desired
Value
Filter
ADS
IAEx
MUX
PA7-PA0
16
PAL
RPAL
Instruction
Decode
DVRA
WDVRA
Instruction
Decode
X5114
for each port. If an input signal exceeds the analog
threshold, a HIGH is detected. This input compares with
the desired value register contents. A mismatch of the
two values generates a fault condition, sets a flag and
generates an interrupt as described for digital fault
monitoring. Reading data in from the port A pins latches
data into the PAL register.
The handshake I/O subsystem efficiently supports high
speed data transfers between an external system and a
controlling master through the SPI ports of the X5114.
These four handshake modes support a variety of 8-bit
parallel data applications, such as interfacing to a simple
8-bit latch, an A/D converter or a microcontroller. The
8-bit parallel data path uses Port A, with the handshake
I/O signals interfacing to Port B.
Handshake I/O subsystem
The handshake I/O subsystem involves all of Port A and
up to four Port B pins. The four primary modes of
operation for the handshake I/O subsystem are:
•
•
•
•
For applications which do not require high speed 8-bit
parallel data transfer, the handshake functions can
generally be ignored. When handshake functions are
used, the remaining Port B pins serve as general I/O
without interfering with the handshake functions.
Single Read Input
Multiple Read Input
Output
Bi-directional
Table 4 on page 17 shows the different functions of port
B pins for different port I/O handshake modes.
Table 4. Special Port B Pins in Handshake Modes
Handshake Mode
Mode Entry
HS2 HS1 HS0
Port B Pin
PB7
STRA
IN
EGA bit (PCR reg)
101
PB6
TDRE
OUT
INVB bit (PCR reg)
PB5/PB4
X
X
X
PB6
STRB
OUT
INVB
PB7/PB5/PB4
X
X
X
PB7
STRA
IN
EGA
PB5
RDRF
OUT
INVB
PB6/PB4
X
X
X
Read Input
Multiple Read Input
Output
Bi-directional
100
110
111
Pin Function
Data Direction
Configure Signal
Polarity
PB7
R/W
IN
none
PB6
TDRE
OUT
INVB
PB5
RDRF
OUT
INVB
PB4
PEN
IN
none
Single Read Input Mode
SIGNALS:
EXAMPLE APPLICATION:
• Port A is the high speed input data port.
• STRA (PB7) is the stobe input. An external device
uses this signal to write new data into the Port A Latch.
The EGA bit selects which edge of the STRA input will
register the input data.
• TDRE (PB6) is the ready output signal. This signal notifies the external device that new data can be written.
Reading the port data via the SPI port automatically
resets the TDRE signal. The invert bit (INVB) sets the
active level of the TDRE output signal.
• RDR Flag - The STRA signal sets the RDR flag in the
Status register. Once set, the RDR flag automatically
inhibits further writes into PORT A from the external
A local slave controller identifies a condition that requires
action and initiates a sequence by sending a command
byte to the X5114 through the parallel port. A Strobe
signal from the slave controller latches in the data and
generates an interrupt to a remote, host system. The host
reads the data on the SPI lines and takes appropriate
action. Reading the data automatically frees the port for
the next input byte.
MODE ENTRY:
Set HS2, HS1, HS0 bits in PCR register to 101
17
X5114
Figure 12. Single Read Input Mode - Parallel Write
STRA (PB7 in)
Port A Data
RDR (Flag)
Don’t Care
Valid Port Data
Don’t Care
Full
Empty
interlocked mode
TDRE (PB6 out)
pulsed mode
IRQA
Figure 13. Single Read Input Mode - SPI Read
CSa/CSb
SCKa/SCKb
Device Address
RPAL Instruction
D D D D D D D D O O O O O O O O
A A A A A A A A P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SIa/SIb
Status Register Data
S S S S S S S S
7 6 5 4 3 2 1 0
SOa/SOb
Don’t Care
PAL Data Out
D D D D D D D
7 6 5 4 3 2 1
D
0
interlocked mode
TDRE (PB6 out)
pulsed mode
IRQA
RDR (Flag)
device. The host system should not attempt to write to
the Port A Latch. The host processor can poll RDR
through the SPI port or RDR can generate an external
interrupt. The ERDR bit enables the RDR interrupt.
• PLS bit - The pulse bit (PLS) HIGH sets the TDRE signal to operate in an “interlocked” mode, where TDRE
“tracks” the RDR flag. The PLS bit LOW sets the handshake to operate in a “pulsed” mode.
Fault monitoring on pins PA7-PA0 and PB7-PB6 is
disabled in this mode. Fault monitoring and general I/O
functionality of the remaining six Port B pins remains
user configurable.
18
X5114
Figure 14. Multiple Read Input Mode - SPI Read
CSa/CSb
SCKa/SCKb
Device Address
Instruction
SIa/SIb
D D D D D D D D O O O O O O O O
A A A A A A A A P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SOa/SOb
S S S S S S S S
7 6 5 4 3 2 1 0
Status Register Data
Port A
Don’t Care
D7:D0 Data
D D D D D D D
7 6 5 4 3 2 1
D
0
D7:D0
STRB (PB6)
CSa/CSb
SCKa/SCKb
Don’t Care
Don’t Care
SIa/SIb
D7:D0 Data
D D D D D D D
7 6 5 4 3 2 1
SOa/SOb
Port A
D
0
D7:D0
STRB (PB6)
MODE ENTRY:
Multiple Read Input Mode
Set HS2, HS1, HS0 bits in PCR register to 100
EXAMPLE APPLICATION:
SIGNALS:
An A/D converter connects to the X5114 parallel port.
The host reads the A/D converter data through the SPI
port. Reading the data automatically generates a STRB
output signal that initiates a new A/D conversion cycle.
• Port A is the high speed input data port.
• STRB (PB6) is the strobe output. The invert bit (INVB)
sets the active level of STRB in the multiple read mode.
Reading Port A data through the SPI port automatically
19
X5114
Figure 15. Output Mode - SPI Write
CSa/CSb
SCKa/SCKb
Device Address
WDVRA Instruction
D D D D D D D D O O O O O O O O
A A A A A A A A P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SIa/SIb
PORT A Data
D D D D D D D D
7 6 5 4 3 2 1 0
Status Register Data
S S S S S S S S
7 6 5 4 3 2 1 0
SOa/SOb
interlocked mode
RDRF (PB5 out)
pulsed mode
IRQA
XRE (Flag)
Figure 16. Output Mode - Parallel Read
STRA (PB7 in)
Port A Data (Normal)
Static Valid Port Data
Port A Data (Tristate)
Valid Port Data
XRE (Flag)
interlocked mode
RDRF (PB5 out)
pulsed mode
IRQA
generates STRB. This mode gives the X5114 the
capability of performing multiple data reads while the
SPI select line, CSa or CSb remains asserted and
SCK clocks data through the SPI port.
Output Mode
EXAMPLE APPLICATION:
The host processor initiates a data byte transfer through
the SPI and Port A to a slave processor. The slave then
executes the command. This mechanism allows
numerous remote processors to reside on the same SPI
three wire bus to reduce interface complexity. In this
case, the remote processor does not need an SPI port,
but communicates via a parallel I/O.
20
X5114
MODE ENTRY:
the DVRA. The invert bit (INVB) sets the active level of
the RDRF output signal.
• STRA (PB7) is the strobe input. An external device
uses this signal to inform the host that data has been
read from Port A and that new data can be written. The
user selects the active edge of the STRA input with the
EGA bit.
• XRE Flag - The STRA signal sets the XRE flag in the
Status register. The host processor can poll XRE
through the SPI port or XRE can generate an external
interrupt. The EXRE bit in the ICR register enables the
XRE interrupt.
Set HS2, HS1, HS0 bits in PCR register to 110
SIGNALS:
• Port A - Parallel data is sent out through this port.
• DVRA Register - The host writes data through the SPI
port to this register. In this case, DVRA data is not mirrored into non-volatile memory as in the general I/O
mode.
• RDRF (PB6) is the output strobe signal. This signal
notifies the external device that new data was written to
Figure 17. Bi-directional Mode - SPI Write
CSa/CSb
SCKa/SCKb
Device Address
WDVRA Instruction
D D D D D D D D O O O O O O O O
A A A A A A A A P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SIa/SIb
Status Register Data
S S S S S S S S
7 6 5 4 3 2 1 0
SOa/SOb
interlocked mode
RDRF (PB5 out)
pulsed mode
IRQA
XRE (Flag)
Figure 18. Bi-directional Mode - Parallel Read
PEN (PB4 in)
R/W (PB7 in)
Port A Data (Tristate)
Valid Port Data
XRE (Flag)
interlocked mode
RDRF (PB5 out)
pulsed mode
IRQA
21
PORT A Data
D D D D D D D D
7 6 5 4 3 2 1 0
X5114
Figure 19. Bi-directional Mode - Parallel Write
PEN (PB4 in)
R/W (PB 7 in)
Port A Data
RDR (Flag)
interlocked mode
TDRE (PB6 out)
pulsed mode
IRQA
Figure 20. Bi-directional Mode - SPI Read
CSa/CSb
SCKa/SCKb
Device Address
SIa/SIb
RPAL Instruction
D D D D D D D D O O O O O O O O
A A A A A A A A P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Status Register Data
Don’t Care
PAL Data Out
S S S S S S S S D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SOa/SOb
interlocked mode
TDRE (PB6 out)
pulsed mode
IRQA
RDR (Flag)
• PLS bit - The pulse bit (PLS) HIGH sets RDRF signal
to operate in an “interlocked” mode, where RDRF
“tracks” the XRE flag. The PLS bit HIGH sets RDRF to
operate in a “pulsed” mode.
• The TRI bit HIGH disables the tri-state operation of the
port, making the outputs always active in this mode.
Bi-directional Mode
EXAMPLE APPLICATION:
This Mode provides full handshake capability to allow
bidirectional interraction between the host, communicating
over the SPI port and a slave processor communicating
over parallel port A. In this mode, Port A looks like an
SRAM to the slave processor.
Fault monitoring on pins PA7-PA0, PB7 and PB6 is
disabled in this mode. Fault monitoring and general I/O
functionality of the remaining six Port B pins remains
user configurable.
MODE ENTRY:
Set HS2, HS1, HS0 bits in PCR register to 111.
22
X5114
SIGNALS:
• INVB bit - The invert bit (INVB) sets the active level of
both the RDRF and TDRE output signals.
• The RDR flag in the status register provides status of
an external write to Port A. Writing data to the PAL sets
RDR HIGH. RDR going HIGH generates an interrupt
when the ERDR bit is set. Reading the PAL register
through the SPI port clears the RDR bit.
• The XRE flag in the status register provides status of
an external read of Port A. Writing data to the DVRA
through the SPI port sets XRE LOW. Reading the
DVRA register through Port A sets the XRE bit. XRE
going HIGH generates an interrupt when the EXRE bit
is set.
• PLS Bit - The pulse bit (PLS) LOW causes the RDRF
and TDRE signals to function “interlocked” with the
XRE and RDR flags respectively. The PLS bit HIGH
causes the RDR and TDRE signals to operate in a
“pulsed” mode. The Bi-directional mode disables Fault
monitoring on all Port A pins (PA7-PA0) and some Port
B pins (PB7-PB4).
• Port A - Bidirectional data passes through this port.
• DVRA Register - The host writes data through the SPI
port to this register. This SPI write operation sets the
XRE status flag LOW and asserts the RDRF signal.
The Slave Reads data from this register using PEN
LOW and R/W HIGH.
• Port A Latch (PAL) - The slave processor writes data
through Port A to this register, using PEN LOW and
R/W LOW. This write operation sets the RDR flag. The
host processor reads this register through the SPI port.
• R/W(PB7) is the read/write control for the slave processor. This signal works with the PEN input to make the
port look like a static RAM, where a HIGH on R/W
selects a read and a LOW selects a write. A read outputs the contents of the DVRA register on the port A
pins. A write transfers the data on the port A pins to the
Port A Latch (PAL).
• The PEN(PB4) input controls the Port A operation and
functions like a chip select. PEN HIGH sets all Port A
pins to a high impedance state. PEN LOW and R/W
HIGH initiates a read operation that terminates on the
rising edge of the PEN input. PEN LOW and R/W LOW
initiates a write operation that termnates with either the
R/W or PEN signals going HIGH.
• The TDRE(PB6) output signal provides notification that
data was read from Port A and the buffer is now empty.
• The RDRF(PB5) output signal notifies the slave processor that new data is available on Port A.
Fault monitoring and general I/O functions of the
remaining four port B pins remain user configurable.
INTERRUPT REQUESTS
Figure 21 shows the conditions for generating and
enabling the interrupts. If not masked out, the occurance
of an interrupt sets a flag in the IRQ Error Register. If
enabled (by setting the ENA or ENB bits), then an IRQA
Figure 21. Interrupt Flow Chart (Generating, Enabling And Resetting Interrupts)
MASK BITS
Active Only in General I/O
PA7
DVRA7
PA0
DVRA0
PB7
DVRB7
IAM7
ENABLE
BITS
ROUTING
BIT
IAE7(1)
IRQA Error Reg
=
IAM0
IAE0(1)
EIOE
IRQA Error Reg
=
IBM7
ORAB
IBE7(2)
IRQB Error Reg
IRQA
ENA
PB0
DVRB0
Active Only
in Handshake
=
ERROR
FLAGS
RDR
Signal
XRE
Signal
Failed
Command
=
IBM0
ORAB
IBE0(2)
IRQB Error Reg
RDR(3)
ERDR
ENB
IRQB
Status Reg
XRE(4)
EXRE
Status Reg
FC(5)
ENFC
Status Reg
23
(1)
(2)
(3)
(4)
(5)
Reset with RIAE instruction
Reset with RIBE instruction
Reset with RPAL instruction
Reset with RDVRA instruction
Reset with RFCR instruction
X5114
or IRQB output signal results, otherwise only the flag is
set. Certain instructions clear the interrupt condition (See
Figure 21). Clearing an interrupt condition resets the
interrupt flag and releases the interrupt output.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ...................... -65°C to +135°C
Storage Temperature ............................ -65°C to +150°C
Voltage on any pin with respect to Vss ...........-1V to +7V
DC Output Current................................................. 10mA
Lead Temperature (Soldering, 10 Seconds) .........300°C
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X5114
5V ±10%
–40°C
+85°C
Industrial
D.C. OPERATING CHARACTERISTICS
TA = -40°C to +85°C, Vcc = +4.5V to +5.5V, unless otherwise specified.
Symbol
Parameter
Min
Max
Unit
ICC
Vcc Supply Current, fSCKa or fSCKb = 2.0MHz; Vcc = +5.5V;
SOa, SOb = Open (Active, Non-Volatile Write States only)
5
mA
ISB
Standby Current, Vcc = +5.5V; VIN = Vss or Vcc;
CSa = CSb = Vcc;
2
mA
ILI
Input Leakage current, VIN = Vss to Vcc
10
uA
ILO
Output Leakage current, VOUT = Vss to Vcc
10
uA
(1)
Input Low Voltage
-0.5
Vcc x 0.3
V
(1)
VIH
Input High Voltage
Vcc x 0.7
Vcc + 0.5
V
VOL
Output Low Voltage, IOL = +3mA
0.4
V
VOH
Output High Voltage, VCC = +5V; IOH = -3mA
VIL
Vcc - 0.8
(1) VIL min. and VIH max. are for reference only and not tested.
24
V
X5114
ADS
TU2
TU1
TU0
PORT A INPUT THRESHOLD
1
1
1
1
Vcc * .9
4.5
±0.1
V
1
1
1
0
Vcc * .8
4.0
±0.1
V
1
1
0
1
Vcc * .7
3.5
±0.1
V
1
1
0
0
Vcc * .6
3.0
±0.1
V
0
x
x
x
Vcc * .5
2.5
±0.1
V
1
0
1
1
Vcc * .4
2.0
±0.1
V
1
0
1
0
Vcc * .3
1.5
±0.1
V
1
0
0
1
Vcc * .2
1.0
±0.1
V
1
0
0
0
Vcc * .1
0.5
±0.1
V
Parameter(1)
Input Port A Threshold Level
Typ
Typ
(Vcc=5V)
Max.
Error
Units
Comments
ADS, TU2-TU0 are
bits in the Threshold/Block Lock Register (TBL)
Notes: (1) These parameters are periodically sampled and not 100% tested.
CAPACITANCE
TA = +25°C, VCC = +5V, fSCK = 2.0MHz
Symbol
COUT
CIN
(1)
(1)
Parameter
Max
Unit
Test Conditions
Output Capacitance
10
pF
VOUT = 0V
Input Capacitance
6
pF
VIN = 0V
Notes: (1) This parameter is periodically sampled and not 100% tested.
POWER-ON TIMING
Symbol
tRVCC
(1)
Parameter
Min
Vcc Rise Time
Max
Unit
0.1
V/uS
tPOR
Power Supply Stable to Issuance of an Instruction without nonvolatile write Cycle
1
mS
tPOW(1)
Power Supply Stable to Issuance of an Instruction with a nonvolatile write Cycle
5
mS
25
X5114
A.C. CONDITIONS OF TEST
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 nS
VCC x 0.5
Input and Output Timing Levels
Output Load
Equivalent Output
Equivalent A.C. Test Circuits
5V
Port A
Port B
SO
CSC
CSO
704Ω
5V
920Ω
826Ω
IRQA
IRQB
100pF
100pF
26
X5114
A.C. CHARACTERISTICS
SPI Timing (SPI Clock Mode 3 Only)
TA = -40°C to +85°C, Vcc = 4.5V to +5.5V, unless otherwise specified.
Symbol
Parameter
Min
Max
Unit
2
MHz
fSCK
SPI Clock Frequency
tCYC
SPI Clock Cycle Time
500
nS
tWH
SPI Clock High Time
200
nS
tWL
SPI Clock Low Time
200
nS
tLEAD
Lead Time
200
nS
tLAG
Lag Time
400
nS
tSU
Input Setup Time
50
nS
tH
Input Hold Time
50
nS
tRI
(1)
Input Rise Time
tFI
(1)
Input Fall Time
tDIS
50
50
SO Output Disable Time
0
SO Output Valid Time
tV
tHO
nS
nS
100
SO Output Hold Time
nS
0
nS
nS
tRO
(1)
SO Output Rise Time
50
nS
tFO
(1)
SO Output Fall Time
50
nS
TI
SPI Noise Suppression Time Constant
20
nS
tCS
SPIA_CS or SPIB_CS Deselect Time
100
tASU
Device Address Setup Time
100
nS
tAH
Device Address Hold Time
0
nS
nS
Notes: (1) This parameter is periodically sampled and not 100% tested.
NONVOLATILE WRITE CYCLE TIMING
Symbol
tWC
Parameter
Nonvolatile Write Cycle Time
27
Typ
Max
Unit
5
10
mS
X5114
Input Timing
tCS
CSa/CSb
tLEAD
tCYC
SCKa/SCKb
tSU
tH
...
tWH
...
tWL
MSB
SIa/SIb
tLAG
tRI
tFI
LSB
Output Timing
CSa/CSb
SCKa/SCKb
tV
tHO
...
MSB
SOa/SOb
...
tDIS
LSB
Hardware Device Address Timing
(Any Instruction)
CSa/CSb
tAH
tASU
A0
|
A7
IRQ GENERATION TIMING
Symbol
Parameter
Min
Max
Unit
tIOE
Interrupt Output Enable time (Initial error condition valid or Error condition still valid after reset of error flag.)
250
800
nS
tFCE
Failed Command Enable time (CS HIGH to Failed Command error valid)
250
800
nS
28
X5114
Fault Condition
Interrupt condition
still exists
IRQA or IRQB
tIOE
tIOE
CSa/CSb
SCKa/SCKb
SIa/SIb
C1
C0
Don't Care
RIAE or RIBE
Instruction
Failed Command Timing
IRQA, IRQB
tFCE
CSa/CSb
Failed Instruction
29
X5114
GENERAL I/O TIMING
Symbol
Parameter
Min
Max
Unit
tPSU
Port Setup Time
50
nS
tPH
Port Hold Time
50
nS
Port Data Output Valid Time
100
nS
tPDO
Internal (SPI) Read Data From Port A/Port B
SCKa/SCKb
SIa/SIb
C1
C0
Don't Care
Don't Care
RPAL/RPBL Instruction
SOa/SOb D1
D0
D7
SR Data
tPSU
D0
PAL/PBL Data
tPH
Data [7:0]
Port A/Port B (in)
Internal (SPI) Write Data to Port A/Port B
SCKa/SCKb
SIa/SIb
D1
D0
Data to DVRA/DVRB
SOa/SOb
tPDO
Port A/Port B(out)
Old Port A/Port B Data
30
New Port A/Port B Data
X5114
INPUT MODE TIMING
Symbol
Parameter
Min
Max
Unit
tPSU
Port Setup Time
50
nS
tPH
Port Hold Time
70
nS
tWSTR
Write Strobe Time
150
nS
tRDRF
RDR Full Time
100
nS
tRDRE
RDR Empty Time
100
nS
tRDRP
RDR Pulse Time
250
1000
nS
tPWRF
Port Write RDR Full Time
250
800
nS
tPRRE
Port Read RDR Empty Time
500
nS
tSTRH
Strobe High Time
100
nS
tSTRL
Strobe Low Time
100
nS
Single Read input Mode - Parallel Write Data to Port A
tWSTR
STRA (PB7 in)
tPSU
Port A Data (in)
tPH
Valid Port Data
tRDRF
(interlocked mode)
TDRE (PB6 out)
(pulsed mode)
tPWRF
IRQA
RDR (flag)
Empty
31
Full
X5114
Single Read input Mode - SPI Read Data From Port A
SCKa/SCKb
SIa/SIb
C1
C0
Don't Care
Don't Care
RPAL Instruction
SOa/SOb
D0
D1
D7
SR Data
D6
PAL Data
tRDRE
(interlocked mode)
tRDRE
TDRE (PB6 out)
tRDRP
(pulsed mode)
tPRRE
IRQA
RDR (flag)
Empty
Full
Multiple Read input Mode - SPI Read Data From Port A
SCKa/SCKb
SIa/SIb
C1
C0
Don't Care
Don't Care
—1st read = RPAL Instruction
subsequent reads = don’t care
SOa/SOb (1st read) D1
D0
D7
—1st read = SR Data
subsequent reads = tristate
tPSU
Port A (in)
D1
D0
PAL Data
tPH
Data [7:0]
tSTRH
STRB (PB6-out)
32
tSTRL
X5114
OUTPUT MODE TIMING
Symbol
Max
Unit
tPV
Port Valid Time
Parameter
Min
150
nS
tPR
Port Read Time
100
nS
tPD
Port XRE Disable Time
0
ns
150
nS
tRSTR
Read Strobe Pulse
tXREF
XRE Full Time
250
nS
tXREE
XRE Empty Time
100
nS
tXREP
XRE Pulse Time
1000
nS
tPWXF
Port Write XRE Full Set Time
500
nS
tPRXE
Port Read XRE Empty Time
800
nS
250
250
Output Mode - SPI Write Data to Port A
SCKa/SCKb
SIa/SIb
D1
D0
Port A Data
tPV
Ports (Driven Outputs)
Old Port A Data
New Port A Data
tXREF
(interlocked mode)
tXREF
RDRF (PB5 out)
tXREP
(pulsed mode)
tPWXF
IRQA
XRE (flag)
Empty
33
Full
X5114
Output Mode - Parallel Read Data From Port A
tRSTR
STRA (PB7 in)
Valid Port Data
Ports (Driven Outputs)
tPR
tPD
Port A Pins (Tri-State Outputs)
Valid Port Data
tXREE
(interlocked mode)
RDRF (PB5 out)
(pulsed mode)
tPRXE
IRQA
Full
XRE (flag)
Empty
BI-DIRECTIONAL TIMING
Symbol
Parameter
Min
Max
Unit
tPSU
Port Setup Time
50
nS
tPH
Port Hold Time
50
nS
tPV
Port Valid Time
100
nS
tRDRF
RDR Full Time
100
nS
tRDRE
RDR Empty Time
100
nS
tRDRP
RDR Pulse Time
250
1000
nS
tPWRF
Port Write RDR Full Time
250
800
nS
tPRRE
Port Read RDR Empty Time
500
nS
tXREF
XRE Full Time
250
nS
tXREE
XRE Empty Time
100
nS
tXREP
XRE Pulse Time
1000
nS
tPWXF
Port Write XRE Full Set Time
500
nS
tPRXE
Port Read XRE Empty Time
250
800
nS
tPEW
Port Enable Write Time
150
tPEPR
Port Read Time
tPEPD
Port XRE Disable Time
0
ns
tPEWS
R/W Setup Time
20
nS
tPEWH
R/W Hold Time
0
nS
150
nS
tPER
250
nS
100
Port Enable Read Time
34
nS
X5114
Bi-directional Mode - Parallel Write Data to Port A
tPEW
PEN (PB4 in)
R/W (PB7 in)
tPEWH
tPEWS
tPSU
Port A Pins (in)
tPH
Valid Port Data
tRDRF
(interlocked mode)
TDRE (PB6 out)
(pulsed mode)
tPWRF
IRQA
RDR (flag)
Empty
Full
Bi-directional Mode - SPI Read Data From Port A
SCKa/SCKb
SOa/SOb
D0
D7
SR Data
PAL Data
tRDRE
tRDRE
(interlocked mode)
tRDRP
TDRE (PB6 out)
(pulsed mode)
tPRRE
IRQA
RDR (flag)
Empty
Full
35
X5114
Bi-directional Mode - SPI Write Data to Port A
SCKa/SCKb
SIa/SIb
D1
D0
Port A Data
tPV
Ports (Driven Outputs)
Old Port A Data
New Port A Data
tXREF
(interlocked mode)
tXREF
RDRF (PB5 out)
tXREP
(pulsed mode)
tPWXF
IRQA
XRE (flag)
Empty
Full
Bi-directional Mode - Parallel Read Data From Port A
tPER
PEN (PB4 in)
R/W (PB7 in)
tPEPR
Port A Pins (out)
tPEPD
Valid Port Data
tXREE
(interlocked mode)
RDRF (PB5 out)
(pulsed mode)
tPRXE
IRQA
XRE (flag)
Full
Empty
36
X5114
CSO/CSC TIMING
Symbol
Max
Unit
tCSOE
Chip Select Output Enable time
Parameter
Min
200
nS
tCSCE
Chip Select Cascade Enable time
200
nS
tCSOD
Chip Select Output Disable time
100
nS
tCSCD
Chip Select Cascade Disable time
100
nS
CSO Timing (Enable)
CSa/CSb
SCKa/SCKb
SIa/SIb
A1
A0
C7
Device Address
C6
Device Command
tCSOE
CSO
CSC Timing (Enable)
CSa/CSb
SCKa/SCKb
SIa/SIb
C1
C0
Don't Care
NOP Instruction
tCSCE
CSC
CSO/CSC Timing (Disable)
CSa/CSb
tCSOD
CSO
tCSCD
CSC
37
Don't Care
X5114
PACKAGING INFORMATION
44-PIN PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.020 (0.51)
0.110 (2.79)
0.100 (2.54)
0.695 (17.65)
0.685 (17.40)
0.655 (16.64)
0.650 (16.51)
0.180 (4.57)
0.165 (4.19)
0.500 (12.70)
REF.
0.156 (3.96)
0.145 (3.68)
PIN 1
0.695 (17.65)
0.685 (17.40)
0.050 REF.
(1.27)
0.655 (16.64)
0.650 (16.51)
0.500
(12.70)REF.
0.021 (0.63)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.630 (16.00)
0.590 (14.99)
0.011 (0.28)
0.009 (0.23)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
38
3926 ILL F29.2
X5114
PACKAGING INFORMATION
48-LEAD THIN QUAD FLAT PACK (TQFP) PACKAGE TYPE L
He
E
L1
D
Hd
GAGE PLANE 0.25
L
e
b
A2
7°±0°
DIM
C
MAX
MIN
MAX
A1
A2
0.05
0.15
0.002
0.006
1.35
1.45
0.53
0.057
b
0.17
0.27
0.007
0.011
c
0.090
0.200
0.004
0.008
D
7.0 BSC
0.273 BSC
E
7.0 BSC
0.273 BSC
e
0.5 BSC
0.02 BSC
Hd
9.0 BSC
0.35 BSC
He
9.0 BSC
0.35 BSC
L
L1
39
INCHES
MIN
A1
NOTES:
1. GAGE PLANE DIMENSION IS IN MM.
2. LEAD COPLANARITY SHALL BE 0.10MM [0.004] MAXIMUM.
3. MOLD FLASH NOT INCLUDED IN DIMENSIONS
MILLIMETERS
0.45
0.75
1.00 TYP
0.018
0.030
0.039 TYP
7052 FM 23
X5114
ORDERING INFORMATION
X5114
X
X
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
L = 48-Lead TQFP
J = 44-Lead PLCC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
40