TA8552AFN TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA8552AFN PLL Data Synchronizer For DAT Streamer The TA8552AFN is PLL data synchronizer for digital audio tape (DAT) strteamer, digital data storage (DDS). Features · The TA8552AFN incorporates edge detector, data synchronizer, and latch for data separator. Also the TA8552AFN is available to correspond to ×1, ×2 and ×3 of data transfer rates by adjusting external devices. · The data synchronizer is avalable to correspond to ±7% variation of data transfer rate. · By employing full differential signal processing in PLL loop, the TA8552AFN eliminates the influence of external noise. Fast & stable locking is realized by switching between the frequency detective mode and the phase detective mode. · Operating power supply voltage range: 4.5V to 5.5V · Small package; SSOP30−P−300−0.65 Weight: 0.17g (typ.) Pin Connectoion Top view Handle with care to prevent devices from deterioration by static electricity. 1 NC 1 30 COB RVCO1 2 29 COA AGND2 3 28 AGND1 CVCO1 4 27 RCP2 RVCO2 5 26 RCP1 CVCO2 6 25 AVCC1 AVCC2 7 24 DETSEL TMON1 8 23 TSTCLK TMON2 9 22 DVCC3 XTMON2 10 21 PBDT V TTLO 11 20 PBCK MODESEL 12 19 DGND3 TSTCPMP 13 18 TSTSEL2 RD 14 17 REFCLK XRD 15 16 TSTSEL1 2002-10-30 TA8552AFN Block Diagram DETSEL MODESEL RCP1 RCP2 REFCLK RD XRD Frequency detecter Edge detecter ECL / TTL D PBCK Charge − pump 1 / 2 counter VCO Phase detecter Selecter Delay (2) COA Detecter selector COB Q PBDT TSTCLK TSTSEL1 RVCO1 RVCO2 CVCO1 CVCO2 TSTSEL2 2 2002-10-30 TA8552AFN Pin Function Pin No. Pin Name 1 NC 2 Function In / Out NC terminal. (open at normal use) ― RVCO1 VCO adjusting terminal. Connect an external resistor (RVCO1) between VCC. ― 3 AGND2 Analog ground for VCO. ― 4 CVCO1 VCO adjusting terminal. Connect a capacitor (CVCO) between this pin and pin6. ― 5 RVCO2 VCO adjusting terminal. Connect an external resistor (RVCO2) between VCC. ― 6 CVCO2 VCO adjusting terminal. Connect a capacitor (CVCO) between this pin and pin4. ― 7 AVCC2 Analog power supply voltage for VCO. ― 8 TMON1 NC terminal (open at normal use) ― 9 TMON2 NC terminal (open at normal use) ― 10 XTMON2 NC terminal (open at normal use) ― 11 V_TTLO Input terminal for TTL voh (high voltage level of pin20, and pin21 output) limitting. ― 12 MODESEL Input terminal for switching the normal mode and the serching mode. (H: Normal mode, L: Serching mode) 13 TSTCPMP NC terminal. (open at normal use.) 14 RD 15 XRD 16 TSTSEL1 Input terminal for test mode selecting. (refer the chapter of "test mode") 17 REFCLK Reference clock input of frequency synchronizer. 18 TSTSEL2 Input terminal for test mode selecting. (refer the chapter of "test mode") ― 19 DGND3 Digital ground for TTL output. ― 20 PBCK Output terminal of data latch clock. TTL-out 21 PBDT Output terminal of data latch. TTL-out 22 DVCC3 Digital power supply voltage for TTL output. ― 23 TSTCLK Input terminal of ×1 / 2 vco test clock. (short with VCC at mormal use.) ― 24 DETSEL Input terminal for switching the frequency detective mode and the phase detective mode. (L : The frequency detective mode H : The phase detective mode.) 25 AVCC1 Analog power supply voltage. TTL-in ― Input terminal of data (normal phase) ECL-in or TTL-in Input terminal of data (reverse phase). (this terminal is active when TSTSEL1 = L and TSTSEL2 = H. Otherelse, short with VCC.) (ECL-in) ― TTL-in TTL-in ― 3 2002-10-30 TA8552AFN Pin No. Pin Name Function In / Out 26 RCP1 Adjusting terminal of charge pump at normal mode. Connect an external resistor (Rcp1) between GND. ― 27 RCP2 Adjusting terminal of charge pump at normal mode. Connect an external resistor (Rcp2) between GND. ― 28 AGND1 Analog ground ― 29 COA Connecting terminal of loop filter. Connect an external loop filter between this pin and 30pin. ― 30 COB Connecting terminal of loop filter. Connect an external loop filter between this pin and 29pin. ― Absolute Maximum Rating (Ta = 27°C) Parameter Symbol Rating Unit AVCC 7 V VIN -0.3~VCC+0.3 V VOUT -0.3~VCC+0.3 V Tstg −55~150 °C Supply voltage Input voltage Output voltage Storage temperature Recommended Operating Condition Parameter Supply voltage Operation temperature Symbol Condition Min. Typ. Max. AVCC ― Topr ― Unit 4.5 5 5.5 V -5 ― 75 °C Max. Unit 65 mA Power Supply (unless otherwise specifide, Ta = 27°C, VCC = 5.0V) Parameter Supply current Symbol Condition IPLCC TSTSEL1 = H, TSTSEL2 = L DETSEL = L, MODSEL = H 4 Min. Typ. 2002-10-30 TA8552AFN Electrical Characteristic (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Symbol Test Circuit High level input voltage (1) VIH ― Low level input voltage (1) VIL High level input current (1) Low level input current (1) Parameter Test Condition Min. Typ. Max. Unit TTL input pins 2.0 ― ― V ― TTL input pins ― ― 0.4 V IIH ― TTL input pins ― ― 20 µA IIL ― TTL input pins ― ― -360 µA ― ― V High level input voltage (2) VIHE ― ECL input pins VCC -1.0 Low level input voltage (2) VILE ― ECL input pins ― ― VCC -1.5 V High level input current (2) IIHE ― ECL input pins ― ― 2.0 mA Low level input current (2) IILE ― ECL input pins ― ― 1.6 mA High level output voltage (1) VOH ― TTL output pins IOH = 400µA VTTLO -0.2 VTTLO +0.2 V Low level output voltage (1) VOL ― TTL output pins IOL = 4mA ― ― 1.0 V Output rise time (1) TOR ― TTL output pins 1.5V to 3.5V CL≤30pF *1 ― ― 5 ns Output fall time (1) TOF ― TTL output pins 3.5V to 1.5V CL≤30pF *1 ― ― 5 ns VTTLO ― 2.7 ― 3.3 V Min. Typ. Max. Unit Input voltage range to VTTLO terminal *1; Design guaranteed value. Charge Pump (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Symbol Range of output current setting ICP Accuracy of output current setting Iacu Leak current Ireak Test Circuit Condition ― At normal mode *1 30 ― ― ― At serching mode *2 ― ― 800 ― At normal mode -6 ― +6 ― At serching mode -8 ― +8 Between COA pin and COB pin, at high impedance -3.5 +3.5 µA % µA *1; Output current is set by an external resistor (Rcp1), as following; 2×1.3 / Rcp1 = (output current at normal mode). *2; Output current is set by external resisters (Rcp1, Rcp2), as following; 2×1.3 / Rcp1+8×1.3 / Rcp2 = (output current at search mode). (Note) The above values are all at open loop. 5 2002-10-30 TA8552AFN VCO (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Input voltage of VCO (V (COB -COA)) Symbol Test Circuit VVCO ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF fVCO = 28.224MHz *1 *1 Condition Min. Upper limitation of VCO frequency fmax ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF V (COB -COA) = 0.6V Lower limitation of VCO frequency fmin ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF V (COB -COA) = -0.6V *1 GVCO ― RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF Voltage (COB -COA) Excursion 0.3V to -0.3V *1 tjit ― PBCK pin at ×3 transfer rate Control gain (F / V) VCO jitter Typ. 0.25 Max. Unit 0.45 V 29.5 MHz 6 23.5 MHz 7.7 MHz / V 300 *2 ps *1; CVCO inclides the package capacitance. *2; Design guaranteed value. (Note) The above values are all at open loop, measured at the PBCK pin Closed Loop (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Symbol Test Circuit VCO jitter in closed loop tjit2N ― VCO jitter in closed loop tjit2S ― Parameter Condition Min. Typ. Max. Unit In search mode lock to REFCLK 0.5 ns In normal mode lock to RD 0.4 ns Values of external parts are (RVCO1 = 3.75 kΩ, RVCO2 = 1.21 kΩ, CVCO = 39pF (including storage capacitor), RCP1 = 8.25k, RCP2 = 30.1k). 6 2002-10-30 TA8552AFN Character Of VCO The connection of input voltage and output frequency of VCO (measured at PBCK after the 1 / 2 frequency counter) is written as following; fvco = 1 × I + I 8×C vco × DV O ofs (Vin>2Vop) I I 1 ( O × Vin + O + Iofs ) 8×C vco ×DV 4Vop 2 (2Vop>Vin> -2Vop) 1 ×I 8×C vco × DV ofs (Vin< -2Vop) Where; Cvco is an external capacitor between 4pin and 6pin, ∆V = 0.35V, Vop = 0.275V, Vin is the input voltage of VCO (differential), IO = 3×1.3 / Rvco1, and lofs = 2×1.3 / Rvco2･ fVCO I0 + IOFS 8 CVCO ∆V I0 + IOFS 2 8 CVCO ∆V IOFS 8 CVCO ∆V − 2 Vop 0 2 Vop VIN So, the gain of VCO is defined as following (at PBCK); I 1 × O 8×Cvco ×DV 4Vop 7 2002-10-30 TA8552AFN And, upper limitation f upper, and lower limitation of VCO frequency f lower is defined as follows; fupper = (IO+Iofs) / 8Cvco ∆V flower =Iofs / 8Cvco ∆V I 0 can be determined by selecting Rvco1, and I ofs can by Rvco2. So, you can independently determine the gain of VCO, upper limitation and lower limitation of VCO frequency by selecting Cvco, Rvco1, and Rvco2･ 【Example】When, Cvco = 22.1pF, Rvco1 = 2.6kΩ, Rvco2 = 2.6 kΩ, Gain of VCO ; 1.3 / (2.6´10 3 )´3 8´22.1´10 -12 ´0.35 ´ 4´0.275 = 22MHz / V Upper limitation of VCO frequency ; 1.3 / (2.6´10 3 )´3 +1.3 / (2.6´10 3 )´2 8´ 22.1´10 -12 ´0.35 = 40.4MHz ; 1.3 / (2.6´10 3 )´ 2 8´ 22.1´10 -12 ´0.35 = 16.2MHz Lower limitation of VCO frequency f 40.4MHz Gain; 22MHz / V 28.224MHz 16.2MHz V − 0.55V 0 8 + 0.55V 2002-10-30 TA8552AFN Function Description: The angular frequency (ωn) and dumping facter (ζ) are adjusted by external devices. The setting procedure is shown as following. The setting conditions to lock PLL inside a constant time; · Data transfer rate: 28.224Mbps (fM = 28.244MHz) · The capturing signal of PLL: The rectangle wave of 14.112MHz (data pattern is 101010...), The term of this data is continuous 180 bits. · The capturing time of PLL: 1 / (14.114×106) ×180 = 12.75×10-6s 12.75×10-6×0.9 = 11.5µs (this 0.9 is a factor of margin.) 【The transfer function of PLL】 Phase comparater θi + Kf − Loop filter VCO Z (s) K0 / s Z (s) CL1 θo 1 / 2 counter RL CL2 1/2 The transfer function (F (S)), the angular frequency (ωn), and the dumping facter (ζ) of the above composition are defined as following (However CL2 is ignored as CL2≪CL1): wn = ( z= K )1/ 2 CL1 RL CL1wn 2 【Calculation of ζ】 The dumping factor (ζ) is set to 0.7 as the most stable response characteristic. Besides ωn t is assumed to set as 6. 9 2002-10-30 TA8552AFN 【Calculation of ωn】 The capturing time of PLL is expected as above 11.5µs. Therefore (ωn) is deternimated as the following: ωn = 6 / (11.5×10-6) = 552krad / s 【Calculation of K0 (VCO control gain)】 K0 is determined as the following; K0 = 40MHz / V = 251.3Mrad / V 【Calculation of Kf (phase detector gain)】 Kf is estimated as the following (the current of charge pump is set as ±50µA.) 1 1 ･ ×50×10-6 = 3.98×10-6(A / rad) 2 2F Kf = The current of charge pump (Ichp) is set by an external resister (Rcp1), connected with Rcp1 (26pin). When "H"level voltage inputs to MODESEL (12pin), Ichp is set as the following: Ichp = 2×1.3 / RCP1→RCP1 = 2×1.3 / Ichp = 2×1.3 / 50×10-6 = 52×103Ω Therefore, when RCP1 is 52kΩ, Ichp is set as ±50µA 【Calculation of external devices of loop-filter】 CL1 = RL = Kf´K 0 3.98´10 -6 ´251.3´10 6 = = 1800 ´ 10 - 6 F 2wn 2´ (522´10 3 )2 2z 2´0.7 = = 1.5 ´ 10 3 W CL1 wn 12 3 1800´10 ´522´10 CL2 = CL1 / 10 = 180pF 10 2002-10-30 TA8552AFN Modesel Switching Function The TA8552AFN has a function to correspond with the high-speed serching mode of DAT streamer. In the searching mode, the data transfer rate will shift with small percentage error. The TA8552AFN is available to solve this problem by extending the lock-in-range (∆ωL). In the serching mode the current of charge pump will be increased to raise the phase detecter gain, then the lock-in-range (∆ωL) will extend. This function is selected by modesel (12pin). (H: Normal mode / L: Searching mode) 【Calculation of the charge pump's current in the searching mode】 The charge pump's current in the searching mode is estimated as the following (the shift rateX of data, transfer is assumed as X = 7% in this example); 6 f ´ X´2p I chp = M ´ 8p = 28.224 ´10 ´0.07 ´2´3.14 ´ 8 ´ 3.14 = 830 ´ 10 - 6 (A) R´K 0 3 1.5´10 ´251.3 ´10 6 When "L" level voltage inputs to modesel (12pin), the charge pump's current (Ichp) increases. In the normal mode, the charge pump's current (Icp1) is set by an external resister (Rcp1). And in the searching mode, another current (Icp2), is set by an external resisiter (Rcp2), adds to Icp1. This (Rcp2) is the resister to be connected with RCP2 (27pin) The additional current (Icp2) is determined by the following: Icp2 = 8×1.3 / Rcp2 Therefore, Rcp2 is estimated as the following: R cp2 = 8´1.3 = 13.3 ´ 10 3 W 6 6 830´10 - 50´10 Modesel function is summarized by the followings Mode Modesel (12pin) Charge pump current Ichp Setting definition Normal Mode High-speed Searghing Mode H L Icp1 Icp1+Icp2 2×1.3 / Rcp1 2×1.3 / Rcp1+8×1.3 / Rcp2 11 2002-10-30 TA8552AFN Timing Chart Of Latch 4.704 MHz, 360 pulse for x1−Speed 9.408 MHz, 360 pulse for x2−Speed 14.112 MHz, 360 pulse for x3−Speed Synk−byte Data D1 D2 D3 D4 D5 D6 D7 D8 D9 RD Locked by PLL Out of edge det. PBCK Out of latch 12 2002-10-30 TA8552AFN (Note) Test Monitor Output Terminal Tstsel Datainput Function 1 2 L L TTL input from 14pin (RD) ― H L TTL input from 14pin (RD) PBCK (20pin) & PBDT (21pin) becomes disable L H ECL input from 14pin (RD) and 15pin (XRD) H H TTL input from 14pin (RD) ― The internal PLL becomes disable, and the external clock from tstclk (23pin) becomes enable as input data signal. (Note) ● We commend the use of this IC under the comdition of ECL input from 14pin (RD) and 15pin (XRD) when (TSTSEL1, TSTSEL2) = (L, H) ● It is possible of the use of TTL input from 14pin (RD) when (TSTSEL1, TSTSEL2) = (L, L) 13 2002-10-30 TA8552AFN Application Diagram RVCO1 VCC 30 COB 2 29 CVCO1 CVCO 22.1pF RUCO1 2.7kΩ GND 3 AGND2 0.1µF RVCO2 RVCO2 VCC 1 2.7kΩ CVCO2 VCC AVCC2 TMON1 TMON2 XMON2 3.3V V H / normal L / search TTL0 XRD TTL in VCC Data in AGND1 GND 5 26 6 25 7 24 8 23 TSTCLK 9 22 10 21 11 20 12 19 14 17 15 16 1500pF RCP1 27 18 RCP2 13.3kΩ COA 4 MODESEL TSTCPMP 13 RD 28 1500pF CL2 NC1 1800pF RL 180pF 0.1µF CL1 1.5kΩ When the data transfer rate is 28.224Mbps, the application diagram is shown below. RCP2 52kΩ RCP1 AVCC1 VCC DETSEL DVCC3 H / phase comparate mode L / frequency comparate mode VCC OUT PBDT OUT PBCK DGND3 GND TSTSEL2 REFCLK TTL in 28.224MHz TSTSEL1 Test set 1 Test set 2 ECL in or Xdata in Data in 14 2002-10-30 TA8552AFN Package Dimensions Weight: 0.17g (typ.) 15 2002-10-30 TA8552AFN RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. 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