NEC UPD161620

PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µ PD161620
432 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM
DESCRIPTION
The µ PD161620 is a TFT-LCD source driver that includes display RAM.
This driver has 432 outputs, a display RAM capacity of 304,128 bits (432 dots x 4 bits x 176 lines) and, can provide a
4,096-color display.
FEATURES
• TFT-LCD driver with on-chip display RAM
• Logic supply voltage: 2.5 to 3.6 V
★ • Driver supply voltage: 3.6 to 5.5 V
• Display RAM: 432 x 4 x 176 bits
★ • Driver outputs: 432 output
• CPU interface: Serial, 4-bit/8-bit parallel interface selectable
★
(Parallel interface requires WAIT control via RDY signal)
• Colors: 4,096 colors/pixel
• On-chip VCOM generator
• On-chip timing generator
• On-chip oscillator
ORDERING INFORMATION
Part Number
Package
µ PD161620
TCP/Chip
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14797EJ3V7PM00 (3rd edition)
Date Published July 2001 NS CP(K)
Printed in Japan
The mark ★ shows the major revised points.
©
2000
µ PD161620
★ 1. BLOCK DIAGRAM
Y1
Y2
Y3
Y431 Y432
Y4
Gray
scale
generator
LCD drive circuit
VRH, V0 to V15
VLH1, VLH2
Decoder
Level shifter (2.7 V
4 or 5 V)
Display data latch
LCD timing control
Display data RAM
(4 x 176 x 144 x 3 bits)
Calibrator
Oscillator
Arbiter
BGR
Remark
2
PS
control
/xxx indicates active low signal.
Preliminary Product Information S14797EJ3V7PM
OSCIN
OSCSEL
Gate
control
VCOM
TEST2 to
TEST5, TESTIN
TEST1, TEST6 to
TEST9, TESTOUT
RS
/CS1
CS2
/RD(E)
/WR(R, /W)
D7(SI)
D6(SCL)
D5(SO)
D0 to D4
PSX0
PSX1
/RESET
C86
RDY
IP0 to IP3
OP0 to OP3
DVSS
VS
DVCC1
VSS
VCC1
VCC2
I/O buffer
VCOM
generator
Data
register
VCOUT
VCOMR
BGRIN
Address
decoder /
controller
DCON
RGONP
VCE
VCD2
VCD11
VCD12
LPMG,LPMP
Command
decoder
GCLK
GSTB
GOE1
GOE2
RGONG
TEST10
Internal
timing
generator
µ PD161620
★ 2. PIN CONFIGURATION (PAD LAYOUT)
Chip size: 16800 x 3060 µm2
Bump size (output): 33 x 60 µm2
Bump size (input & dummy): 87 x 60 µm2
Alignment Mark
X: –7806.06 Y: 858.24
X: 7783.83 Y: –914.43
389
50
338 outputs
390
49
Y(-
Chip surface
(Bump side)
Output side
Output side
47 outputs
Output side
X(+
Input side
438
552
60 um
439
72 um
1
72 um
60 um
72 um
72 um
Preliminary Product Information S14797EJ3V7PM
3
µ PD161620
★
Table 2–1. Pad Layout (1/4)
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
4
Pad name
DUMMY
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
DUMMY
DUMMY
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
X[µm]
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8287.08
8166
8088
8040
7992
7944
7896
7848
7800
7752
7704
7656
7608
7560
7512
7464
7416
7368
7320
7272
7224
7176
7128
7080
7032
6984
6936
6888
6840
6792
6744
6696
Y[µm]
-1182
-1104
-1056
-1008
-960
-912
-864
-816
-768
-720
-672
-624
-576
-528
-480
-432
-384
-336
-288
-240
-192
-144
-96
-48
0
48
96
144
192
240
288
336
384
432
480
528
576
624
672
720
768
816
864
912
960
1008
1056
1104
1182
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
Pad No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Pad name
Y78
Y79
Y80
Y81
Y82
Y83
Y84
Y85
Y86
Y87
Y88
Y89
Y90
Y91
Y92
Y93
Y94
Y95
Y96
Y97
Y98
Y99
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Y118
Y119
Y120
Y121
Y122
Y123
Y124
Y125
Y126
Y127
Y128
Y129
Y130
Y131
Y132
Y133
Y134
Y135
Y136
Y137
Y138
Y139
Y140
Y141
Y142
Y143
Y144
Y145
Y146
Y147
Y148
Y149
Y150
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Preliminary Product Information S14797EJ3V7PM
X[µm]
Y[µm]
6648
6600
6552
6504
6456
6408
6360
6312
6264
6216
6168
6120
6072
6024
5976
5928
5880
5832
5784
5736
5688
5640
5592
5544
5496
5448
5400
5352
5304
5256
5208
5160
5112
5064
5016
4968
4920
4872
4824
4776
4728
4680
4632
4584
4536
4488
4440
4392
4344
4296
4248
4200
4152
4104
4056
4008
3960
3912
3864
3816
3768
3720
3672
3624
3576
3528
3480
3432
3384
3336
3288
3240
3192
3144
3096
3048
3000
2952
2904
2856
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
µ PD161620
★
Table 2–1. Pad Layout (2/4)
Pad No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pad name
Y158
Y159
Y160
Y161
Y162
Y163
Y164
Y165
Y166
Y167
Y168
Y169
Y170
Y171
Y172
Y173
Y174
Y175
Y176
Y177
Y178
Y179
Y180
Y181
Y182
Y183
Y184
Y185
Y186
Y187
Y188
Y189
Y190
Y191
Y192
Y193
Y194
Y195
Y196
Y197
Y198
Y199
Y200
Y201
Y202
Y203
Y204
Y205
Y206
Y207
Y208
Y209
Y210
Y211
Y212
Y213
Y214
Y215
Y216
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y233
Y234
Y235
Y236
Y237
X[µm]
Y[µm]
2808
2760
2712
2664
2616
2568
2520
2472
2424
2376
2328
2280
2232
2184
2136
2088
2040
1992
1944
1896
1848
1800
1752
1704
1656
1608
1560
1512
1464
1416
1368
1320
1272
1224
1176
1128
1080
1032
984
936
888
840
792
744
696
648
600
552
504
456
408
360
312
264
216
168
120
72
24
-24
-72
-120
-168
-216
-264
-312
-360
-408
-456
-504
-552
-600
-648
-696
-744
-792
-840
-888
-936
-984
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
Pad No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
Pad name
Y238
Y239
Y240
Y241
Y242
Y243
Y244
Y245
Y246
Y247
Y248
Y249
Y250
Y251
Y252
Y253
Y254
Y255
Y256
Y257
Y258
Y259
Y260
Y261
Y262
Y263
Y264
Y265
Y266
Y267
Y268
Y269
Y270
Y271
Y272
Y273
Y274
Y275
Y276
Y277
Y278
Y279
Y280
Y281
Y282
Y283
Y284
Y285
Y286
Y287
Y288
Y289
Y290
Y291
Y292
Y293
Y294
Y295
Y296
Y297
Y298
Y299
Y300
Y301
Y302
Y303
Y304
Y305
Y306
Y307
Y308
Y309
Y310
Y311
Y312
Y313
Y314
Y315
Y316
Y317
Preliminary Product Information S14797EJ3V7PM
X[µm]
Y[µm]
-1032
-1080
-1128
-1176
-1224
-1272
-1320
-1368
-1416
-1464
-1512
-1560
-1608
-1656
-1704
-1752
-1800
-1848
-1896
-1944
-1992
-2040
-2088
-2136
-2184
-2232
-2280
-2328
-2376
-2424
-2472
-2520
-2568
-2616
-2664
-2712
-2760
-2808
-2856
-2904
-2952
-3000
-3048
-3096
-3144
-3192
-3240
-3288
-3336
-3384
-3432
-3480
-3528
-3576
-3624
-3672
-3720
-3768
-3816
-3864
-3912
-3960
-4008
-4056
-4104
-4152
-4200
-4248
-4296
-4344
-4392
-4440
-4488
-4536
-4584
-4632
-4680
-4728
-4776
-4824
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
5
µ PD161620
★
Table 2–1. Pad Layout (3/4)
Pad No.
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
6
Pad name
Y318
Y319
Y320
Y321
Y322
Y323
Y324
Y325
Y326
Y327
Y328
Y329
Y330
Y331
Y332
Y333
Y334
Y335
Y336
Y337
Y338
Y339
Y340
Y341
Y342
Y343
Y344
Y345
Y346
Y347
Y348
Y349
Y350
Y351
Y352
Y353
Y354
Y355
Y356
Y357
Y358
Y359
Y360
Y361
Y362
Y363
Y364
Y365
Y366
Y367
Y368
Y369
Y370
Y371
Y372
Y373
Y374
Y375
Y376
Y377
Y378
Y379
Y380
Y381
Y382
Y383
Y384
Y385
DUMMY
DUMMY
Y386
Y387
Y388
Y389
Y390
Y391
Y392
Y393
Y394
Y395
X[µm]
-4872
-4920
-4968
-5016
-5064
-5112
-5160
-5208
-5256
-5304
-5352
-5400
-5448
-5496
-5544
-5592
-5640
-5688
-5736
-5784
-5832
-5880
-5928
-5976
-6024
-6072
-6120
-6168
-6216
-6264
-6312
-6360
-6408
-6456
-6504
-6552
-6600
-6648
-6696
-6744
-6792
-6840
-6888
-6936
-6984
-7032
-7080
-7128
-7176
-7224
-7272
-7320
-7368
-7416
-7464
-7512
-7560
-7608
-7656
-7704
-7752
-7800
-7848
-7896
-7944
-7992
-8040
-8088
-8166
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
Y[µm]
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1417.08
1182
1104
1056
1008
960
912
864
816
768
720
672
Pad No.
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
Pad name
Y396
Y397
Y398
Y399
Y400
Y401
Y402
Y403
Y404
Y405
Y406
Y407
Y408
Y409
Y410
Y411
Y412
Y413
Y414
Y415
Y416
Y417
Y418
Y419
Y420
Y421
Y422
Y423
Y424
Y425
Y426
Y427
Y428
Y429
Y430
Y431
Y432
DUMMY
DUMMY
DUMMY
TEST10
LPMG
RGONG
GOE2
GOE1
GCLK
GSTB
DVCC1
IP3
IP2
IP1
IP0
DVSS
OP3
OP2
OP1
OP0
DUMMY
VRL2
VRL1
V15
V14
V13
V12
V11
V10
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
VRH
DUMMY
TEST6
DVCC1
Preliminary Product Information S14797EJ3V7PM
X[µm]
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8287.08
-8204.46
-8060.46
-7916.46
-7772.46
-7628.46
-7484.46
-7340.46
-7196.46
-7052.46
-6908.46
-6764.46
-6620.46
-6476.46
-6332.46
-6188.46
-6044.46
-5900.46
-5756.46
-5612.46
-5468.46
-5324.46
-5180.46
-5036.46
-4892.46
-4748.46
-4604.46
-4460.46
-4316.46
-4172.46
-4028.46
-3884.46
-3740.46
-3596.46
-3452.46
-3308.46
-3164.46
-3020.46
-2876.46
-2732.46
-2588.46
-2444.46
-2300.46
Y[µm]
624
576
528
480
432
384
336
288
240
192
144
96
48
0
-48
-96
-144
-192
-240
-288
-336
-384
-432
-480
-528
-576
-624
-672
-720
-768
-816
-864
-912
-960
-1008
-1056
-1104
-1182
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
µ PD161620
★
Table 2–1. Pad Layout (4/4)
Pad No.
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
Pad name
DVSS
BGRIN
VCOMR
VS
VS
VS
VSS
VSS
VSS
VCC1
VCC1
VCC1
DUMMY
DUMMY
DUMMY
VCOM
VCOUT
DUMMY
DCON
RGONP
LPMP
VCD11
VCD12
VCD2
VCE
TESTOUT
TESTIN
DUMMY
VCC2
VCC2
VCC2
CS2
DUMMY
/RD(E)
/WR(R,/W)
RS
D0
D1
D2
D3
D4
D5(SO)
D6(SCL)
D7(SI)
/CS1
/RESET
RDY
OSCIN
DVSS
DUMMY
DVCC1
PSX1
DVSS
PSX0
DVCC1
C86
DVSS
OSCSEL
DVCC1
TEST5
TEST4
DVSS
TEST3
DVCC1
TEST2
DVSS
TEST1
TEST9
TEST8
TEST7
DUMMY
DUMMY
X[µm]
Y[µm]
-2156.46
-2012.46
-1868.46
-1724.46
-1580.46
-1436.46
-1292.46
-1148.46
-1004.46
-860.46
-716.46
-572.46
-428.46
-284.46
-140.46
3.54
147.54
291.54
435.54
579.54
723.54
867.54
1011.54
1155.54
1299.54
1443.54
1587.54
1731.54
1875.54
2019.54
2163.54
2307.54
2451.54
2595.54
2739.54
2883.54
3027.54
3171.54
3315.54
3459.54
3603.54
3747.54
3891.54
4035.54
4179.54
4323.54
4467.54
4611.54
4755.54
4899.54
5043.54
5187.54
5331.54
5475.54
5619.54
5763.54
5907.54
6051.54
6195.54
6339.54
6483.54
6627.54
6771.54
6915.54
7059.54
7203.54
7347.54
7491.54
7779.54
7779.54
7923.54
8204.46
Preliminary Product Information S14797EJ3V7PM
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
-1417.08
7
µ PD161620
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Symbol
Pin Name
Pad No.
I/O
-
Function
VCC1
Logic power supply pin
490 to 492
Power supply pin for logic circuit
VCC2
I/O power supply pin
509 to 511
-
Power supply pin for I/O buffer
VS
Driver power supply pin 484 to 486
-
Power supply pin for driver circuit
VSS
Ground pin
Ground pin for logic and driver circuits
487 to 489
-
Power supply for
γ-curve correction
476 to 461
477, 460, 459
-
The µ PD161620 includes power supplies and resistors for the γ-curve,
so if the characteristics of the γ-curve and LCD panel in the µ PD161620
match, leave V0 to V15, VRH, VRL1, VRL2 open.
If some kind of correction is required, adjust the γ-curve by connecting
resistors between the V0 to V15, VRH, VRL1, VRL2 pins (see 5.9 γ -Curve
Correction Power Supply Circuit for Cases of Unbalanced Driving).
★ DVCC1
Mode setting pull-up
power-supply pin
448,480,531,
535,539,544
-
Pull-up power-supply pin for mode setting
★ DVSS
Mode setting pull-down 453,481,529,
power-supply pin
533,537,542,
546
-
Pull-down power-supply pin for mode setting
★ V0 to V15
VRH
VRL1, VRL2
3.2 Logic System Pins
Symbol
Pin Name
(1/3)
Pad No.
PSX0, PSX1 CPU interface selection 534, 532
/CS1,
Chip select
CS2
525,
512
I/O
Function
Input These pins are used to select the CPU interface mode.
PSX0 = H: 8-bit parallel interface
PSX0 = L: 4-bit parallel interface
PSX1 = H: Parallel interface
PSX1 = L: Serial interface
Input This pin is used for chip select signals. When /CS1 = L (CS2 = H),
the chip is active and can perform data input/output operations including
command and data I/O.
/RD
Read (enable)
514
(E)
Input When i80 series parallel data transfer (/RD) has been selected, the
signal at this pin is used to enable read operations. Data is output to the
data bus only when this pin is low.
When M68 series parallel data transfer (E) has been selected, the signal
at this pin is used to enable read/write operations.
★
/WR
Write(read/write)
515
(R, /W)
Input When i80 series parallel data transfer (/WR) has been selected, the
signal at this pin is used to enable write operations. Data is written at
the rising edge of this signal.
When M68 series parallel data transfer (R, /W) and serial data has been
selected, this pin is used to determine the direction of data transfer.
L: Write
H: Read
C86
Select interface
536
Input This pin is used to switch between interface modes (i80 series CPU or
M68 series CPU).
L: Selects i80 series CPU mode
H: Selects M68 series CPU mode
8
Preliminary Product Information S14797EJ3V7PM
µ PD161620
(2/3)
Symbol
★ RDY
Pin Name
Ready signal
Pad No.
527
I/O
Function
Output This pin is the ready signal output. When in 4-bit or 8-bit parallel mode,
connect this pin to external WAIT pin of the CPU. When in serial mode,
this pin is not used, so leave it open.
★ D0 to D7
Data bus
517 to 524
I/O
These pins comprise 8-bit bi-directional data.
(SI)
(Serial data Input)
When the serial interface has been selected (PSX1 = L ), D7 functions as a
(SO)
(Serial data output)
serial data input pin (SI), D6 functions as a serial clock input pin (SCL),
(SCL)
(Serial clock)
and D5 functions as a serial data output pin (SO). In either case, pins D0
to D4 are in high impedance mode.
When the chip is not selected, D0 to D7 are in high impedance mode.
★ RS
Index register/data,
516
Input
command selection
When parallel data transfer has been selected, this pin is usually
connected to the LSB of the standard CPU address bus and is used to
distinguish between data from index registers and data/commands.
RS = H: Indicates that data from D0 to D7 is data/command
RS = L: Indicates that data from D0 to D7 is index register contents
Also, when serial data transfer is selected, the level of the RS pin is
fetched at the rising edge of the eighth clock of the serial clock and
whether the data is index register contents or data/command is
distinguished.
RS = H: Indicates that the data input to SI is data/command.
RS= L: Indicates that the data input to SI is index register contents.
TESTOUT
Test output
506
/RESET
Reset
526
Output This test output pin is used when the IC is in test mode, otherwise, it is left
unconnected.
Input
When /RESET is low, an internal reset is performed. The reset operation
is executed at the /RESET signal level. Be sure to perform reset via this
pin at power application.
★ TEST4,
Test
540,
TEST5
541
TEST2,
545,
TEST3
543
★ IP0 to IP3
Input port
452 to 449
Input
Input low level.
Input
This is a general-purpose input port. The status of these pins (H or L) can
be read via a command.
Because this is CMOS input, do not leave these pins open.
★ OP0 to OP3
Output port
457 to 459
Output This is a general-purpose output port. The status of these pins (H or L)
can be write via a command.
★ TEST6
★ TEST1
★ TEST10
★ LPMG
Test
479
Output Leave open.
547
441
Low power mode signal 442
Connect this pin to the SB pin of the gate driver.
Output This is an output pin for low power mode (for the gate driver).
Connect this pin to the LPM pin of the gate driver.
★ LPMP
501
This is an output pin for the low power mode (for the power-supply IC).
Connect this pin to the LPM pin of the power-supply IC.
★ GOE1
OE1 output for gate
445
driver
Output This pin is an output pin for the low power mode (for the OE1).
Connect to the OE1 pin of the gate driver.
For the signal output timing, refer to 5.4 Display Timing Generator.
★ GOE2
OE2 output for gate
driver
444
Output This pin is the OE2 output for the gate driver.
Connect to the OE2 pin of the gate driver.
For the signal output timing, refer to 5.4 Display Timing Generator.
Preliminary Product Information S14797EJ3V7PM
9
µ PD161620
(3/3)
Symbol
★
GSTB
Pin Name
STB output for
Pad No.
447
I/O
Function
Output This pin is the STB output for the gate driver.
gate driver
Connect to the STVR or STVL pin of the gate driver.
For the signal output timing, refer to 5.4 Display Timing Generator.
GCLK
CLK output for gate
446
Output This pin is the CLK output for the gate driver.
driver
★
DCON
DC/DC converter
★
RGONP
★
RGONG
Connect this pin to the CLK pin of the gate driver.
499
Output DC/DC converter ON/OFF control of power supply IC
Regulator control
500
Output Regulator ON/OFF control of power supply IC
Regulator control
443
Output Regulator ON/OFF control of gate driver IC
control
Connect this pinto the DCON pin of the power-supply IC.
Connect this pin to the RGONP pin of the power-supply IC.
Connect this pin to the RGONG pin of the gate driver.
★
VCD11, VCD12
VDD1 booster select
502, 503
Output Control signal to select x4/x5/x6/x7 booster of power supply IC for VDD1.
Connect this pin to the VCD11 and VCD12 pins of the power-supply IC.
★
VCD2
VDD2 booster select
504
Output Control signal to select x2/x3 booster of power supply IC for VDD2.
Connect this pin to the VCD2 pin of the power-supply IC.
★
VCE
VO level select
505
Output Signal for selecting the level of the power supply IC booster voltage, to be
used for the maximum voltage of VO. Selects that the booster voltage level
is either the same level as VDD1 or a multiple of minus 1.
Connect this pin to the VCE pin of the power-supply IC.
★
TEST7
★
TEST8
★
TEST9
★
OSCIN
Test
Oscillation signal pins
550
I/O
549
I/O
548
I/O
528
Input
Leave open.
This pin is for oscillation signal input.
OSCIN = H: Input oscillation signal
OSCIN = L: This pin is left open.
OSCSEL
Oscillation signal
538
Input
This pin is the oscillation signal select. When an external oscillation circuit
is used, set this pin to H. When an internal oscillation circuit is used, set
select
this pin to L.
★ BGRIN
External-power-supply
482
Input
★ VCOMR
VCOM setting resistor
483
Input
connection pin
★ TESTIN
Test input pins
This is an external-power-supply input pin for VCOM.
For more detail, refer to 5.5 Common Adjustment Circuit.
connection pin
Connects an external resistor for VCOM setting.
For more detail, refer to 5.5 Common Adjustment Circuit.
507
Input
These pins are used to set a test mode for the IC.
Normally, this setting is open.
10
Preliminary Product Information S14797EJ3V7PM
µ PD161620
3.3 Driver-Related Pins
Symbol
Y1 to Y432
Pin Name
Source output
Pad No.
2 to 48, 51 to 388,
I/O
Function
Output Source output pins
391 to 519
★ VCOM
COM center voltage
514
Output This pin is the common center voltage adjustment output.
adjustment
★ VCOUT
Center rectangle
For more detail, refer to 5.5 Common Adjustment Circuit.
515
Output This pin is the center rectangle signal output (4 Vp-p or 5 Vp-p) for
signal output
common modulation.
For more detail, refer to 5.5 Common Adjustment Circuit.
DUMMY
Dummy pin
1, 49, 50, 389, 390,
Dummy pin
438 to 441, 449,
477 to 480,
498 to 500, 524,
541, 546 to 552
Preliminary Product Information S14797EJ3V7PM
11
µ PD161620
★ 4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit types of each pin and recommended connection of unused pins are described below.
I/O
Recommended Connection of Unused Pins
Power
supply
Pin Name
Input Type
PSX0, PSX1
Schmitt trigger
Input
VCC1
Mode setting pinNote
CS2
Filter
Input
VCC2
Connect to VCC2
/RD(E)
Filter
Input
VCC2
Connect to VCC2
(when i80 series interface)
C86
Schmitt trigger
Input
VCC1
Mode setting pinNote
RDY
-
Output
VCC2
-
Leave open
D0 to D4
Filter
I/O
VCC2
-
Leave open
D5 (SO)
Filter
I/O
VCC2
-
D6 (SCL)
Filter
I/O
VCC2
-
D7 (SI)
Filter
VCC2
-
TESTOUT
-
I/O
Output
VCC1
Leave open
Parallel Interface
/RESET
Filter
Input
VCC2
Always reset on power application
IP0 to IP3
Schmitt trigger
Input
VCC1
Connect to VCC1 or VSS1.
OP0 to OP3
-
Output
VCC1
Leave open
TEST10
-
Output
VCC1
Leave open
LPMG, LPMP
-
Output
VCC1
Leave open
GOE1
-
Output
VCC1
Always connect to the gate driver
GOE2
-
Output
VCC1
Always connect to the gate driver
GSTB
-
Output
VCC1
Always connect to the gate driver
GCLK
-
Output
VCC1
Always connect to the gate driver
DCON
-
Output
VCC1
Always connect to the power IC
RGONP
-
Output
VCC1
Always connect to the power IC
RGONG
-
Output
VCC1
Always connect to the gate driver
VCD11, VCD12
-
Output
VCC1
Always connect to the power IC
VCD2
-
Output
VCC1
Always connect to the power IC
VCE
-
Output
VCC1
Always connect to the power IC
TEST1
CMOS
Output
VCC1
Leave open
TEST2
CMOS
Input
VCC1
Connect to VSS
TEST3
CMOS
Input
VCC1
Connect to VSS
TEST4
CMOS
Input
VCC1
Connect to VSS
TEST5
CMOS
VCC1
Connect to VSS
TEST6
CMOS
Input
Output
VCC1
Leave open
TEST7
CMOS
Output
VCC1
Leave open
TEST8
CMOS
Output
VCC1
Leave open
TEST9
CMOS
Output
VCC1
Leave open
OSCIN
CMOS
Input
VCC2
Leave open (in OSCSEL = L mode)
Schmitt trigger
Input
VCC1
Mode setting pinNote
BGRIN
-
Input
VS
Connect to VSS (in BGRS = L mode)
VCOMR
-
Input
VS
Connect to VSS
VCOM
-
Output
VS
Leave open
-
Output
VS
Leave open
OSCSEL
VCOUT
Note Connect to VCC1 or VSS, depending on the mode selected.
12
Preliminary Product Information S14797EJ3V7PM
Serial Interface
Connect to VCC2 or VSS
Connect to VCC1 or VSSNote
µ PD161620
5. DESCRIPTION OF FUNCTIONS
5.1 CPU interface
5.1.1 Selection of interface type
The µ PD161620 chip transfers data using an 8-bit bidirectional data bus (D7 to D0), 4-bit bi-directional data bus (D7
★
to D4) or a serial data input (SI) or a serial date output (SO). Setting the polarity of the PSX0-1 pins as either H (high)
or L (low) enables the selections shown in Table 5–1 below.
Table 5–1.
★
PSX1
PSX0
H
H
H
L
L
X Note2
/CS1
RDY
RS
/RD
(E)
/WR
(R, /W)
C86
D7
D6
D5
D4
D3 to D0
8-bit
parallel
/CS1
RDY
RS
/RD
(E)
/WR
(R, /W)
C86
D7
D6
D5
D4
D3 to D0
4-bit
parallel
/CS1
RDY
RS
/RD
(E)
/WR
(R, /W)
C86
D7
D6
D5
D4
Hi-ZNote1
serialNote3
/CS1
RS
Note2
/WR
(R, /W)
Note2
SI
SCL
SO
Hi-ZNote1
Hi-ZNote1
Mode
Hi-ZNote1
★
Notes 1. Hi-Z: High impedance
2. X: Don’t care (H or L)
3. In serial mode, only commands can be read. Internal RAM data cannot be read.
★
5.1.2 Selection of data transfer mode
In the µ PD161620, when the 8-bit parallel interface and serial interface are selected, there are tow types of modes
to transfer data to display RAM. The mode can be selected as follows with the DTX command.
In the 1-pixel/2-byte mode, 1 pixel of data is written at one time to the internal RAM each time 2 bytes of data are
transferred. If only 1 byte of data has been transferred, writing to the internal RAM is not possible. Similarly, in the 2pixel/3-byte mode, 2 pixels of data are written at one time to the internal RAM each time 3 bytes of data are
transferred. Execute data transfer taking into consideration the above.
Table 5–2.
DTX
★
Mode
1
1-pixel / 2-byte
0
2-pixel / 3-byte
Caution In the 4-bit parallel mode, the DTXX command is disabled. One pixel gets written by transferring 4
bits of data 3 times. The transfer order and relationship between command data and display data are
as follows.
<When transferring command data>
First 4 -bit transfer = Higher 4 bits of command data
Second 4-bit transfer = Lower 4 bits of command data
<When transferring display data>
First 4-bit transfer = Corresponds to display data D11 to D8
Second 4-bit transfer = Corresponds to display data D7 to D4
Third 4-bit transfer = Corresponds to display data D3 to D0
Preliminary Product Information S14797EJ3V7PM
13
µ PD161620
Figure 5–1. Correspondence Between Data Bus and Display RAM (When DTX = 1)
Data bus side
DB7
DB6
D11
D10
D9
Dot 1
1st byte
DB4 DB3
DB5
D8
D7
DB2
DB1
DB0
DB7
D4
D3
D6
D5
Dot 2
1st pixel
DB6
DB5
D2
D1
Dot 3
2nd byte
DB4 DB3
D0
×
DB2
DB1
DB0
×
×
×
Invalid data
Display RAM side
Figure 5–2. Correspondence Between Data Bus and Display RAM (When DTX = 0)
Data bus side
DB7
DB6
DB5
D11
D10
D9
Dot 1
1st byte
DB4 DB3
D8
D7
DB2
DB1
D6
D5
Dot 2
1st pixel
DB0
DB7
D4
D3
DB6
2nd byte
DB4 DB3
DB5
D2
D1
Dot 3
D0
DB2
D11
DB1
D10
D9
Dot 1
DB0
DB7
D8
D7
DB6
DB5
3rd byte
DB4 DB3
D6
D5
Dot 2
2nd pixel
D4
D3
DB2
DB1
D2
D1
Dot 3
DB0
D0
Display RAM side
5.1.3 Parallel interface
When the parallel interface has been selected (PSX1 = H), setting the C86 pin as either H or L enables a direct
★ connection to an i80 series or M68 series CPU (see table below). When the parallel interface is used, wait control for
the bus is required. To execute wait control, connect the RDY pin to the external WAIT pin of the CPU.
Table 5–3.
C86
Mode
/RD(E)
/WR(R, /W)
H
L
M68 series CPU
E
R, /W
i80 series CPU
/RD
/WR
The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in
the following table.
Table 5–4.
14
Common
M68 series CPU
RS
R, /W
H
H
i80 series CPU
Function
/RD
/WR
H
L
H
L
H
L
Write display data and registers
L
H
L
H
Prohibited
L
L
H
L
Write to control index register
Read display data and registers
Preliminary Product Information S14797EJ3V7PM
µ PD161620
(1) i80 Series Parallel Interface
When i80 series parallel data transfer has been selected, data is written to the µ PD161620 at the rising edge of the
/WR signal. The data is output to the data bus when the /RD signal is L.
Figure 5–3. i80 Series Interface Data Bus Status
/CS1
(CS2 = H)
/WR
/RD
Hi-Z
Hi-Z
Valid data
DBn
Data write
Data read
(2) M68 Series Parallel Interface
When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the
R,/W signal is L. In a data read operation, data is output at the rising edge of the E signal in a period when the R,/W
signal is H. The data bus is released (Hi-Z) at the falling edge of the E signal.
Figure 5–4. M68 Series Interface Data Bus Status (When data read)
/CS1
(CS2 = H)
R,/W
E
Hi-Z
DBn
Hi-Z
Valid data
Preliminary Product Information S14797EJ3V7PM
15
µ PD161620
★ 5.1.4 Serial interface
When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI),
serial data output (SO), and serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to
D0 on the rising edge of the serial clock, via the serial input pin. This data is synchronized on the eighth serial clock's
rising edge and is then converted to parallel data for processing. Also, set /WR = L during write and /WR = H during
read.
Note that in the 1-pixel/2-byte mode, make /CS1 active (/CS1 = L) during transfer of 1pixel of data (2 bytes). Similarly
in the 2-pixel/3-byte mode, make CS1 active (/CS1 = L) during transfer of 2 pixels of data (3 bytes). IF /CS1 = H is set
during data transfer, the data may not be transferred normally.
RS input is used to judge serial input data as display data or command data when RS = H the data is display data
and when RS = L the data is command data. When the chip enters active mode, RS input is read at the rising edge
after every eighth serial clock and is then used to judge the serial input data. The serial interface signal chart is
shown below.
Figure 5–5. Serial Interface Signal Chart
★
CS2 = "H"
/CS1
SI
SCL
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RS
/WR
(When in data writing)
Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.
2. The data read function is disabled during serial interface mode (command register is enabled).
★
3. When using SCL wiring, take care concerning the possible effects of terminating reflection and
noise from external sources. Our recommends checking operation with the actual device.
5.1.5 Chip select
The µ PD161620 has two chip select pins (/CS1 and CS2). The CPU parallel and serial interfaces can be used only
when /CS1 = L and CS2 = H. When the chip select pin is inactive, D0 to D7 are set to high impedance (invalid) and
input of RS, /RD, or /WR is not active. If a serial interface mode has been set, the shift register and counter are both
initialized.
★
Note that when using the serial interface, in the 1-pixel/2-byte mode, /CS1 must be made active (/CS1 =L) during
transfer of 1 pixel of data (2 bytes). Similarly in the 2-pixel/3-byte mode, /CS1 must be made active (/CS1 = L) during
transfer of 2 pixels of data (3 bytes). If /CS1 = H is set during data transfer, the data may not be transferred normally.
However, if the parallel interface is used, transfer is performed normally as long as /CS1 is active only during data
transfer in 1-byte units, regardless of whether the 1-pixel/2-byte mode or the 2-pixel/3-byte mode is selected.
16
Preliminary Product Information S14797EJ3V7PM
µ PD161620
★ 5.1.6 Wait control in parallel interface mode
When the parallel interface mode is selected, wait control for the bus is required. Connect the RDY pin of the
µ PD161620 to the external WAIT pin of the CPU to execute wait control. An example of the connection to the CPU is
described in 10. EXAMPLE of µ PD161620 and CPU CONNECTION.
Note that when serial interface mode is selected, wait control via the RDY signal is not required.
5.2 Display Data RAM
This is the RAM that is used to store the display’s dot data. The RAM configuration is 1,728 bits (144 x 12 bits) x
176 bits. Any specified pixel can be accessed by selecting the corresponding X address and Y address.
Figure 5-6 shows the structure of display data RAM.
Figure 5–6.
D11
D10
D9
D8
D7
Dot 1
D6
D5
D4
Dot 2
D3
D2
D1
D0
Dot 3
One pixel ( = one X address)
5.2.1 X address circuit
As shown in Figure 5–7, the display data RAM’s X address is specified via the X address register. When using the X
address increment mode, the specified X address is incremented by one each time a display data read or write
operation is executed. The CPU is able to continuously access the display data.
Following incrementation up to the final X address, executing a display data read or write operation will cause the Y
address to be incremented, and the X address to return to 000H. For the reset value of the address counter, see
Table 5–6.
It is also possible to invert the relationship between the X address and the source output using the ADX flag of
control register 1, as shown in Figure 5–7.
5.2.2 Column address circuit
When displaying the contents of the display data RAM, the column address corresponds to source output, as is
shown Figure 5–7. As is shown in Table 5–5, the correspondence between the display RAM’s column address and
source output can be inverted using the ADC flag in control register 1 (source driver direction selection flag). This
reduces the constraints on chip layout when assembling the LCD module.
Table 5–5.
Y1
Y2
Æ
Y431
Y432
0
000H
001H
Æ Column address Æ
1AEH
1AFH
1
1AFH
1AEH
Å Column address Å
001H
000H
Source Output
ADC
Preliminary Product Information S14797EJ3V7PM
17
µ PD161620
★ 5.2.3 Y address circuit
As is shown in Figure 5–7, the Y address register is used to specify the display data RAM’s Y address. When using
the Y address increment mode, the specified Y address is incremented by one each time a display data read or write
operation is executed. The CPU is able to continuously access the display data. The Y address is incremented up to
AFH, after which the X address is incremented after each read or write operation and the Y address is set back to 00H.
In the case of the 8-bit parallel interface mode and serial interface mode, only the 1-pixel/2-byte mode can be used
as the transfer mode.
Table 5–6. Counter reset for RAM increment
X-address
Y-address
08FH
AFH
Figure 5–7. µ PD161620 RAM addressing
★
ADM0=L,ADM1=L
Source
output
ADX=0
ADC=0
ADC=1
Y1
Y432
X-address
Column addres
Gate output
R,/L=H
R,/L=L
O176
00H
O2
O175
01H
|
|
|
|
|
|
O87
O90
56H
O88
O89
57H
O89
O90
O88
O87
58H
59H
|
|
|
|
|
|
O175
O176
O2
O1
AEH
AFH
Y3
Y430
Y4
Y429
Y5
Y428
Y6
Y427
000H
000H
001H
002H
003H
001H
004H
005H
D11---D8
D7---D4
D3---D0
D11---D8
D7---D4
D3---D0
Y-address
O1
Y2
Y431
1st Pixel
-----
-----
---
---
---
---
Y427
Y6
Y428
Y5
Y429
Y4
Y430
Y3
Y431
Y2
Y432
Y1
1AAH
08EH
1ABH
1ACH
1ADH
08FH
1AEH
1AFH
D11---D8
D7---D4
D3---D0
D11---D8
D7---D4
D3---D0
2nd Pixel
1st Pixel
2nd Pixel
Display area
ADX=1
Source
output
ADC=0
ADC=1
Y1
Y432
Y2
Y431
1AFH
08FH
1AEH
D11---D8
D7---D4
X-address
Column addr
Gate output
R,/L=H
R,/L=L
Y-address
O1
O176
00H
O2
O175
01H
|
|
|
|
|
|
O87
O90
56H
O88
O89
O89
O88
57H
58H
O90
O87
59H
|
|
|
|
O175
O176
|
O2
O1
|
AEH
AFH
18
2nd Pixel
Y3
Y430
Y4
Y429
Y5
Y428
1ADH
1ACH
08EH
1ABH
Y6
Y427
1AAH
D3---D0
D11---D8
D7---D4
D3---D0
--- ----- ---
Y427
Y6
Y428
Y5
005H
001H
004H
D11---D8
D7---D4
--- ----- ---
1st Pixel
2nd Pixel
Display area
Preliminary Product Information S14797EJ3V7PM
Y429
Y4
Y430
Y3
Y431
Y2
003H
002H
000H
001H
000H
D3---D0
D11---D8
D7---D4
D3---D0
1st Pixel
Y432
Y1
µ PD161620
5.3 Oscillator
The µ PD161620 includes a CR-type oscillator, which generate the display clock. When OSCSEL is L, an internal
oscillator is selected. When OSCSEL is H, the internal oscillator is stopped, making it necessary to input the clock from
an external oscillator.
This oscillator also has a calibration function. The time to select one line is set by the calibration start and stop
commands.
Figure 5–8. Frame Frequency Calibration
Start/Stop
Calibration
command
Register
N-bit
counter
OSC
Internal
clock
The calibration function involves counting the number of oscillation clocks generated between the start and stop
signals and storing that number in a register. The number of oscillation clocks is then continually compared with this
register value in subsequent operations, and the time of the clock number stored in the register is set as 1 line
selection time, and used as the internal reference clock.
Using this function allows the frame frequency to be held at a constant value, even when the oscillation frequency is
irregular.
Figure 5–9. Calibration Function Timing
Calibration start
Calibration stop
tcal (1 line time)
1
2
3
5
4
6
tcal = 1/(fFRAME x n)
fFRAME = Frame frequency
n: Line numbers
7
OSC1
1
2
3
4
OSC2
Preliminary Product Information S14797EJ3V7PM
19
µ PD161620
★
5.4 Display Timing Generator
The display timing generator generates the timing signals for the internal timing of the source driver and for the gate
driver. The output timings for normal operation, for normal operation → standby mode, and for standby mode →
normal operation, are shown below.
★
Figure 5–10. During Normal Operation (during line inversion)
GSTB
Data output
line No.
176
dummy
1
2
3
4
5
175
176
dummy
1
2
GCLK
GOE1
GOE2
Source
output
VCOUT
Gate output
O176
Gate output
O1
Gate output
O2
Internal oscillation
clock
GSTB
GCLK
GOE1
VCOUT
Source output
(Source follower
buffer output)
Gate output
O1
Gate output
O2
1st line
20
Preliminary Product Information S14797EJ3V7PM
2nd line
3
µ PD161620
★
Figure 5–11. Normal Operation → Standby Input (during line inversion)
GSTB
Data output line
No.
176
dummy
1
2
3
4
5
175
176
dummy
standby mode
GCLK
GOE1
GOE2
Source
output
VCOUT
Gate output
O176
Gate output
O1
Gate output
O2
Standby command execution
Display OFF
Internal oscillation
clock
GSTB
GCLK
GOE1
GOE2
VCOUT
Source output
(source follower
buffer output)
Gate output
O1
Gate output
O2
176th line
Dummy line
Preliminary Product Information S14797EJ3V7PM
Standby mode
21
µ PD161620
★
Figure 5–12. Standby → Return to Normal Operation (during line inversion)
GSTB
Data output
line No.
standby mode
1
2
3
175
176
dummy
1
2
GCLK
GOE1
GOE2
Source
output
VCOUT
Gate output
O176
Gate output
O1
Gate output
O2
Internal oscillator clock
GSTB
GCLK
GOE1
VCOUT
Source output
(source follower
buffer output)
Gate output
O1
Gate output
O2
1st line
Standby release
22
Preliminary Product Information S14797EJ3V7PM
2nd line
3
µ PD161620
★
5.5 Common Adjustment Circuit
To generate common output, the center voltage of the common waveform is output from the VCOM pin along with
output of a 0 to VS (V) square waveform from the VCOUT pin. The level of the VCOM output can be adjusted using as
external resistor.
Figure 5–13. Common Adjustment Circuit
Outputs common
center voltage
Internal regulator
output:1.24 TYP. (V)
+
Set with command (D 6
bit of R32 register)
−
BGRIN
VCOMR
R1
V S (V)
0 (V)
VCOM
VCOUT
Output 0 to V S (V)
square wave
C1
R3
Output waveform to common
V S(V)
R2
0 (V)
Output waveform at VCOM
output is V S/2 or lower
The BCOM voltage formulas are shown below.
<When internal power supply is used (D6 of R32 = 0)>
COM voltage = (1+R1/R2) x (VBGR/3)
VBGR = 1.2 V TYP.
<When external power supply is used (D6 of R32 = 1)>
COM voltage = (1+R1/R2) x (VBGRIN/9)
VBGRIN = External supply voltage (voltage input from BGRIN)
<Recommended values for R1, R2, R3, C1>
Use the values listed below as a guideline. The user is responsible for ultimately determining the resistance
values and recommended values based on careful evaluation on actual panels.
R1: 200 kΩ
R2: 51 kΩ to 100 kΩ
R3: 51 kΩ to 100 kΩ
C1: 10 µF
Preliminary Product Information S14797EJ3V7PM
23
µ PD161620
5.6 Square Wave Signal Generation Circuit
★
This circuit generates a common square wave signal. A 0 to VS (V) square wave is output from the BCOUT pin.
5.7 Reference Voltage Generator
The µ PD161620 has a reference voltage generator for the voltage regulator.
24
Preliminary Product Information S14797EJ3V7PM
µ PD161620
★
5.8 γ-Curve Correction Power Supply Circuit for Cases of Unbalanced Driving
The µ PD161620 includes a γ-curve correction power supply circuit for cases of unbalanced driving. If the internal γcurve correction matches the LCD characteristics, no external components are necessary.
Support for unbalanced driving is also provided in this circuit using the resistor between VRL1 to VRL2 shown in the
Figure 5–14.
Figure 5–14. γ-Curve Correction Circuit
★
Negative polarity
Positive polarity
VS
VS
VSS
VSS
VRH
V0
,
V0 (black)
V1
V1
V2
V2
V3
V3
V4
V4
V5
V5
V6
V6
V7
V7
V8
V8
V9
V9
V10
V10
V11
V11
V12
V12
V13
V13
V14
V14
V15
,
V15 (white)
VRL1
VS
VS
VRL2
VSS
VSS
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Preliminary Product Information S14797EJ3V7PM
25
µ PD161620
Table 5–7. γ-Curve Correction Circuit
★
When in VS = 5 V
Resistance(kΩ)
Data
Dn+3
Dn+2
Dn+1
Dn
0H
0
0
0
0
1H
0
0
0
2H
0
0
3H
0
4H
Negative
Positive
Voltage (V)
Voltage (V)
r1
0.0
V0’
r2
18.4
0.000
5.000
1
V1’
r3
16.8
0.449
4.551
1
0
V2’
r4
17.6
0.859
4.141
0
1
1
V3’
r5
12.0
1.289
3.711
0
1
0
0
V4’
r6
9.6
1.582
3.418
5H
0
1
0
1
V5’
r7
7.2
1.816
3.184
6H
0
1
1
0
V6’
r8
7.2
1.992
3.008
7H
0
1
1
1
V7’
r9
4.8
2.168
2.832
8H
1
0
0
0
V8’
r10
6.4
2.285
2.715
9H
1
0
0
1
V9’
r11
4.0
2.441
2.559
AH
1
0
1
0
V10’
r12
6.4
2.539
2.461
BH
1
0
1
1
V11’
r13
4.8
2.695
2.305
CH
1
1
0
0
V12’
r14
5.6
2.813
2.188
DH
1
1
0
1
V13’
r15
6.4
2.949
2.051
EH
1
1
1
0
V14’
r16
77.6
3.105
1.895
FH
1
1
1
1
V15’
r17
0.0
5.000
0.000
r18
0.0
rTOTAL = 204.8
Data vs Driving Voltage
6.000
5.000
4.000
(V)
3.000
2.000
1.000
0.000
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DATA
Negative Voltage (V)
26
Positive Voltage (V)
Preliminary Product Information S14797EJ3V7PM
DH
EH
FH
µ PD161620
5.9 Partial Display Mode
The µ PD161620 is provided with a function that allows sections within the screen to be displayed separately (partial
display mode). The start line of the area to be displayed in partial display mode is set using the partial display area
start line register (R28, R29), the number of lines in the area to be displayed is set using the partial display area line
number register (R30, 31), and the color of the area not to be displayed is set using the partial off area color register
★
(R27). If ”1” is set in the partial display area line count registers (R30, R31), the partial display areas each become 1
line. If “0” is set, there are no partial display areas but only normal display areas.
The non-display area indicated by R28 and R30 is called Partial 1, and the non-display area indicates by R29 and
R31 is called Partial 2. The Partial 2 setting is enabled only when the Partial 1 setting has been performed (when R30
≠ 0). Therefore, to set only one area as a non-display area, perform only the setting for Partial 1.
Low power consumption cannot be achieved if only the partial mode is set. If low power consumption is required, the
mode must be switched to the 8-clor mode.
Figure 5–15. Partial Display Mode
00H
01H
02H
03H
...
7DH
7EH
7FH
Partial non-display
start line
Section not displayed
Cautions 1. The "scroll step count register (R26)" command is ignored in the partial display mode.
★
2. The specified partial areas must not directly overlap, and the Partial 1 area and Partial 2 area
must be separated by at least one line. If the areas overlap, only the Partial 1 settings are valid,
and partial display is not performed for the Partial 2 area.
★
3. In the case of the 4096 mode, only “00H” can be set to the partial OFF area color register (R27).
In the case of the 8-color mode, any value from 00H to 07h can be set.
The following sequence is recommended to avoid display malfunction when switching from normal display mode to
partial display mode and vice versa.
Preliminary Product Information S14797EJ3V7PM
27
µ PD161620
(1) Recommended sequence for switching from normal display mode to partial display mode
DISP = 0
R0
D6
<1> Display off
↓
D2
PGDn setting
R27

<2> Partial off area color register setting Note 1
D0
↓
<3> Display data overwrite Note 1
Display data overwrite
(for partial display)
↓
D7
P1SLn, P2SLn setting
R28,
R29

<4> Partial display area start line setting Note 1
D0
↓
D7
P1AWn, P2AWn setting

<5> Partial display area line number setting Note 1
R30,
R31
D0
R1
D1,
D2
<6> Partial display mode, 8-color modeNote 2
R0
D6
<7> Display on
↓
DTY = 1, COLOR = 1
↓
DISP = 1
Notes 1. <2> to <5> can be executed in any order.
2. <6> must be executed after <4> and <5> have been set.
28
Preliminary Product Information S14797EJ3V7PM
µ PD161620
(2) Recommended sequence for switching from partial display mode to normal display mode
R0
DISP = 0
D6
<1> Display off
↓
<2> Display data overwrite Note
Display data overwrite
(for normal display)
↓
DTY = 0, COLOR = 0
R1
D1,
D2
<3> Partial display mode, 4096-color modeNote
R0
D6
<4> Display on
↓
DISP = 1
Note <2> to <3> can be executed in any order.
(3) Recommended sequence for switching from partial display mode to partial display mode (switching the
partial display area)
R0
DISP = 0
D6
<1> Display off
↓
<2> Display data overwrite Notes Note 1, 2
(Display data overwrite)
↓
D7
R28,
R29
P1SLn, P2SLn setting

<3> Partial display area start line setting Note 1
D0
↓
D7
P1AWn, P2AWn setting

<4> Partial display area line number setting Note 1
R30,
R31
D0
R1
D1
<5> Partial display mode Note 3
R0
D6
<6> Display on
↓
DTY = 1
↓
DISP = 1
Notes 1. <2> to <4> can be executed in any order.
2. Execute <2> only when necessary.
3. <5> must be executed after <3> and <4> have been set.
Preliminary Product Information S14797EJ3V7PM
29
µ PD161620
(4) Partial display setting examples
Setting A-1
Register
Setting Value
Details of Setting Value
Partial display area start line register (R28, R29)
00H
Sets Y address 00H
Partial display area line number register (R30, R31)
57H
Sets an area of 88 lines
Setting A-2
Register
Setting Value
Details of Setting Value
Partial display area start line register (R28, R29)
58H
Sets Y address 58H
Partial display area line number register (R30, R31)
57H
Sets an area of 88 lines
Setting A-3
Register
Setting Value
Details of Setting Value
Partial display area start line register (R28, R29)
84H
Sets Y address 84H
Partial display area line number register (R30, R31)
57H
Sets an area of 88 lines
Setting A-4
Register
30
Setting Value
Details of Setting Value
Partial display area start line register (R28, R29)
2CH
Sets Y address 2CH
Partial display area line number register (R30, R31)
57H
Sets an area of 88 lines
Preliminary Product Information S14797EJ3V7PM
µ PD161620
Figure 5–16. Partial Display Setting Examples
Source
Gate
Setting A-1
Source
1
144
Gate
1
1
Area not displayed
88
89
88
89
Area not displayed
Partial display area
176
176
Source
Setting A-3
1
Source
144
1
Gate
Setting A-4
1
144
1
Partial display area
44
45
Area not displayed
44
45
Partial display area
Area not displayed
132
133
132
133
Area not displayed
Partial display area
176
144
1
Partial display area
Gate
Setting A-2
176
Preliminary Product Information S14797EJ3V7PM
31
µ PD161620
5.10 Screen Scroll
The µ PD161620 has a screen scroll function. Any area of the screen can be scrolled by using the scroll area start
line register (R22), scroll area line count register (R24), and scroll step count register (R26) to set the Y address of the
top line of the area to be scrolled, the number of lines of the area to be scrolled, and the scroll step number,
respectively.
Note that in partial mode, the screen scroll function is disabled.
Table 5–8. Scroll Area Start Line Register (R22)
SSL7
SSL6
SSL5
SSL4
SSL3
SSL2
SSL1
SSL0
Start Line Y Address
0
0
0
0
0
0
0
0
00H
0
0
0
0
0
0
0
1
01H
0
0
0
0
0
0
1
0
02H
0
0
0
0
0
0
1
1
03H
1
0
1
0
1
1
0
1
ADH
1
0
1
0
1
1
1
0
AEH
1
0
1
0
1
1
1
1
AFH
↓
↓
Table 5–9. Scroll Area Line Count Register (R24)
SAW7
SAW6
SAW5
SAW4
SAW3
SAW2
SAW1
SAW0
Scroll Area Line Number
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
1
1
↓
4
↓
1
0
1
0
1
1
0
1
174
1
0
1
0
1
1
1
0
175
1
0
1
0
1
1
1
1
176
Table 5–10. Scroll Step count Register (R26)
SST7
SST6
SST5
SST4
SST3
SST2
SST1
SST0
Scroll Step Number
0
0
0
0
0
0
0
0
0 (No scroll)
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
1
↓
1
0
1
0
1
1
0
1
173
1
0
1
0
1
1
1
0
174
1
0
1
0
1
1
1
1
175
Scrolling must be set using the following sequence.
32
3
↓
Preliminary Product Information S14797EJ3V7PM
µ PD161620
(1) Recommended sequence
D7
SSLn setting
R22

<1> Scroll area start line setting Note 1
D0
↓
D7
SAWn setting
R24

<2> Scroll area line number setting Note 1
D0
↓
D7
SSTn setting
R26

<3> Scroll step count register setting Note 2
D0
Notes 1. <1> to <2> can be executed in any order.
2. <3> must be executed after <1> and <2> have been set.
Remark Set SSTn to 00H to disable the scroll operation. No particular sequence is required for this.
Cautions 1. If the sum of the values of SSLn and SAWn is 176 (AFH) or over, it is invalid (no scroll
operation).
2. Set the step number SSTn so that it does not exceed the line number SAWn. If a value
exceeding SAWn is set, it will be invalid (no scroll operation).
Preliminary Product Information S14797EJ3V7PM
33
µ PD161620
(2) Scroll setting examples
Setting A-1
Register
Setting Value
Details of Setting Value
Scroll area start line register (R22)
00H
Sets Y address 00H
Scroll area line count register (R24)
AFH
Sets an area of 176 lines
Setting A-2
Register
Setting Value
Details of Setting Value
Scroll area start line register (R22)
00H
Sets Y address 00H
Scroll area line count register (R24)
57H
Sets an area of 88 lines
Setting A-3
Register
Setting Value
Details of Setting Value
Scroll area start line register (R22)
58H
Sets Y address 58H
Scroll area line count register (R24)
57H
Sets an area of 88 lines
Setting A-4
Register
34
Setting Value
Details of Setting Value
Scroll area start line register (R22)
2CH
Sets Y address 2CH
Scroll area line count register (R24)
57H
Sets an area of 88 lines
Preliminary Product Information S14797EJ3V7PM
µ PD161620
Figure 5–17. Display Scroll Setting Examples
Source
Gate
Setting A-1
1
Source
144
Gate
1
Setting A-2
1
144
1
Scroll area
88
89
Scroll area
Fixed display area
176
176
Source
Gate
Setting A-3
Source
1
144
1
Gate
Setting A-4
1
144
1
Fixed display area
44
45
Fixed display area
88
89
Scroll area
Scroll area
132
133
Fixed display area
176
176
Preliminary Product Information S14797EJ3V7PM
35
µ PD161620
(3) Scroll setting flowchart example
Start
↓
IR
Scroll area
start line register assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
1
0
1
1
D3
D2
D1
0
↓
R22
Scroll area
start line register setting
D7 to D0 Scroll area start line register
RS
H
↓
MSB
D7
LSB
D6
D5
D4
D0
Note D7 to D0 are the data for Scroll area start line.
IR
Scroll area
line count register assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
1
1
0
0
D3
D2
D1
0
↓
R24
Scroll area
line count register setting
D7 to D0 Scroll area line count register
RS
H
↓
MSB
D7
LSB
D6
D5
D4
D0
Note D7 to D0 are the data for Scroll area line count register.
IR
D5 to D0 Index register
RS
Scroll step count register assignment
L
MSB
X
LSB
X
0
1
1
0
1
0
↓
R26
Scroll step count register setting
(1 step)
D7 to D0 Scroll step count register
RS
H
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
1
D4
D3
D2
D1
1
↓
IR
D5 to D0 Index register
RS
X address register assignment
L
MSB
X
LSB
X
1
↓
R3
D7 to D0 X address register
RS
X address register setting
H
↓
MSB
D7
LSB
D6
D5
D0
Note D7 to D0 depend on application condition.
IR
Y address register assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
0
1
0
0
↓
R5
Y address register setting
D7 to D0 Y address register
RS
H
↓
36
MSB
D7
LSB
D6
D5
D4
D3
D2
Note D7 to D0 depend on application condition.
Preliminary Product Information S14797EJ3V7PM
D1
D0
µ PD161620
IR
Display memory assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
1
0
1
1
↓
R11
Display data
Re-write scrolling area 1
(Start)
D7 to D0 Display memory
RS
H
↓
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Note D7 to D0 are display memory data.
R11
Display data
Re-write scrolling area 2
D7 to D0 Display memory
RS
H
↓
↓
↓
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D2
D1
D0
Note D7 to D0 are display memory data.
R11
Display data
Re-write scrolling area n
(End)
D7 to D0 Display memory
RS
H
↓
MSB
D7
LSB
D6
D5
D4
D3
D0
Note D7 to D1 are display memory data.
IR
Scroll step count register assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
1
1
0
1
0
↓
R26
Scroll step count register setting
(2 steps)
D7 to D0 Scroll step count register
RS
H
MSB
0
LSB
0
0
0
0
0
1
0
↓
IR
D5 to D0 Index register
RS
X address register assignment
L
MSB
X
LSB
X
0
0
0
0
1
1
↓
R3
D6 to D0 X address register
RS
X address register setting
H
↓
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Note D7 to D0 depend on application condition.
IR
D5 to D0 Index register
RS
Y address register assignment
L
MSB
X
LSB
X
0
0
0
1
0
0
↓
R50
D7 to D0 Y address register
RS
Y address register setting
H
↓
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Note D7 to D1 depend on application condition.
IR
Display memory assignment
MSB
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
1
0
1
1
↓
Preliminary Product Information S14797EJ3V7PM
37
µ PD161620
Display data
R11
Re-write scrolling area 1
D7 to D0 Display memory
RS
(Start)
H
↓
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D2
D1
D0
Note D7 to D0 are display memory data.
R11
Display data
D7 to D0 Display memory
RS
Re-write scrolling area 2
H
↓
MSB
D7
LSB
D6
D5
D4
D3
D0
Note D7 to D0 are display memory data.
↓
↓
Display data
Re-write scrolling area n
(End)
R11
D7 to D0 Display memory
RS
H
MSB
D7
LSB
D6
D4
D3
↓
Note D7 to D0 are display memory data.
↓
(Repeat)
↓
↓
Next transaction
38
D5
Preliminary Product Information S14797EJ3V7PM
D2
D1
D0
µ PD161620
(4)Scroll function example
Scroll area start line register (R22): 2CH
Scroll area line count register (R24): 58H
(a)Scroll step count register setting (R26): 00H
Source
Gate 1
1
144
Y address
00H
Fixed display area
2BH
2CH
44
45
Scroll area
83H
84H
132
133
Fixed display area
176
AFH
(b)Scroll step count register setting (R26): 01H
Source
Gate 1
1
144
Y address
00H
Fixed display area
2BH
2DH
44
45
Scroll area
83H
2CH
84H
132
133
Fixed display area
176
AFH
Preliminary Product Information S14797EJ3V7PM
39
µ PD161620
(c)Scroll step count register setting (R26): 02H
Source
Gate 1
1
144
Y address
00H
Fixed display area
2BH
2EH
44
45
Scroll area
83H
2CH
2DH
84H
132
133
Fixed display area
176
AFH
(d)Scroll step count register setting (R26): 57H
Source
Gate 1
1
144
Y address
00H
Fixed display area
2BH
83H
2CH
44
45
Scroll area
132
133
82H
84H
Fixed display area
176
40
AFH
Preliminary Product Information S14797EJ3V7PM
µ PD161620
★
5.11 Initialization Setting Sequence Example
Power ON
hard reset (/RESET = L)
↓
IR
D5 to D0 Index register
RS
Reset register assignment
L
MSB
X
LSB
X
0
0
0
0
1
X
X
X
X
X
X
0
↓
R2
D7 to D0 Reset
RS
Reset register setting
H
MSB
X
LSB
1
↓
<Initialized state setting sequence>
IR
D5 to D0 Index register
RS
Power supply control register 1 assignment
L
MSB
X
LSB
X
1
0
0
0
0
D3
0
0
0
↓
R32
D7 to D0 Power supply control register 1
RS
Power supply control register 1 setting
H
↓
↓
MSB
X
LSB
D6
D5
D4
0
Note D6 to D4 depend on application condition., D3 to D0:gate
driver, power supply IC regulator OFF, DC/DC converter OFF
IR
D5 to D0 Index register
RS
Power supply control register 2 assignment
L
MSB
X
LSB
X
1
0
0
0
1
0
↓
R34
D7 to D0 Power supply control register2
RS
Power supply control register 2 setting
H
↓
MSB
X
LSB
X
X
X
D3
D2
X
X
Note D3, D2 depend on application condition.
IR
D5 to D0 Index register
RS
Power supply control register 1 assignment
L
MSB
X
LSB
X
1
0
0
0
0
0
↓
R32
Power supply control register 1 setting
D7 to D0 Power supply control register1
RS
H
↓
↓
MSB
X
LSB
D6
D5
D4
D3
1
1
1
Note D6 to D4 depend on application condition., D3 to D0:gate
driver, power supply IC regulator OFF, DC/DC converter OFF
Preliminary Product Information S14797EJ3V7PM
41
µ PD161620
IR
Control register 1 assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
0
0
0
0
↓
R0
Control register 1 setting
D7 to D0 Control register1
RS
↓
↓
↓
↓
↓
IR
Control register 2 assignment
MSB
LSB
H
0
0
0
X
X
D2
Note D7: Normal write mode
D6: Display OFF
D5: Standby OFF
D2 and D1: depend on application condition
Always write to 0 in D0
D5 to D0 Index register
RS
L
D1
MSB
X
0
LSB
X
0
0
0
0
0
0
0
0
0
1
↓
R1
Control register 2 setting
D7 to D0 Control register 2
RS
H
↓
↓
↓
↓
↓
↓
MSB
0
LSB
0
D5
D0
Note D7: All data 0 display OFF (normal mode)
D4: Normal driving mode
D2: 4096-color mode
D1: Normal display mode
D5 and D0: depend on application condition
Always write to 0 in both D6 and D3
IR
Invert set register assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
0
1
1
0
↓
R6
Invert set register setting
D7 to D0 Invert set register
RS
MSB
LSB
H
X
X
X
X
X
Note D0 depends on application condition.
↓
IR
Calibration register assignment
X
X
0
1
1
H
X
X
X
X
X
Note Calibration wait time (tcal)
tcal = 1/(frame frequency x 177)
X
X
D0
D5 to D0 Index register
RS
L
MSB
X
LSB
X
1
0
0
↓
R38
Calibration register setting
(calibration start)
D7 to D0 Calibration register
RS
↓
↓
IR
Calibration register assignment
MSB
LSB
1
D5 to D0 Index register
RS
L
MSB
X
LSB
X
1
0
0
1
1
X
X
X
X
0
↓
R38
Calibration register setting
(calibration stop)
D7 to D0 Calibration register
RS
H
MSB
X
LSB
X
↓
42
Preliminary Product Information S14797EJ3V7PM
X
0
µ PD161620
<Data write sequence>
IR
X address register assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
0
0
1
0
0
0
0
1
↓
R3
X address register setting
D7 to D0 X address register
RS
H
↓
MSB
0
LSB
0
0
0
X address: 00H
IR
Y address register assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
0
1
0
1
↓
R5
Y address register setting
D7 to D0 Y address register
RS
H
↓
MSB
0
LSB
0
0
0
0
0
0
0
Y address: 00H
IR
Display memory assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
1
0
1
D4
D3
D2
D1
D3
D2
D1
D3
D2
D1
1
↓
Display data write 1
R11
D7 to D0 Display memory
RS
(start)
H
↓
R11
RS
↓
↓
LSB
D6
D5
D0
D7 to D0 Display memory
H
(end)
D7
Note D7 to D0: display memory data
Display data write 2
Display data write n
MSB
MSB
D7
LSB
D6
D5
D4
D0
Note D7 to D0: display memory data
R11
D7 to D0 Display memory
RS
H
MSB
D7
LSB
D6
D5
D4
D0
Note D7 to D0: display memory data
Preliminary Product Information S14797EJ3V7PM
43
µ PD161620
IR
Control register 1 assignment
D5 to D0 Index register
RS
L
MSB
X
LSB
X
0
0
0
0
0
X
X
D2
D1
0
↓
R0
Control register 1 setting
D7 to D0 Control register 1
RS
H
↓
↓
↓
↓
↓
MSB
0
LSB
1
Note D7: Normal write mode
D6: Display ON
D5: Standby OFF
D2 and D1: depend on application condition
Always write to 0 in D0
Nest transaction
44
0
Preliminary Product Information S14797EJ3V7PM
0
µ PD161620
6. RESET
If the /RESET input becomes L or the reset command is input, the internal timing generator is initialized. The reset
command will also initialize each register to its default value. These default values are listed in the table below.
Register
★
Reset Command
Default Value
Index register
IR
X
O
00H
Control register 1
R0
X
O
00H
Control register 2
R1
X
O
00H
X address register
R3
X
O
00H
Y address register
R5
X
O
00H
Reverse setting register
R6
X
O
00H
Display memory Note 2
R11
X
X
-
Scroll area start line register
R22
X
O
00H
Scroll area line count register
R24
X
O
00H
Scroll step count register
R26
X
O
00H
Partial off area color register
R27
X
O
00H
Partial 1 display area start line register
R28
X
O
00H
Partial 2 display area start line register
R29
X
O
00H
Partial 1 display area line count register
R30
X
O
00H
Partial 2 display area line count register
R31
X
O
00H
Power supply control register 1
R32
X
O
00H
Power supply control register 2
R34
X
O
00H
Calibration register
★
/RESET Pin Note 1
Note 3
R38
X
O
01H
Output port register
R42
X
O
00H
Input port register
R43
X
O
00H
R44 to R47
X
O
00H
Test mode
O: Default value set, X: Default value not set
Notes 1. The internal counters are initialized only by a reset from the /RESET pin. Be sure to perform reset via the
/RESET pin at power application.
2. The contents of RAM are saved in the case of both reset by /RESET pin and reset by reset command.
Note that the RAM contents are T.B.D. immediately after the power is turned on.
3. The following value is set as the calibration setting time, tcal, in a reset by reset command.
tcal = 1/fOSC x 32
★
Remark T.B.D. (to be determined.)
Preliminary Product Information S14797EJ3V7PM
45
µ PD161620
7. COMMAND
★
7.1 Command List
Index Register
5
1st byte
2nd byte
Remark
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Register Name
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Bits
R/W
0
7
IR
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
6
5
2
IR2
ADX
1
0
Y address register
Reverse setting register
R/W
R/W
YA7
YA6
YA5
Display memory
R/W
D7
D6
D5
Scroll area start line register
R/W SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0
Scroll area line count register
R/W SAW7 SAW6 SAW5 SAW4 SAW3 SAW2 SAW1 SAW0
Scroll step count register
Partial off area color register
Partial 1 display area start line register
Partial 2 display area start line register
Partial 1 display area line count register
Partial 2 display area line count register
Power supply control register 1
R/W SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0
PGD2 PGD1 PGD0
R/W
R/W P1SL7 P1SL6 P1SL5 P1SL4 P1SL3 P1SL2 P1SL1 P1SL0
R/W P2SL7 P2SL6 P2SL5 P2SL4 P2SL3 P2SL2 P2SL1 P2SL0
R/W P1AW7 P1AW6 P1AW5 P1AW4 P1AW3 P1AW2 P1AW1 P1AW0
R/W P2AW7 P2AW6 P2AW5 P2AW4 P2AW3 P2AW2 P2AW1 P2AW0
BGRS VCE VCD2 PVCOM RGONG RGONP DCON
R/W
Power supply control register 2
R/W
Calibration register
R/W
Output port register
Input port register
W
R
R/W
R/W
R/W
R/W
Test mode
Test mode
Test mode
Test mode
: These registers cannot be used.
Also, the RS signal during the write operation becomes invalid.
2. A low level is output when an unused register is read.
46
3
IR3
W
IR5
IR4
R/W RMW DISP STBY
R/W FDM
DTX LPM
W
R/W XA7 XA6 XA5 XA4
Cautions 1. If a write-only register is read, invalid data will be output.
★
4
Index register
Control register 1
Control register 2
Reset
X address register
Preliminary Product Information S14797EJ3V7PM
IR1
ADC
COLOR DTY
IR0
XA3
XA2
INC
CRES
XA1 XA0
YA4
YA3
YA2
YA1
YA0
INV
D4
D3
D2
D1
D0
VCD12 VCD11
OC
OP3
IP3
OP2
IP2
OP1
IP1
OP0
IP0
µ PD161620
7.2 Command Explanation
(1/4)
Resistor
★
R0
Bit
D7
Symbol
RMW
Function
This bit enables/disables use of the read-modify-write mode function.
Perform read/write switching in the read-modify-write mode at every 2-byte access in the 1-pixel/2-byte
mode. Similarly, in the 2-ixel/3-byte mode, perform read/write switching at every 3-byte access
0: Address is incremented by one each time a display data read or write
1: Read modify write mode (address is incremented by one each time a display data
write only)
D6
DISP
This bit switches display ON/OFF. When display OFF is selected, output is performed as when all the
data is “1”, regardless of the internal RAM data. (In the case of normally white, white display is
performed.)
This command is executed from the time the next line data is output.
0: Display off (All output pins are VSS level, OSC and DC/DC converter are working)
1: Display on
D5
STBY
This bit selects the standby function. When the standby function is selected, a display OFF operation is
executed and the amplifiers at each output stage and the operation of internal oscillation circuit are
stopped.
However, standby control cannot be performed for the gate IC (µ PD161640) connected to
µ PD161620 and the power supply IC (µ PD161660). Therefore, after executing the standby function
using this bit, set both the regulator for the gate IC and power supply IC to off and set the DC/DC
converter to OFF. For the sequence, refer to the preliminary product information machine of the
µ PD161660.
Note that when releasing standby, perform the opposite operation, i.e., after setting the DC/DC
converter to ON and setting the regulators of the gate IC and power supply IC to ON, execute the
normal operation command.
0: Normal operation
1: Stand-by function
(Display read off from RAM, stop both OSC and VCOM, display off = entire data is output as 1 )
D2
ADX
Switches X address addressing
X address direction
★
R1
D1
ADC
Column address direction
D7
FDM
This bit does not depend on the internal RAM data. This function performs output in the same way as
when all the data is “0”. (In the case of normally white, black display is performed.)
This command is executed from the time the next line data is output.
0: Normal operation
1: RAM data is ignored and the entire data is output as 0.
D5
DTX
This bit selects the method for transferring data to internal RAM.
0: 2-pixel / 3-byte
1: 1-pixel / 2-byte
D4
LPM
This bit is used when setting the gate IC (µ PD161640) and power supply IC (µ PD161660) to the lowpower mode. When the low-power mode is selected, the LPMG pin and the LPMP pin signals change
from low to high (output changes immediately following command execution.).
The LPMG pin must be connected to the LPM pin of the gate IC, and the LPMP pin must be connected
to the LPM pin of the power supply IC.
0: Normal
1: Low power mode
Preliminary Product Information S14797EJ3V7PM
47
µ PD161620
(2/4)
Resistor
Bit
D2
Symbol
COLOR
Function
This pin switches the 4096-color mode and the 8-color mode. When the 8-color mode is
selected, low power supply can be selected in order to stop the amplifier at each output stage.
In the 8-color mode, the value of the MSB of the internal RAM data is used as the color data.
This command is executed following transfer from the time the next line data is output.
0: 4096-color mode (12 bits/pixels)
1: 8-color mode (3 bits/pixels)
D1
DTY
This pin selects the partial function.
When the partial function s selected in the 4096-color mode, set the partial-OFF area-color
selection register (R27) to 00H. In the 8-color mode, the partial OFF area color can be set to any
value from 00H to 07 H. The power consumption cannot be reduced with the partial function.
To reduce the power consumption, select the 8-color mode.
This command is executed following transfer from the time the next line data is output.
0: Normal display mode
1: Partial display mode
D0
INC
This pin selects the address increment direction.
In the case of the 8-bit parallel interface mode and the serial interface mode, when Y address
increment is selected, only the 1-pixel/2-byte mode can be selected as the data transfer mode.
However, when X address increment is selected, both the 1-pixel/2-byte and 2-pixel/3-byte modes
can be selected.
0: X address increment
1: Y address increment
★
R2
D0
CRES
Command reset function. Be sure to execute this bit after power ON.
Command reset automatically clears this bit following execution (CRES = 01H). Therefore, it is
not necessary to set 0 (select normal operation) again by software. Moreover, since the time
required for the value of this bit to change (1 → 0) following command reset execution is
extremely short, it is not necessary to secure time until the next command is set following
command reset setting.
0: Normal operation
1: Command reset
★
R3
D7 to D0
XA7 to XA0
This register sets the X address.
Set a value between 00H and 8FH.
★
R5
D7 to D0
YAn
This register sets the Y address.
★
R6
D0
INV
This bit selects between the line inversion function and the frame inversion function.
Set a value between 00H and 8FH.
The mode selected by this command is executed from the start of the next scan after the gate
scan in progress when this command was executed has completed 176 lines. When the reset
command is input, the INV register is initialized. 0: Line inversion with same line.
0: Line inversion
1: Frame inversion
★
R11
D7 to D0
Dn
These bits are used for reading/writing data from /to display memory (internal RAM).
R22
D7 to D0
SSLn
Scroll area start line register (00H to AFH)
R24
D7 to D0
SAWn
Scroll area line count register (00H to AFH)
R26
D7 to D0
SSTn
Scroll step count register (00H to AFH), invalid in partial display mode
48
Preliminary Product Information S14797EJ3V7PM
µ PD161620
(3/4)
Resistor
★
R27
Bit
D2 to D0
Symbol
PGDn
Function
Partial off area color register (000H to 111H)
The relationship between each color data and the bits of this register is as follows. This
relationship does not depend on the ADX and ADC values
D11 to D8: PGD0
D7 to D4: PGD1
D3 to D0: PGD2
★
R28
D7 to D0
P1SLn
Partial1 display area start line register (00H to AFH)
R29
D7 to D0
P2SLn
Partial2 display area start line register (00H to AFH)
R30
D7 to D0
P1AWn
Partial1 display area line count register (00H to AFH)
When this register is 0, the values of the partial 2 display area start line register (R29) and the
partial 2 display area line count register (R31) are not valid.
★
R31
D7 to D0
P2AWn
Partial2 display area line count register (00H to AFH)
R32
D6
BGRS
This pin selects whether to use the internal power supply or an external power supply (input
from the BRGIN pin) for generation the common center voltage output from the VCOM pin.
0: The internal power-supply is selected as the VCOM power supply
1: Input from the external power-supply BGRIN is selected as the BCOM power supply
D5
VCE
Selects the VO output level of the power supply IC (µ PD161660).
The VCE pin of this IC and the VCE pin of the power supply IC must be connected.
0: The Vo high-level booster voltage level is VDD1 minus 1 level
1: The Vo high-level booster voltage level is the same level as VDD1
D4
VCD2
Selects the VDD2 output level of the power supply IC (µ PD161660).
The VCD2 pin of this IC and the VCD2 pin of the power supply IC must be connected.
0: VDD2 = VDC × 2
1: VDD2 = VDC × 3
D2
RGONG
Switches the internal regulator of the gate IC (µ PD161640) ON/OFF.
When OFF is selected, a low level is output from the RGONG pin, and when ON is selected, a
high level is output from the RGONG pin.
The RGONG pin of this IC and the RGON pin of the gate IC must be connected.
0: Regulators of gate driver (VB) are off
1: Regulators of gate driver (VB) are on
D1
RGONP
Switches the internal DC/DC converter of the power supply IC (µ PD161660) ON/OFF.
When OFF is selected, a low level is output from the RGONP pin, and when ON is selected, a
high level is output from the RGONP pin.
The RGONP pin of this IC and the RGON pin of the power supply IC must be connected.
0: Regulators of power supply IC (VT, VS) are off
1: Regulators of power supply IC (VT, VS) are on
D0
DCON
Switches the internal DC/DC converter of the power supply IC (µ PD161660) ON/OFF.
When OFF is selected, a low level is output from the DCON pin, and when ON is selected, a
high level is output from the DCON pin.
The DCON pin of this IC and the DCON pin of the power supply IC must be connected.
0: DC/DC converter is off
1: DC/DC converter is on
Preliminary Product Information S14797EJ3V7PM
49
µ PD161620
(4/4)
Resistor
★
R34
Bit
Symbol
Function
D3,
VCD12,
Performs booster control for the DC/DC converter in the power supply IC (µ PD161660)
D2
VCD11
The data set with this bit is output from the VCD11 pin and the VCD12 pin.
The VCD11 pin and VCD12 pin of µ PD161620 must be connected to the VCD11 pin and the
VCD12 pin of the power supply IC.
VCD12, VCD11 = 0, 0: VDD1 = VDC × 4
= 0, 1: VDD1 = VDC × 5
= 1, 0: VDD1 = VDC × 6
= 1, 1: VDD1 = VDC × 7
★
R38
D0
OC
This bit is used for calibration.
The time from calibration start command execution until calibration stop command execution
becomes the time for 1 line.
0: Calibration start
1: Calibration stop
★
R42
D3 to D0
OPn
Output port (OP3 to OP0) write
When after the R42 register is specified in the index register, writing to the R42 register is
performed, the values written to the OP3 to OP0 pins are output.
★
R43
D3 to D0
IPn
Input port (IP3 to IP0) read
To read the IP3 to IP0 inputs, use the following method.
<Read sequence>
<1> Specify the R43 register from the index register.
<2> Execute dummy write to the R43 register.
(Values input to IP3 to IP0 are loaded to internal latch.)
<3>Execute R43 register read.
(Reads the internal latch data.)
R44
-
-
R45
-
-
R46
-
-
R47
-
-
50
Test mode (for IC testing only)
Preliminary Product Information S14797EJ3V7PM
µ PD161620
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V)
Parameter
★
Symbol
Ratings
Unit
Power supply voltage
VS
–0.5 to +6.5
V
Power supply voltage
VCC1
–0.5 to +6.5
V
Power supply voltage
VCC2
–0.5 to VCC1 + 0.5
V
Power supply voltage for γ-curve correction
V1 to V15
–0.5 to VS + 0.5
V
Input voltage
VI
–0.5 to VCC1 + 0.5
V
Input current
II
±10
mA
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = –40 to +85°°C, VSS = 0 V)
Parameter
★
★
★
Power supply voltage
Input voltage
Symbol
MIN.
TYP.
MAX.
Unit
VS
3.6
4.0/5.0
5.5
V
VCC1
2.5
2.7
3.6
V
VCC2
1.8
VCC1
V
VI Note1
0
VCC1
V
VI Note2
0
VCC2
V
Notes 1. Pins of VCC1 power-supply system: PSX0, PSX1, OSEL, C86, TESTOUT, IP0 to IP3, OP0 to OP3, LPMG, LPMP,
GOE1, GOE2, GSTB, GCLK, DCON, RGONP, RGONG, VCD11, VCD12,
VCD2, VCE, OSCSEL, TESTIN
★
2. Pins of VCC2 power-supply system: /CS1, CS2, /RD(E), /WR(R,/W), RDY, D0 to D4, D5(SO), D6(SCL), D7(SI),
RS, /RESET, GSB, OSCIN
Preliminary Product Information S14797EJ3V7PM
51
µ PD161620
★ Electrical Specifications (Unless Otherwise Specified, TA = –40 to +85°°C, VCC1 = 2.5 to 3.6 V,
VCC2 = 1.8 V to VCC1, VS = 3.6 to 5.5 V)
Parameter
Symbol
Condition
Specification
MIN.
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
VCOM output voltage
TYP.Note
Unit
MAX.
VIH1
VCC1
0.8 VCC1
V
VIH2
VCC2
0.8 VCC2
V
VIL1
VCC1
0.2 VCC1
V
VIL2
VCC2
0.2 VCC2
V
VOH1
VCC1, IOUT = –100 µA
0.9 VCC1
V
VOH2
VCC2, IOUT = –1 mA
0.8 VCC2
V
VOH3
VCOUT, IOUT = –100 µA
0.9 VS
V
VOL1
VCC1, IOUT = 100 µA
0.1 VCC1
V
VOL2
VCC2, IOUT = 1 mA
0.2 VCC2
V
VOL3
VCOUT, IOUT = 100 µA
0.1 VS
V
VCOMH
ISOURCE = 40 µA
VCOM – 12.5
mV
VCOML
ISINK = –40 µA
IIH1
D0 to D7, TESTIN
IIH2
TESTIN
IIL1
Except D0 to D7
High level leakage current
ILIH
D0 to D7
Low level leakage current
ILIL
D0 to D7
IVOH
VX = 3.0 V, VOUT = 4.0 V,
–100
µA
★ High level input current
Low level input current
★ High level driver output current
20
60
VCOM + 12.5
mV
1
µA
130
µA
–1
µA
10
µA
–10
µA
VS = 5.0 V
★ Low level driver output current
VX = 2.0 V, VOUT = 1.0 V,
IVOL
µA
150
VS = 5.0 V
★ Driver output deviation
★ Internal reference voltage
∆VO
∆VCOM
–6
±30
mV
0
6
V
90
135
µA
variation for VCOM output
★ Current consumption
ICC1
VCC1 (when non-access CPU)
ICC2
VCC2 (when non-access CPU)
1
µA
IS
4096-color mode
800
1200
µA
8-color mode
100
150
µA
5
µA
Stand-by mode
Note TYP. values are reference values when TA = 25°C
52
Preliminary Product Information S14797EJ3V7PM
µ PD161620
★ AC Characteristics (Unless Otherwise Specified, TA = –40 to +85°°C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 V to VCC1,
VS = 3.6 to 5.5 V)
(a) i80 series CPU interface
RS
tAS8
tf
tr
tAH8
/CS1
(CS2 = 1)
tCYC8
tCCLW, tCCLR
/WR, /RD
tCCHR, tCCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Preliminary Product Information S14797EJ3V7PM
53
µ PD161620
When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2
★
★
Symbol
Condition
MIN.
0
TYP.
Note
Parameter
Address hold time
tAH8
RS
MAX.
Unit
ns
Address setup time
tAS8
RS
System cycle time
tCYC8
Control low-level pulse width (/WR)
tCCLW
/WR
120
ns
Control low-level pulse width (/RD)
tCCLR
/RD
140
ns
0
ns
250
ns
Control high-level pulse width (/WR)
tCCHW
/WR
60
ns
★
Control high-level pulse width (/RD)
tCCHR
/RD
80
ns
★
Data setup time
tDS8
D0 to D7
80
ns
★
Data hold time
tDH8
D0 to D7
5
★
/RD access time
tACC8
D0 to D7, CL = 100 pF
★
Output disable time
tOH8
D0 to D7, CL = 100 pF
ns
10
140
ns
140
ns
MAX.
Unit
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
When VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 2.5 V, VCC1 ≥ VCC2
Symbol
Condition
TYP.
Note
Parameter
Address hold time
tAH8
RS
MIN.
0
Address setup time
tAS8
RS
0
ns
System cycle time
tCYC8
333
ns
★
Control low-level pulse width (/WR)
tCCLW
/WR
120
ns
★
Control low-level pulse width (/RD)
tCCLR
/RD
160
ns
Control high-level pulse width (/WR)
tCCHW
/WR
100
ns
Control high-level pulse width (/RD)
tCCHR
/RD
140
ns
Data setup time
tDS8
D0 to D7
100
ns
5
★
★
Data hold time
tDH8
D0 to D7
★
/RD access time
tACC8
D0 to D7, CL = 100 pF
★
Output disable time
tOH8
D0 to D7, CL = 100 pF
10
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
54
Preliminary Product Information S14797EJ3V7PM
ns
180
ns
180
ns
µ PD161620
(b) M68 series CPU interface
RS
R,/W
tAS6
tf
tr
tAH6
/CS1
(CS2 = 1)
tCYC6
tEWHR, tEWHW
E
tEWLR, tEWLW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Preliminary Product Information S14797EJ3V7PM
55
µ PD161620
When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2
Parameter
Address hold time
Symbol
tAH6
RS
Address setup time
tAS6
RS
System cycle time
tCYC6
★ Data setup time
Condition
MIN.
0
TYP.
Note
MAX.
Unit
ns
0
ns
250
ns
tDS6
D0 to D7
80
ns
tDH6
D0 to D7
0
ns
Access time
tACC6
D0 to D7, CL = 100 pF
Output disable time
tOH6
D0 to D7, CL = 100 pF
10
Read
tEWHR
E
140
ns
Write
tEWHW
E
120
ns
Read
tEWLR
E
80
ns
Write
tEWLW
E
60
ns
Data hold time
★ Enable high pulse width
★ Enable low pulse width
110
ns
100
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VCC2.
When VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 2.5 V, VCC1 ≥ VCC2
Note
Symbol
tAH6
RS
MIN.
0
Address setup time
tAS6
RS
0
ns
System cycle time
tCYC6
333
ns
Data setup time
tDS6
D0 to D7
100
ns
Data hold time
tDH6
D0 to D7
0
ns
Access time
tACC6
D0 to D7, CL = 100 pF
Output disable time
tOH6
D0 to D7, CL = 100 pF
10
Read
tEWHR
E
160
ns
Write
tEWHW
E
120
ns
Read
tEWLR
E
140
ns
Write
tEWLW
E
100
ns
★ Enable high pulse width
★ Enable low pulse width
Condition
TYP.
Parameter
Address hold time
MAX.
Unit
ns
150
ns
150
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (tr + tf) < (tCYC6–tEWLR–tEWHR) or (tr + tf) < (tCYC6–tEWLW–tEWHW).
2. All timing is rated based on 20 to 80% of VCC2.
56
Preliminary Product Information S14797EJ3V7PM
µ PD161620
(c) RDY timing
Write cycle (Display data write)
/CS1
(CS2 = 1)
tRDWE
/WR (i80)
tWP
E (M68)
tRYR1
★
tRYZ
RDY
tRYF
tRYR2
tDS8/tDS6
tDH8/tDH6
D0 to D7
(Write)
★
VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 1.9 V, VCC1 ≥ VCC2
Parameter
★
★
Symbol
Condition
MIN.
TYP.
MAX.
Unit
RDY output delay time (CS)
tRYR1
CL = 15 pF
110
ns
RDY output delay time (/WR, E)
tRYR2
CL = 15 pF
160
ns
RDY low level time
tRYF
Note 1
850
ns
Write pulse width
tWP
Note 1
RDY to /WR, E time
tRDWE
RDY output delay time
tRYZ
0
Note 2
ns
1000
ns
90
ns
Data setup time
tDS8/6
100
ns
Data hold time
tDH8/6
0
ns
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
Notes 1.
VCC2
1.8 kΩ
1.0 kΩ
60 pF
2.
VCC2
1.8 kΩ
1.0 kΩ
5 pF
Preliminary Product Information S14797EJ3V7PM
57
µ PD161620
Write cycle (Display data read)
/CS1
(CS2 = 1)
tRDRE
/RD (i80)
tRP
/E (M68)
tRYR1
★
tRYZ
RDY
tRYF
tRYR2
D0 to D7
(Read)
tACC8/tACC6
tOH8/tOH6
VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 1.9 V, VCC1 ≥ VCC2
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
RDY output delay time (CS)
tRYR1
CL = 15 pF
110
ns
★
RDY output delay time (/RD, E)
tRYR2
CL = 15 pF
160
ns
★
RDY low level time
tRYF2
Note 1
850
ns
Read pulse width
tRP
Note 1
RDY to /WR, E time
tRDRE
RDY output delay time
tRYZ
Note 2
Read data access time
tACC8/6
CL = 100 pF
Data hold time
tOH8/6
CL = 100 pF
★
★
0
10
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
Notes 1.
VCC2
1.8 kΩ
1.0 kΩ
60 pF
2.
VCC2
1.8 kΩ
1.0 kΩ
58
5 pF
Preliminary Product Information S14797EJ3V7PM
ns
1000
ns
90
ns
150
ns
150
ns
µ PD161620
Write cycle (Display data write)
/CS1
(CS2 = 1)
tRDWE
/WR (i80)
tWP
E (M68)
tRYR1
★
tRYZ
RDY
tRYF
tRYR2
tDS8/tDS6
tDH8/tDH6
D0 to D7
(Write)
★
VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2
Parameter
★
★
Symbol
Condition
MIN.
TYP.
MAX.
Unit
RDY output delay time (CS)
tRYR1
CL = 15 pF
80
ns
RDY output delay time (/WR, E)
tRYR2
CL = 15 pF
140
ns
RDY low level time
tRYF2
Note 1
850
ns
Write pulse width
tWP
Note 1
RDY to /WR, E time
tRDWE
RDY output delay time
tRYZ
0
Note 2
ns
1000
ns
70
ns
Data setup time
tDS8/6
80
ns
Data hold time
tDH8/6
0
ns
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
Notes 1.
VCC2
1.8 kΩ
1.0 kΩ
60 pF
2.
VCC2
1.8 kΩ
1.0 kΩ
5 pF
Preliminary Product Information S14797EJ3V7PM
59
µ PD161620
Read cycle (Display data read)
/CS1
(CS2 = 1)
tRDRE
/RD (i80)
tRP
/E (M68)
tRYR1
★
tRYZ
RDY
tRYF
tRYR2
D0 to D7
(Read)
tACC8/tACC6
tOH8/tOH6
VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2
Parameter
★
Symbol
Condition
MIN.
TYP.
MAX.
Unit
RDY output delay time (CS)
tRYR1
CL = 15 pF
80
ns
RDY output delay time (/RD, E)
tRYR2
CL = 15 pF
140
ns
RDY low level time
tRYF2
Note 1
850
ns
Read pulse width
tRP
Note 1
RDY to /RD, E
tRDRE
RDY output delay time
tRYZ
Note 2
Read data access time
tACC8/6
CL = 100 pF
Data hold time
tOH8/6
CL = 100 pF
0
10
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
Notes 1.
VCC2
1.8 kΩ
1.0 kΩ
60 pF
2.
VCC2
1.8 kΩ
1.0 kΩ
60
5 pF
Preliminary Product Information S14797EJ3V7PM
ns
1000
ns
70
ns
110
ns
100
ns
µ PD161620
(d) Serial interface
tCSS
tCSH
/CS1
(CS2 = 1)
tSAS
tSAH
RS
tSCYC
tSLW
SCL
tSHW
tf
tSDS
tr
tSDH
SI
VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 1.9 V, VCC1 ≥ VCC2
Parameter
Symbol
Condition
MIN.
TYP.
Note
MAX.
Unit
Serial clock cycle
tSCYC
SCL
250
ns
SCL high-level pulse width
tSHW
SCL
100
ns
SCL low-level pulse width
tSLW
SCL
100
ns
Address hold time
tSAH
RS
150
ns
Address setup time
tSAS
RS
150
ns
Data setup time
tSDS
SI
100
ns
Data hold time
tSDH
SI
100
ns
CS - SCL time
tCSS
/CS1, CS2
150
ns
tCSH
/CS1, CS2
150
ns
Note TYP. values are reference values when TA = 25°C.
VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 ≥ VCC2
Parameter
Serial clock cycle
Symbol
Condition
MIN.
TYP.
Note
MAX.
Unit
tSCYC
SCL
150
ns
SCL high-level pulse width
tSHW
SCL
60
ns
SCL low-level pulse width
tSLW
SCL
60
ns
Address hold time
tSAH
RS
90
ns
Address setup time
tSAS
RS
90
ns
Data setup time
tSDS
SI
60
ns
Data hold time
tSDH
SI
60
ns
CS - SCL time
tCSS
/CS1, CS2
90
ns
tCSH
/CS1, CS2
90
ns
Note TYP. values are reference values when TA = 25°C.
Remarks 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20 to 80% of VCC2.
Preliminary Product Information S14797EJ3V7PM
61
µ PD161620
(e) Common
Parameter
★
★
Symbol
Condition
MIN.
TYP.Note 1
MAX.
Unit
Oscillation frequency
fOSC
Internal oscillator
260
412
680
kHz
Calibration setting time
tcal
Note 2
47
77.6
93
µs
(frame frequency)
(fFRAME0)
(120)
(72.8)
(60.7)
(Hz)
Frame frequency
fFRAME1
Uncalibrated
46
73
120
Hz
fFRAME2
Calibrated Note 3
76
80
84
Hz
fFRAME3
Calibrated Note 4
79
80
81
Hz
Input oscillation frequency
fOSCIN
External oscillator
260
680
kHz
Reset pulse width at power on
tVR
VCC1 or VCC2 to /RESET↑
100
ns
Reset pulse width
tRW
100
ns
Reset time
tR
100
ns
/RESET↑ to interface operation
Notes 1. TYP. values are reference values when TA = 25°C.
2. The relationship between the frame frequency and the calibration setting time is as follows (n: line count).
★
fFRAME0 =
1
tcal x 177
3. Measured at TA = –40 to +85°C, after calibration at frame frequency = 80 Hz, TA = 25°C exactly.
4. Measured at ±5°C, after calibration at frame frequency = 80 Hz exactly.
62
Preliminary Product Information S14797EJ3V7PM
µ PD161620
★
9. CONNECTION of µ PD161620, 161640, and 161660
The connection of the µ PD161620, 161640, and 161660 is outlined below.
1.7 V to VCC1
CPU
VDD
An
/CS1, CS2
/RD(E)
/WR(R,/W)
D7 to D0
RESET
WAIT
2.5 V to 3.6 V
VCC1
VCC1
RS
/CS1, CS2
/RD(E)
/WR(R,/W)
D7 to D0
RESET
RDY
VCC2
VS
VS
VDC
DCON
DCON
RGONP
RGONP
VCOMR
VCOM
uPD161620
VCE
VCE
VCD11
VCD11
VCD12
VCD12
uPD161660
VSS
VCCD22
LPMP
LPM
VO
VCCD22
VT
VCOMOUT
2.5 V to 5.5 V
GND(0 V)
GCLK
GSTB
GOE1
GOE2
RGONG
GSB
VSS
Y432
Y431
Y2
Y1
LPMP
VCC1
VEE
VT
CLK
STVR(STVL)
OE1
OE2
RGONG
SB
LPM
COMMON
O1
O2
uPD161640
TFT-LCD Panel
O176
VSS
Preliminary Product Information S14797EJ3V7PM
63
µ PD161620
★ The appearance of the µ PD161620, 161640, and 161660 when they are connected face-up is as follows.
Sample uPD161620/40/60 connection diagram
Capacitor and diode connected to power supply IC
VDD1: 1 uF, 25 V withstandiing voltage,
VDD2: 1 uF, 10 V withstanding voltage, VT,
VREF: 0.1 uF, 10 V withstanding voltage,
VDC: 1 uF, 10 V withstanding voltage,
VCC1: 1 uF, 10 V withstanding voltage
VCC1
vss
Diode: 40 V
withstanding voltage
DUMMY
VCD12
VCD2
VCE
DUMMY
DUMMY
VDC
DUMMY
DUMMY
VS
MVS
VREF
VT
MVT
VDD1
VDD2
DUMMY
1 uF, 25 V withstanding
voltage
Face Up
DUMMY
LACS0
VSS
TESTIN6
TESTOUT
TESTIN5
TESTIN4
DUMMY
DUMMY
VCC1
DUMMY
VSS
DUMMY
TESTIN3
TESTIN2
TESTIN1
DUMMY
DUMMY
VCD11
LPM
RGONP
DCON
EXRVT
EXRVS
LFS1
LFS0
FS1
FS0
RSEL
ACS1
ACS0
VREFSEL
LACS1
DAMMY
1 uF
DUMMY
VO
C6+
C6C5+
C5C4+
C4C3+
C3C2+
C2C1+
C1DUMMY
DUMMY
DUMMY
Diode: 40 V
withstanding voltage
C1 to C6: 1 uF, 10 V withstanding
voltage
4.7 to 10 uF, 10 V withstanding voltage
Variable resistor: 51 to 100 kΩ
Resistor
Resis
Variable resistor: 51 to 150 kΩ
Resisto
200 kΩ
0.1 to 10 uF, 10 V withstanding voltage
DUMMY
TEST7
TEST8
TEST9
TEST1
DVSS
TEST2
DVCC1
TEST3
DVSS
TEST4
TEST5
DVCC1
OSCSEL
DVSS
C86
DVCC1
PSX0
DVSS
PSX1
DVCC1
DVSS
OSCIN
RDY
/RESET
/CS1
D7(SI)
D6(SCL)
D5(SO)
D4
D3
D2
D1
D0
RS
/WR(R,/W)
/RD(E)
SSB
CS2
VCC2
TESTIN
TESTOUT
VCE
VCD2
VCD12
VCD11
LPMP
RGONP
DCON
VCOUT
VCOM
DUMMY
DUMMY
DUMMY
VCC1
VSS
VS
VCOMR
BGRIN
DVSS
DVCC1
TEST6
VRH
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
VRL1
VRL2
OP0
OP1
OP2
OP3
DVSS
IP0
IP1
IP2
IP3
DVCC1
GSTB
GCLK
GOE1
GOE2
RGONG
LPMG
TEST10
CPU I/F
Face Up
Y5
Y4
Y3
Y2
Y1
Y1
Y2
Y3
To COM
Face Up
O176
O175
O174
O3
O2
O1
64
Preliminary Product Information S14797EJ3V7PM
TEST1
TEST2
PVCC1
LACS0
PVSS
LACS1
PVCC1
ACS0
PVSS
ACS1
PVCC1
R,/L
PVSS
EXRV
PVCC1
RSEL
PVSS
OSEL
PVCC1
VREF
VR
VB
VT
VEE
VSS
VCC1
VB
VR
MVR
STVR
STVL
CLK
OE1
OE2
RGONG
LPM
SB
µ PD161620
★
10. EXAMPLE of µ PD161620 and CPU CONNECTION
Examples of µ PD161620 and CPU connection are shown below. In parallel interface mode, connect the RDY signal
to the external WAIT pin of the CPU to execute wait control. In the example below, RS pin control in parallel interface
mode is described for the case when the least significant bit of the address bus is being used.
(1) i80 series format
(2) M68 series format
µ PD161620
CPU
µ PD161620
CPU
VDD
VCC2
VDD
VCC2
VSS
VSS
VSS
VSS
/CS
/CS1
/CS
/CS1
A0
RS
D0 to D7
D0 to D7
/RD
/RD
/WR
/WR
/WAIT
RDY
/RESET
/RESET
A0
D0 to D7
R,/W
E
/WAIT
/RESET
RS
D0 to D7
R,/W
E
RDY
/RESET
(3) Serial interface
µ PD161620
CPU
VDD
VCC2
VSS
VSS
/CS
/CS1
PORT
RS
SCL
SCL
SI
SO
SO
SI
/RESET
/RESET
Preliminary Product Information S14797EJ3V7PM
65
µ PD161620
11. REVISION HISTORY
(1/2)
Edition/
Date
Page
Description
This
Previous
Type of
edition
edition
revision
1st edition/
S14797EJ1V0PM00
Apr. 2000
−
−
−
2nd edition/
S14797EJ2V0PM00
Aug. 2000
Throughout
Throughout
Modification
Title
Throughout
Throughout
Modification
R22 register name
Throughout
Throughout
Modification
R24 register name
p.2
p.2
Modification
1. BLOCK DIAGRAM
66
Location
−
p.7
p.7
Modification
3. PIN FUNCTIONS
p.10
p.10
Modification
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF
UNUSED PINS
p.12
p.11
Modification
5.1 title
p.12
p.11
Modification
p.12
p.11
Addition
p.14
p.13
Addition
p.14
p.13
Modification
5.1.1 Selection of interface type
5.1.2 Selection of data transfer mode
Figure 5−3
Figure 5−4 title
p.15
−
Addition
5.1.4 Serial interface
p.16
p.14
Addition
5.2.1 X address circuit
p.17
p.15
Addition
5.2.3 Y address circuit
p.18
−
Modification
Figure 5−7
p.19
p.17
Modification
5.3 Oscillator
p.19
−
Addition
Figure 5−9
p.22
−
Addition
5.9 Partial Display Mode
p.27
−
Addition
5.10 Screen Scroll
p.36
p.19
Modification
6. RESET
p.37
p.20
Modification
7. COMMAND
p.46
−
Addition
p.50
p.28
Modification
(c) RDY timing
(d) Serial interface
Preliminary Product Information S14797EJ3V7PM
µ PD161620
(2/2)
Edition/
Date
3rd edition/
S14797EJ3V7PM00
Jul. 2001
Page
Description
This
Previous
Type of
Location
edition
edition
revision
Throughout
Throughout
Deletion
384 output
Throughout
Throughout
Addition
V8 to V15, VRH, VRL1, VRL2
p.1
p.1
Modification
p.2
p.2
Modification
1. BLOCK DIAGRAM
p.3,4,5,6,7
p.3,4,5,6
Modification
2. PIN CONFIGURATION, Table2−1 Pad Layout
Driver supply voltage, CPU interface (FEATURES)
p.8
p.7
Modification
3. PIN FUNCTIONS
p.12
p.10,11
Modification
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF
UNUSED PINS
–
p.11
Deletion
p.13
p.12
Modification
5.1.1 Selection of interface type
Note 2, 3, 4
p.13
p.12
Modification
5.1.2 Selection of data transfer mode
p.14
p.13
Modification
5.1.3 Parallel interface
p.16
p.15
Modification
5.1.4 Serial interface
p.16
p.15
Modification
5.1.5 Chip select
p.17
p.15
Modification
5.1.6 Wait control in parallel interface mode
p.18
p.17
Modification
5.2.3 Y address circuit
p.18
p.18
Modification
Figure 5–7. µ PD161620 RAM addressing
p.20
p.20
Modification
5.4 Display Timing Generator
p.23
p.20
Modification
5.5 Common Adjustment Circuit
p.24
p.20
Modification
5.6 Square Wave Signal Generation Circuit
p.25
p.21
Modification
5.8 γ-Curve Correction Power Supply Circuit for Cases of
Unbalanced Driving, Figure5–14 γ-Curve correction circuit
p.26
–
Addition
p.27
p.22
Modification
Table5–7 γ-Curve correction circuit
5.9 Partial Display Mode, caution
p.41
–
Addition
p.45
p.36
Modification
6. RESET
5.11 Initialization Setting Sequence Example
p.46
p.37
Modification
7.1 Command List, Caution1
p.47, 48, 49,
50
p.38, 39
Modification
7.2 Command Explanation
p.51
p.40
Modification
Power supply voltage for γ-curve correction (Absolute Maximum
Ratings)
p.51
p.40
Modification
Power supply voltage, Input voltage (Recommended Operating
Conditions)
p.51
p.40
Addition
p.52
p.41
Modification
Electrical Specifications
p.53 to 61
p.42 to 50
Modification
Each table (AC Characteristics)
(e) Common
Notes1, 2 (Recommended Operating Conditions)
p.62
p.51
Modification
p.63, 64
–
Addition
9. CONNECTION of µ PD161620, 161640, and 161660
p.65
–
Addition
10. EXAMPLE of µ PD161620 and CPU CONNECTION
Preliminary Product Information S14797EJ3V7PM
67
µ PD161620
[MEMO]
68
Preliminary Product Information S14797EJ3V7PM
µ PD161620
[MEMO]
Preliminary Product Information S14797EJ3V7PM
69
µ PD161620
[MEMO]
70
Preliminary Product Information S14797EJ3V7PM
µ PD161620
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Product Information S14797EJ3V7PM
71