W83304D/W83304G Winbond ACPI Controller W83304D W83304G TM For AMD Claw Hammer CPU -1- Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G W83304D Data Sheet Revision History DATES VERSION VERSION ON WEB 1 June/04 0.50 N/A Preliminary Version 2 April/06 0.51 N/A Add Pb-free part no of W83304G PAGES MAIN CONTENTS 3 4 5 6 7 8 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -2- W83304D/W83304G Table of Content1. 2. 3. 4. 5. 6. 7. 8. 9. 10. GENERAL FUNCTION DESCRIPTION...................................................................................... 4 PIN-OUT...................................................................................................................................... 5 PIN DESCRIPTIONS .................................................................................................................. 6 BLOCK DIAGRAM ...................................................................................................................... 9 ELECTRICAL SPECIFICATION ............................................................................................... 10 5.1 AC CHARACTERISTICS.............................................................................................. 10 APPLICATION CIRCUIT........................................................................................................... 12 POWER SEQUENCE ............................................................................................................... 13 ORDERING INSTRUCTION ..................................................................................................... 14 HOW TO READ THE TOP MARKING...................................................................................... 14 PACKAGE DIMENSION ........................................................................................................... 15 -3- Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 1. GENERAL FUNCTION DESCRIPTION y y y y y y y y Provides Powers - 5V Active/Sleep (5VDL) - Provide a switch 5VDLEN pin to enable/disable 5VDL output in S5 state for USB application. - 3.3V Active/Sleep (3.3VDUAL) - Dual-Channel 2.5V Active/Sleep (2.5VSTR) for DDR - 1.5V for AGP 4X/8X Voltage - Two 1.25V~5V Linear Voltage Regulators Support VCC/VSTR/VDL/VSB Voltages - 1.25V DDR Bus Termination Regulated Voltage - 1.2V VLDT for AMD_K8 CPU Hyper transport. - 2.5VDDA for AMD_K8 PLL. - 1.25VREF for AMD_K8 reference. - Up to 0.3V/0.1V incremental voltage on DDR RAM for over-clocking application. Provides Signals for ATX Power Supply PS_ON# Control Support AMD K8 Claw Hammer Specific Power Up/Down Sequence Provides fault signal control. Internal Charge Pump Support Up to 9.5VSB Drive All N-Channel MOSFET Soft Start Under-Voltage Monitoring for VAGP, VRAM, VLDT, 3.3VDUAL Channels -4- W83304D/W83304G 36 35 34 33 32 31 30 29 28 27 26 VLDT_SEN VLDT_DRV 5VSB LR2_SEN LR2_DRV LR1_SEN LR1_DRV VAGP_SEN VAGP_DRV 3VSB_DRV 3VSB_SEN 5VDRV/3VDRV 2. PIN-OUT 25 5VUSB_DRV 37 24 GND C1 38 23 VDDIO_DRV1 C2 39 22 ISEN1 CHR_PMP 40 21 VDDIO_DRV2 5VSB 41 20 ISEN2 GND 42 19 VDDIO_SEN RSMRST# 43 18 VTT_DRV 5VDL_EN 44 17 VTT_SEN MISC_EN 45 16 VTT_SINK PWR_OK 46 15 ISET S3# 47 14 SS S5# 48 13 1.25VREF VDDIO_SET1 Fault# 8 9 -5- 10 11 12 GND VDDIO_SET0 7 2.5VDDA OV_CLK# 6 VCC3 5 VDD_EN 4 VDD_GD 3 PS_ON_OUT# 2 PS_ON_IN# 1 ALL_PWR_OK W83304D Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 3. PIN DESCRIPTIONS I/O12t I/O12ts O12 AO12 OD12 INt INts AIN NO 1 2 - TTL level bi-directional pin with 12 mA source-sink capability,open drain output - TTL level and schmitt trigger - Output pin with 12 mA source-sink capability - Output pin(Analog) with 12mA capability - Open-drain output pin with 12 mA sink capability - TTL level input pin - TTL level input pin and schmitt trigger - Input pin(Analog) NAME I/O ALL_PWR_OK OD24 OV_CLK# I POWER SOURCE FUNCTION DESCRIPTION 5VSB Power OK Signal. The signal is drove high to indicate all power ready. 5VSB H/W Trapping Pin for Over-Clocking Application. 1: Normal 0: +50mV is added on All regulated powers (VDDIO, VDDA, VAGP, VLDT, 1.25VREF ). VDDIO Output Voltage Setting Pin. VDDIO output with OV_CLK# = High 3 VDDIO_SET0 Its 5VSB VDDIO_SET1 VDDIO_SET0 2.5V 0 0 2.6V 0 1 2.7V 1 0 2.8V 1 1 VDDIO output with OV_CLK# = Low 4 VDDIO_SET1 Its 5 Fault# Its 6 PS_ON_IN# Its 7 PS_ON_OUT# OD12 5VSB VRAMSET1 VRAMSET0 2.55V 0 0 2.65V 0 1 2.75V 1 0 2.85V 1 1 System Fault Input Signal. Pull the pin low when any critical event alerted; the chip will shut the system down when the signal pulled low. ATX PS_ON# Signal Input. The PS_ON# signal of ATX power supply is routed through the chip for power fault control. -6- W83304D/W83304G Pin Descriptions, continued NO NAME I/O POWER SOURCE 8 VDD_GD I 5VSB CPU Power Good Signal. The signal is inputted for power sequence control. 9 VDD_EN OD24 5VSB Signal Output to Enable CPU Power. The signal output to enable CPU power for sequence control. 10 VCC3 P 11 2.5VDDA AO200mA 12 GND P 13 1.25VREF AO5mA 3VSB 1.25V Reference Voltage. 14 SS AI/AO 5VSB Soft-Start Pin. A capacitor (0.1u) is attached in this pin for soft-start slope rate adjustment. 15 ISET AI/AO 5VSB Reference Current Input. An input current for internal circuit reference. 16 VTT_SINK AO 5VSB 17 VTT_SEN AI 5VSB 18 VTT_DRV AO 9VSB 19 VDDIO_SEN AI 20 ISEN2 AI 21 VDDIO_DRV2 AO 22 ISEN1 AI 23 VDDIO_DRV1 AO 24 GND P 25 VLDT_SEN AI 5VSB 26 VLDT_DRV AO 9VSB 27 5VSB P 28 LR2_SEN AI 5VSB 29 LR2_DRV AO 9VSB 30 LR1_SEN AI 5VSB 31 LR1_DRV AO 9VSB FUNCTION DESCRIPTION Power VCC. VCC3 2.5V Power for CPU PLL Core. Power Ground. 9VSB Power VTT. A bi-direction linear regulator is provided to regulate voltage for DDR bus terminator. Power VDDIO. A dual-channels linear regulator with current balancing architecture is provided for higher current DDR SDRAM application. Power Ground. Power VLDT. 1.2V power for LDT bus. Standby Power Pin. Linear Regulator 1. A general purpose linear regulator is provided to generate 1.2V~5.0V power for specific device. Linear Regulator 2. A general purpose linear regulator is provided to generate 1.2V~5.0V power for specific device. -7- Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G Pin Descriptions, continued NO NAME I/O POWER SOURCE 32 VAGP_SEN AI 5VSB 33 VAGP_DRV AO 9VSB 34 3VSB_DRV AO 9VSB 35 3VSB_SEN AI 5VSB 36 5VDRV/3VDRV AO 9VSB 36 5VDRV/3VDRV AO 9VSB 37 5VUSB_DRV AO 9VSB 38 C1 I 5VSB 39 C2 I 5VSB 40 CHR_PMP P 5VSB 41 5VSB P 42 GND 43 RSMRST# FUNCTION DESCRIPTION Power for AGP Core. 1.5V power is regulated for AGP core. Power 3.3VDL. A linear regulator and switch is combined to generate 3V dual power. Power for USB Device. A 5V switch power is provided for USB device and can be programmed for various USB application with configuration of pin 44. Charge Pump Pins. It supports achieve 10mA driving current and insures output voltage 9.5V or above. Standby Power Pin. Power Ground. OD12 Signal to Indicate Status of Standby Power. The signal will be pulled high to indicate the standby power stable. 44 5VDL_EN I 5VSB 5VUSB Power Type Setting Pin. 5VUSB_EN=Low, support power for USB device in S0, S3 state. 5VUSB_EN =High, support power for USB device in S0, S3, S5 state. 45 MISC_EN OD24 5VSB Signal to Enable Miscellaneous Power. 46 PWR_OK Its 5VSB Power OK Signal form ATX Power Supply. 47 S3# I 48 S5# I ACPI Control Signals. -8- W83304D/W83304G S3# S5# PWR_OK# ALL_PWR_OK RSMRST# OV_CLK 5VUSB_EN MISC_EN VDD_GD VDD_EN VDDIO_SET0 VDDIO_SET1 PS_ON_IN# PS_ON_OUT# Fault# 4. BLOCK DIAGRAM CHR_PMP C1 C2 VLDT_DRV VLDT_SEN Charge Pump 1.2VLDT Control Logic SS ISET 3.3VDL 3VDRV 3.3VSB_DRV 3.3VSB_SEN 1.25VTT VTT_DRV VTT_SEN VTT SINK 1.25VREF 1.25VREF 5VUSB 5VDRV 5VSB_DRV 5VUSB_EN Soft Start Ref. Current 2.5VRAM Linear Regulator -9- 2.5VDDA VDDA_DRV Linear Regulator LR2_DRV LR2_SEN 1.5VAGP LR1_DRV LR1_SEN VAGP_DRV VAGP_SEN VDDIO_DRV1 ISEN1 VDDIO_SEN VDDIO_DRV2 ISEN2 Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 5. ELECTRICAL SPECIFICATION 5.1 AC CHARACTERISTICS Vcc=5V ± 5 %, TA = 0°C to +70°C PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS VAGP Linear Regulator Nominal Output Voltage 1.5 V OVA#=1 Nominal Output Voltage 1.55 V OVA#=0 Regulation 5 Under-Voltage Falling Threshold % 86.67 % 1.25VREF Nominal Output Voltage 1.25 Iload < 5mA; OVA#=1 Nominal Output Voltage 1.3 Iload < 5mA; OVA#=0 1.2VLDT Linear Regulator Nominal Output Voltage 1.2 V OVA#=1 Nominal Output Voltage 1.25 V OVA#=0 Regulation 5 Under-Voltage Falling Threshold VDDIO Regulator VRAMSET0 VRAMSET1 Under-Voltage Falling Threshold % 87.5 % VDDIO VOLTAGE SETTING OVA#=1 VRAMSET1 VRAMSET0 2.5V 0 0 2.6V 0 1 2.7V 1 0 2.8V 1 1 VDDIO VOLTAGE SETTING OVA#=0 VRAMSET1 VRAMSET0 2.55V 0 0 2.65V 0 1 2.75V 1 0 2.85V 1 1 84 Regulation % 5 - 10 - % W83304D/W83304G AC CHARACTERISTICS, continued Vcc=5V ± 5 %, TA = 0°C to +70°C PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS 2.5VDDA Nominal Output Voltage 2.5 Iload < 200mA; OVA#=1 Nominal Output Voltage 2.55 Iload < 200mA; OVA#=0 Nominal Output Voltage / V(VRAM2.5_SEN) 50 % Regulate a 1.25V for DDR bus termination Half of VDDIO voltage Nominal Output Voltage 1.25 V Bus Terminator 5VDUAL Switch Controller 5VDRV Output High Voltage 9 Cap Loading 5VSBDRV Output High Voltage 9 Cap Loading 5VUSB SS Sourcing Current 2.5 uA 78.79 % @ Soft-start 3.3VDual Under-Voltage Falling Threshold 5VDRV Output High Voltage 9 3VSBDRV 3.3 V Regulation Charge Pump Charge Pump Frequency Charge Pump Voltage 180 KHz 9.5 Two linear regulator Nominal Output Voltage Linear regulator from1.2V~5V - 11 - Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 6. APPLICATION CIRCUIT C2 1000U DUAL/VSB/STR/VCC VLR1=1.2/R3*(R1+R3) C1 100U Q1 1 3 DUAL/VSB/STR/VCC 3 VCC3 3 5VSB Q2 1 C3 47U Q3 1 C4 47U VLR2=1.2/R4*(R2+R4) C5 1000U C6 1500U Q5 Q4 VLR1 2 2 1 2 VAGP 3 2 VCC3 R1 R 1 C7 C R4 R C8 C R 3VDUAL 2 3 VLR2 R2 R R3 3VDUAL VCC3 3 W5VSB C10 1000U 5VSB Q7 1 C15 0.1U W5VSB RSMRST#(to SB) 5VDL_EN MISC_EN PWR_OK(from ATX) C18 5VSB 5VSB R11 4.7K S3# S5# 0.1U R13 4.7K C21 0.1U W83304D 5VSB 5VSB 5VSB VCC3 2 2 ISEN2 VDDIO 2 VDDIO_DRV1 ISEN1 VDDIO_DRV2 ISEN2 C17 3000U R7 4.7K VDDIO_SET0 VDDIO_SET1 Q11 1.25VREF(S0,S3) 5VSB R8 4.7K R9 4.7K (OPT) 1 R10 4.7K (OPT) 5VSB VDDIO_SET1 VDDIO_SET0 0 0 0 1 1 0 1 1 VDDIO 2.5V 2.6V 2.7V 2.8V C19 0.1U R12 100K VTT C20 1500U OV_CLK# R14 4.7K 5VSB R15 OV_CLK# 0 2.5VDDA,VDDIO,VLDT,AGP,1.25VREF ADD 4.7K 5OmV (OPT) 1 Normal 1 C22 1n C23 1n (OPT) (OPT) 5VDL_EN 2.5VDDA C25 1U C24 CAP R17 W5VSB 5VSB C26 1U VCC3 R21 4.7K R22 4.7K R23 4.7K - 12 - R16 4.7K 5VSB 5 R19 4.7K R20 4.7K R6 4m Q12 ALL_PWR_OK OV_CLK# VDDIO_SET0 VDDIO_SET1 Fault# PS_ON_IN#(connect to MB) PS_ON_OUT#(to ATX) VDD_GD VDD_EN VCC3 VDDIO_DRV2 3 C16 1500U 24 23 22 21 20 19 18 17 16 15 14 13 R5 4m ISEN1 0.1U GND VDDIO_DRV1 ISEN1 VDDIO_DRV2 ISEN2 VDDIO_SEN VTT_DRV VTT_SEN VTT_SINK ISET SS 1.25VREF 1 C12 2000U 2 5VUSB 5VUSB_DRV C1 C2 CHR_PMP 5VSB GND RSMRST# 5VDL_EN MISC_EN PWR_OK S3# S5# Q8 3 37 38 39 40 41 42 43 44 45 46 47 48 2 3 C14 2200p C13 VDDIO_DRV1 2 Q9 ALL_PWR_OK OV_CLK# VDDIO_SET0 VDDIO_SET1 Fault# PS_ON_IN# PS_ON_OUT# VDD_GD VDD_EN VCC3 2.5VDDA GND Q10 1 1.2VLDT 1 2 3 4 5 6 7 8 9 10 11 12 100U 5VDRV/3VDRV 3VSB_SEN 3VSB_DRV VAGP_DRV VAGP_SEN LR1_DRV LR1_SEN LR2_DRV LR2_SEN 5VSB VLDT_DRV VLDT_SEN U1 1 36 35 34 33 32 31 30 29 28 27 26 25 3 2 VCC5 C11 3 Q6 1 3 C9 1500U C27 1U R18 4.7K (OPT) 5VDL_EN 0 1 5VUSB STR DUAL W83304D/W83304G 7. POWER SEQUENCE W83304D power sequence(RUN_MISC default) 4.3 3.7 5VSB 82mS RSMRST# PSIN# S3# S5# PSOUT# VCC AGP 2.5VDDA PWROK RUN_MISC V TT &V RAM & 1.25VREF V CORE _EN V CORE _PG 1.2VLDT 1.2VLDT_PG ALLPWR_OK Note: 1. When at power up sequence, the delay time between adjacent power planes is 5ms after the previous power plane is power-good. 2. When at power down sequence, the delay time between adjacent power planes is 20ms after the previous power plane is power-down. 3. After 1.2VLDT_PG=H and delay 20ms, the ALLPWR_OK will be High(ALLPWR_OK=H). 4. All “LUV” detect is enabled after the power plane have power-good. - 13 - Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G 8. ORDERING INSTRUCTION PART NO. PACKAGE W83304D 48-pin LQFP W83304G 48-pin LQFP 9. HOW TO READ THE TOP MARKING inbond W83304D 214658302 310GBRA inbond W83304G 214658302 310GBRA 1st Line: Winbond Logo 2nd Line: Part_No W83304D, W83304G (Pb-free package) 3rd Line: lot no 4th Line: tracking code 310GBRA 310：date code,310 means package was made in ’03 week 10 G：Assembly ID, G means GR, A means ASE…etc. B：Chip Version, A means version A, B means version B RA：Winbond internal use - 14 - REMARKS Pb-free package W83304D/W83304G 10. PACKAGE DIMENSION HD D A A2 36 A1 25 37 24 48 13 HE E 1 12 b e c SEATING PLANE L Y θ L1 Controlling dimension : Millimeters Symbol A A1 A2 b c D E e HD HE L L1 Y 0 Dimension in inch Dimension in mm Min Nom Max Min Nom Max 0.002 0.004 0.006 0.05 0.053 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.010 0.15 0.20 0.25 0.004 0.006 0.008 0.10 0.15 0.20 0.272 0.276 0.280 6.90 7.00 7.10 0.272 0.276 0.280 6.90 7.00 7.10 0.020 0.026 0.35 0.50 0.65 0.014 0.10 0.15 0.350 0.354 0.358 8.90 9.00 9.10 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.004 0 - 15 - 7 0.10 0 7 Publication Release Date: April, 2006 Revision 0.51 W83304D/W83304G Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 16 -