WEDC WSF512K16

White Electronic Designs
WSF512K16-XXX
512KX16 SRAM/FLASH MODULE, SMD 5962-96901
FEATURES
Access Times of 35ns (SRAM) and 90ns (FLASH)
TTL Compatible Inputs and Outputs
Access Times of 70ns (SRAM) and 120ns (FLASH)
Packaging
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight - 13 grams typical
• 66 pin, PGA Type, 1.385" square HIP, Hermetic
Ceramic HIP (Package 402)
FLASH MEMORY FEATURES
• 68 lead, Hermetic CQFP (G2), 22mm (0.880")
square (Package 500). Designed to fit JEDEC 68
lead 0.990” CQFJ footprint (FIGURE 2)
100,000 Erase/Program Cycles
Sector Architecture
512Kx16 SRAM
• 8 equal size sectors of 64K bytes each
512Kx16 5V FLASH
Organized as 512Kx16 of SRAM and 512Kx16 of
Flash Memory with separate Data Busses
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
5 Volt Programming; 5V ± 10% Supply
Both blocks of memory are User Configurable as
1Mx8
Embedded Erase and Program Algorithms
Hardware Write Protection
Low Power CMOS
Commercial, Industrial and Military Temperature
Ranges
Page Program Operation and Internal Program
Control Time.
Note: Programming information available upon request.
FIGURE 1 – PIN CONFIGURATION
FOR WSF512K16-XH2X
Pin Description
Top View
1
12
SD8
23
SWE2#
34
SD15
45
VCC
FD8
56
FD15
SD9
SCS2#
SD14
FD9
FCS2#
FD14
SD10
GND
SD13
FD10
FWE2#
FD13
A13
SD11
SD12
A6
FD11
FD12
A14
A10
OE#
A7
A3
A0
A15
A11
A17
NC
A4
A1
A16
A12
SWE1#
A8
A5
A2
FD0-15
Flash Data Inputs/Outputs
SD0-15
SRAM Data Inputs/Outputs
A0-18
Address Inputs
SWE1-2#
SRAM Write Enable
SCS1-2#
SRAM Chip Selects
OE#
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
FWE1-2#
Flash Write Enable
FCS1-2#
Flash Chip Select
Block Diagram
S W E 1 # S CS 1 #
11
A18
VCC
SD7
A9
FWE1#
FD7
SD0
SCS1#
SD6
FD0
FCS1#
FD6
SD1
NC
SD5
FD1
GND
FD5
SD2
SD3
SD4
FD2
FD3
FD4
512K x 8
SRAM
22
33
44
55
S W E 2 # S CS 2 #
F W E 1 # F CS 1 #
F W E 2 # F CS 2 #
OE#
A0-18
66
512K x 8
SRAM
512K x 8
FLASH
512K x 8
FLASH
8
8
8
8
SD0-7
SD8-15
FD0-7
FD8-15
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
1
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White Electronic Designs
WSF512K16-XXX
FIGURE 2 – PIN CONFIGURATION FOR WSF512K16-XG2X
Pin Description
NC
A0
A1
A2
A3
A4
A5
FCS1#
GND
FCS2#
SWE1#
A6
A7
A8
A9
A10
VCC
Top View
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
GND
FD8
FD9
FD10
FD11
FD12
FD13
FD14
FD15
Flash Data Inputs/Outputs
SD0-15
SRAM Data Inputs/Outputs
A0-18
Address Inputs
SWE1-2#
SRAM Write Enable
SCS1-2#
SRAM Chip Selects
OE#
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
FWE1-2#
Flash Write Enable
FCS1-2#
Flash Chip Select
NC
NC
A18
A17
SWE2#
FWE1#
FWE2#
OE#
SCS2#
A16
SCS1#
A15
A14
A13
A12
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VCC
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
FD0-15
Block Diagram
S W E 1 # S CS 1 #
S W E 2 # S CS 2 #
F W E 1 # F CS 1 #
F W E 2 # F CS 2 #
OE#
A0-18
512K x 8
SRAM
512K x 8
SRAM
512K x 8
FLASH
512K x 8
FLASH
8
8
8
8
SD0-7
SD8-15
FD0-7
FD8-15
The WEDC 68 lead G2 CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2 has the TCE
and lead inspection advantage of
the CQFP form.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
2
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White Electronic Designs
WSF512K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Operating Temperature
TA
Storage Temperature
TSTG
Signal Voltage Relative to GND
VG
Junction Temperature
TJ
Supply Voltage
VCC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
7.0
150
7.0
SRAM TRUTH TABLE
Unit
°C
°C
V
°C
V
SCS#
H
L
L
L
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
TA = +25°C
20 years
100,000
Test
OE# Capacitance
F/S WE1-2# Capacitance
F/S CS1-2# Capacitance
Data I/O Capacitance
Address Input Capacitance
NOTES: 1. Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIH
VIL
SWE#
X
H
H
L
CAPACITANCE
Parameter
Flash Data Retention
Flash Endurance (write/erase cycles)
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
OE#
X
L
H
X
Min
4.5
2.2
-0.5
Max
5.5
VCC + 0.3
+0.8
Symbol
COE
CWE
CCS
CI/O
CAD
Condition
Max Unit
VIN = 0V, f = 1.0MHz 50 pF
VIN = 0V, f = 1.0MHz 20 pF
VIN = 0V, f = 1.0MHz 20 pF
VIN = 0V, f = 1.0MHz 20 pF
VIN = 0V, f = 1.0MHz 50 pF
This parameter is guaranteed by design but not tested.
Unit
V
V
V
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 16 Mode
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash VCC Active Current for Read (1)
Flash VCC Active Current for Program or Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Low VCC Lock Out Voltage
Symbol
ILI
ILO
ICCx16
ISB
VOL
VOH
ICC1
ICC2
VOL
VOH1
VLKO
Conditions
VCC = 5.5, VIN = GND to VCC
SCS# = VIH, OE# = VIH, VOUT = GND to VCC
SCS# = VIL, OE# = FCS# = VIH, f = 5MHz, VCC = 5.5
FCS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 6mA, VCC = 4.5
IOH = -1.0mA, VCC = 4.5
FCS# = VIL, OE# = SCS# = VIH
FCS# = VIL, OE# = SCS# = VIH
IOL = 8.0mA, VCC = 4.5
IOH = -2.5 mA, VCC = 4.5
Min
Max
10
10
330
45
0.4
2.4
130
150
0.45
0.85 x VCC
3.2
4.2
Unit
µA
µA
mA
mA
V
V
mA
mA
V
V
V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
3
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White Electronic Designs
WSF512K16-XXX
SRAM AC CHARACTERISTICS
SRAM AC CHARACTERISTICS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
tRC
tAA
tOH
tACS
tOE
tCLZ1
tOLZ1
tCHZ1
tOHZ1
-35
-70
Min Max Min Max
35
70
35
70
0
5
35
70
25
35
4
10
0
5
15
25
15
25
Parameter
Write Cycle
Unit
Symbol
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
tWC
tCW
tAW
tDW
tWP
tAS
tAH
tOW1
tWHZ1
tDH
-35
-70
Min Max Min Max
35
70
25
60
25
60
20
30
25
50
0
0
0
5
0
5
15
25
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
FIGURE 3
AC Test Circuit
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
≈
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
Unit
V
ns
V
V
Notes: VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
4
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WSF512K16-XXX
FIGURE 4 – SRAM TIMING WAVEFORM — READ CYCLE
tRC
ADDRESS
tAA
tRC
SCS#
ADDRESS
tAA
tCLZ
tOH
DATA I/O
tCHZ
tACS
PREVIOUS DATA VALID
SOE#
DATA VALID
tOE
tOLZ
READ CYCLE 1 (SCS# = OE# = VIL, SWE# = VIH)
DATA I/O
tOHZ
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2 (SWE# = VIH)
FIGURE 5 – SRAM WRITE CYCLE — SWE# CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
SCS#
tAS
tWP
SWE#
tOW
tWHZ
tDW
DATA I/O
tDH
DATA VALID
WRITE CYCLE 1, SWE# CONTROLLED
FIGURE 6 – SRAM WRITE CYCLE — SCS# CONTROLLED
tWC
ADDRESS
tAS
tAW
tAH
tCW
SCS#
tWP
SWE#
tDW
DATA I/O
tDH
DATA VALID
WRITE CYCLE 2, SCS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
5
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White Electronic Designs
WSF512K16-XXX
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FWE# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
-90
Symbol
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time Before Write
VCC Set-up Time
Chip Programming Time
Chip Select Hold Time
Chip Erase Time (3)
tAVAV
tELWL
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tGHWL
tWC
tCS
tWP
tAS
tDS
tDH
tAH
tWPH
Min
90
0
45
0
45
0
45
20
-120
Max
Min
120
0
50
0
50
0
50
20
Max
300
15
tVCS
0
50
tOEH
10
300
15
0
50
11
11
10
64
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
µs
sec
ns
sec
NOTES:
1. Typical value for tWHWH1 is 7ns.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
FLASH AC CHARACTERISTICS – READ ONLY OPERATIONS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
OE# to Output Valid
Chip Select to Output High Z (1)
OE# High to Output High Z (1)
Output Hold from Address, CS# or OE# Change, whichever is first
-90
Symbol
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
tOE
tDF
tDF
tOH
Min
90
-120
Max
Min
120
90
90
35
20
20
0
Max
120
120
50
30
30
0
Unit
ns
ns
ns
ns
ns
ns
ns
1. Guaranteed by design, not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WSF512K16-XXX
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FCS# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle Time
FWE# Setup Time
FCS# Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
FCS# Pulse Width High
Duration Of Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
-970
Symbol
tAVAV
tWLEL
tELEH
tAVEL
tDVEH
tEHDX
tELAX
tEHEL
tWC
tWS
tCP
tAS
tDS
tDH
tAH
tCPH
tWHWH1
tWHWH2
tGHEL
Min
90
0
45
0
45
0
45
20
-120
Max
Min
120
0
50
0
50
0
50
20
300
15
0
Max
300
15
0
11
64
11
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
sec
sec
NOTES:
1. Typical value for tWHWH1 is 7ns.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
7
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White Electronic Designs
WSF512K16-XXX
FIGURE 7 – AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS
tRC
Addresses
Addresses Stable
tACC
FCS#
tDF
tOE
OE#
FWE#
Outputs
tCE
tOH
High Z
Output Valid
High Z
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
8
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White Electronic Designs
WSF512K16-XXX
FIGURE 8 – WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE# CONTROLLED
Data# Polling
Addresses
5555H
PA
tWC
tAS
PA
tAH
tRC
FCS#
tGHWL
OE#
tWP
FWE#
tWHWH1
tWPH
tCS
tDH
A0H
Data
tDF
tOE
D7#
PD
DOUT
tDS
tOH
5.0 V
tCE
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
9
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White Electronic Designs
WSF512K16-XXX
FIGURE 9 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY
tAS
Addresses
5555H
tAH
2AAAH
5555H
5555H
2AAAH
SA
FCS#
tGHWL
OE#
tWP
FWE#
tWPH
tCS
Data
tDH
AAH
55H
80H
AAH
55H
10H/30H
tDS
VCC
tVCS
Note: SA is the sector address for Sector Erase.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
10
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White Electronic Designs
WSF512K16-XXX
FIGURE 10 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM
OPERATIONS FOR FLASH MEMORY
t CH
FCS#
t DF
t OE
OE#
tOEH
FWE#
tCE
t OH
D7 =
Valid Data
D7#
D7
High Z
tWHWH 1 or 2
D0-D7
Valid Data
D0-D6 = Invalid
D0-D6
t OE
D7
Valid Data
D7
D7
High Z
tWHWH 1 or 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
11
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White Electronic Designs
WSF512K16-XXX
FIGURE 11 – WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS# CONTROLLED
Data# Polling
Addresses
5555H
PA
tWC
tAS
PA
tAH
FWE#
tGHEL
OE#
tCP
FCS#
tWHWH1
tCPH
tWS
tDH
A0H
Data
D7#
PD
DOUT
tDS
5.0 V
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
12
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White Electronic Designs
WSF512K16-XXX
PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
35.2 (1.385) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
5.7 (0.223)
MAX
3.81 (0.150)
± 0.1 (0.005)
1.27 (0.050) ± 0.1 (0.005)
0.76 (0.030) ± 0.1 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WSF512K16-XXX
PACKAGE 500: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2)
The WEDC 68 lead G2 CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2 has the TCE
and lead inspection advantage of
the CQFP form.
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
14
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White Electronic Designs
WSF512K16-XXX
ORDERING INFORMATION
W S F 512K16 - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGE TYPE:
H2 = Ceramic Hex In-line Package, HIP (Package 402)
G2 = 22 mm Ceramic Quad Flat Pack, CQFP (Package 500)
ACCESS TIME (ns)
39 = 35ns SRAM and 90ns FLASH
72 = 70ns SRAM and 120ns FLASH also available
ORGANIZATION, 512K x 16
FLASH
SRAM
WHITE ELECTRONIC DESIGNS CORP.
DEVICE TYPE
SRAM SPEED
FLASH SPEED
PACKAGE
SMD NO.
512K x 16 Mixed Module
70ns
120ns
66 pin HIP (H2)
5962-96901 01HXX
512K x 16 Mixed Module
35ns
90ns
66 pin HIP (H2)
5962-96901 02HXX
512K x 16 Mixed Module
70ns
120ns
68 lead CQFP/J (G2)
5962-96901 01HMX
512K x 16 Mixed Module
35ns
90ns
68 lead CQFP/J (G2)
5962-96901 02HMX
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2006
Rev. 6
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com