CY7C1339F 4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K × 32 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) — 4.5 ns (for 100-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages • “ZZ” Sleep Mode Option Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1339F operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram A 0, A 1, A A DDRESS REGISTER 2 A [1:0] M ODE A DV CLK Q1 BURST COUNTER CLR A ND Q0 LOGIC A DSC A DSP BW D DQ D BYTE W RITE REGISTER DQ D BYTE W RITE DRIVER BW C DQ C BYTE W RITE REGISTER DQ C BYTE W RITE DRIVER DQ B BYTE W RITE REGISTER DQ B BYTE W RITE DRIVER BW B BW A BW E ZZ ENA BLE REGISTER SENSE A M PS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQ A BYTE W RITE DRIVER DQ A BYTE W RITE REGISTER GW CE 1 CE 2 CE 3 OE M EM ORY A RRA Y INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL 1 Note: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05217 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 09, 2004 CY7C1339F Selection Guide 250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access Time 2.6 2.6 2.8 3.5 4.0 4.5 ns Maximum Operating Current 325 290 265 240 225 205 mA Maximum CMOS Standby Current 40 40 40 40 40 40 mA Shaded areas contain advanced information. Please contact your local Cypress sales representative for availability of these parts. BYTE C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100-pin TQFP CY7C1339F 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC BYTE B BYTE A Document #: 38-05217 Rev. *C NC NC VSS VDD NC NC A A A A A A A MODE A A A A A1 A0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BYTE D NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Pin Configurations Page 2 of 17 CY7C1339F Pin Configurations (continued) 119-ball BGA CY7C1339F (128K × 32) 1 2 3 4 5 6 7 VDDQ A NC NC CE2 A A ADSP A A ADSC VDD A A VDDQ A A NC A NC NC D E DQC DQC NC DQC VSS VSS NC CE1 VSS VSS NC DQB DQB DQB F G H J VDDQ DQC DQC VDDQ DQC DQC DQC VDD VSS BWc VSS NC OE ADV GW VDD VSS BWB VSS NC DQB DQB DQB VDD VDDQ DQB DQB VDDQ K DQD DQD VSS CLK VSS DQA DQA L DQD DQD BWD NC BWA DQA DQA M N VDDQ DQD DQD DQD VSS VSS BWE A1 VSS VSS DQA DQA VDDQ DQA P DQD NC VSS A0 VSS NC DQA R T NC NC A MODE VDD A A NC A A NC NC NC ZZ U VDDQ NC NC NC NC NC VDDQ A B C Pin Definitions BGA TQFP I/O Description A0, A1, A Name P4,N4, A2,C2,R2, A3,B3,C3, T3,T4,A5, B5,C5,T5, A6,C6,R6 37,36, 32,33,34, 35,44,45, 46,47,48, 49,50,81, 82,99, 100 InputSynchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 are fed to the two-bit counter.. BWA,BWB L5,G5,G3, L3 93,94,95, 96 InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW H4 88 InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). BWE M4 87 InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK K4 89 InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. E4 98 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. B2 97 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. BWC,BWD CE1 CE2 Document #: 38-05217 Rev. *C Page 3 of 17 CY7C1339F Pin Definitions (continued) Name BGA TQFP I/O CE3 - 92 InputSynchronous OE F4 86 ADV G4 83 InputSynchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. A4 84 InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC B4 85 InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ T7 64 InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device Asynchronous in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs K6,L6,M6, N6,K7,L7, N7,P7,E6, F6,G6,H6, D7,E7,G7, H7,D1,E1, G1,H1,E2, F2,G2,H2, K1,L1,N1, P1,K2,L2, M2,N2 52,53,56, 57,58,59, 62,63,68, 69,72,73, 74,75,78, 79,2,3,6, 7,8,9,12, 13,18,19, 22,23,24, 25,28,29 I/OSynchronous VDD J2,J4,R4 15,41,65, 91 Power Supply Power supply inputs to the core of the device. VSS D3,E3,F3, K3,M3,N3, P3,D5,E5, F5,H5,K5, M5,N5,P5 17,40,67, 90 Ground Ground for the core of the device. VDDQ A1,F1,J1, M1,U1,A7, F7,J7,M7, U7 4,11,20, 27,54,61, 70,77 I/O Power Supply Power supply for the I/O circuitry. VSSQ - 5,10,21, 26,55,60, 71,76 I/O Ground Ground for the I/O circuitry. R3 31 InputStatic ADSP MODE Document #: 38-05217 Rev. *C Description Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. InputOutput Enable, asynchronous input, active LOW. Controls the Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a three-state condition. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Page 4 of 17 CY7C1339F Pin Definitions (continued) Name NC BGA TQFP B1,C1,R1, T1,D2,P2, T2,U2,J3, U3,D4,L4, U4,J5,U5, B6,D6,P6, T6,U6,B7, C7,R5,R7 1,14,16, 30,38,39, 42,43,51, 66,80 I/O Description No Connects. Not internally connected to the die Functional Overview Single Write Accesses Initiated by ADSP All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.5 ns (166-MHz device). This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. The CY7C1339F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Document #: 38-05217 Rev. *C ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BW[A:D] signals. The CY7C1339F provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1339F is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1339F is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Page 5 of 17 CY7C1339F Burst Sequences Interleaved Burst Address Table (MODE = Floating or VDD) The CY7C1339F provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. IDDZZ Snooze mode standby current ZZ > VDD – 0.2V tZZS Device operation to ZZ ZZ > VDD – 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to snooze current This parameter is sampled tRZZI ZZ Inactive to exit snooze current This parameter is sampled Max. Unit 40 mA 2tCYC ns 2tCYC ns 2tCYC 0 ns ns Truth Table[ 2, 3, 4, 5, 6, 7] Operation Add. Used CE1 CE2 CE3 ZZ H X X L Deselect Cycle, Power-down None Deselect Cycle, Power-down None L L X L Deselect Cycle, Power-down None L X H Deselect Cycle, Power-down None L L X DQ WRITE OE CLK X X L-H three-state ADSP X ADSC L ADV X L X X X X L-H three-state L L X X X X L-H three-state L H L X X X L-H three-state Deselect Cycle, Power-down None L X H L H L X X X L-H three-state Snooze Mode, Power-down None X X X H X X X X X X three-state READ Cycle, Begin Burst External L H L L L X X X L L-H Q READ Cycle, Begin Burst External L H L L L X X X H L-H three-state WRITE Cycle, Begin Burst External L H L L H L X L X L-H D READ Cycle, Begin Burst External L H L L H L X H L L-H Q READ Cycle, Begin Burst External L H L L H L X H H L-H three-state Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05217 Rev. *C Page 6 of 17 CY7C1339F Truth Table[ 2, 3, 4, 5, 6, 7] Operation Add. Used READ Cycle, Continue Burst Next CE1 CE2 CE3 ZZ X X X L READ Cycle, Continue Burst Next H X X READ Cycle, Continue Burst Next H X X WRITE Cycle, Continue Burst Next X X WRITE Cycle, Continue Burst Next H X DQ WRITE OE CLK H H L-H three-state ADSP H ADSC H ADV L L X H L H L L-H Q L X H L H H L-H three-state X L H H L L X L-H D X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H three-state READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H three-state WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D Partial Truth Table for Read/Write[2, 8] Function Read GW H BWE H BWD X BWC X BWB X BWA X Read H L H H H H Write Byte A – DQA Write Byte B – DQB H L H H H L H L H H L H Write Bytes B, A H L H H L L Write Byte C– DQC H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D– DQD H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Notes: 8. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05217 Rev. *C Page 7 of 17 CY7C1339F Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Range Ambient Temperature DC Voltage Applied to Outputs in three-state ....................................... –0.5V to VDDQ + 0.5V Commercial 0°C to +70°C Industrial DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range Parameter Description VDD VDDQ 3.3V –5%/+10% 2.5V –5% to VDD –40°C to +85°C [9, 10] Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.6 V VDDQ I/O Supply Voltage 2.375 VDD V VOH Output HIGH Voltage VOL VIH VIL IX Output LOW Voltage Input HIGH Input LOW Voltage[9] Voltage[9] Input Load Current except ZZ and MODE VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 V VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V VDDQ = 3.3V 2.0 VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA GND ≤ VI ≤ VDDQ Input = VDD Input Current of ZZ 5 Input = VSS IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VDD Operating Supply Current ISB1 ISB2 Automatic CE Power-down Current—TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC Automatic CE VDD = Max, Device Deselected, Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V, Current—CMOS Inputs f = 0 µA µA –5 Input = VDD IDD µA –30 Input Current of MODE Input = VSS 30 µA 5 µA 4-ns cycle, 250 MHz 325 mA 4.4-ns cycle, 225 MHz 290 mA 5-ns cycle, 200 MHz 265 mA 6-ns cycle, 166 MHz 240 mA 7.5-ns cycle, 133 MHz 225 mA 10-ns cycle, 100 MHz 205 mA 4-ns cycle, 250 MHz 120 mA 4.4-ns cycle, 225 MHz 115 mA 5-ns cycle, 200 MHz 110 mA 6-ns cycle, 166 MHz 100 mA 7.5-ns cycle, 133 MHz 90 mA –5 10-ns cycle, 100 MHz 80 mA All speeds 40 mA Shaded area contains advanced information. Notes: 9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 10. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05217 Rev. *C Page 8 of 17 CY7C1339F Electrical Characteristics Over the Operating Range (continued)[9, 10] Parameter ISB3 Description Test Conditions Min. Max. Unit 105 mA 100 mA 95 mA 6-ns cycle, 166 MHz 85 mA 7.5-ns cycle, 133 MHz 75 mA Automatic CE VDD = Max, Device Deselected, or 4-ns cycle, 250 MHz Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V 4.4-ns cycle, 225 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 5-ns cycle, 200 MHz ISB4 VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 Automatic CE Power-down Current—TTL Inputs 10-ns cycle, 100 MHz 65 mA All Speeds 45 mA Shaded areas contain advance information. Thermal Resistance[11] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions TQFP Package BGA Package Unit 41.83 47.63 °C/W 9.99 11.71 °C/W Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. Capacitance[11] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TQFP Package Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V BGA Package Unit 5 5 pF 5 5 pF 5 7 pF AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω VT = 1.5V (a) GND 5 pF R = 351Ω INCLUDING JIG AND SCOPE OUTPUT RL = 50Ω ≤ 1ns (c) ALL INPUT PULSES VDDQ GND 5 pF R =1538Ω VT = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% ≤ 1ns R = 1667Ω 2.5V OUTPUT (a) 10% (b) 2.5V I/O Test Load Z0 = 50Ω ALL INPUT PULSES VDDQ (b) 10% 90% 10% 90% ≤ 1ns ≤ 1ns (c) Note: 11. Tested initially and after any design or process change that may affect these parameters Document #: 38-05217 Rev. *C Page 9 of 17 CY7C1339F Switching Characteristics Over the Operating Range[16, 17] 250 MHz Parameter tPOWER 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max Unit Description VDD(Typical) to the first Access[12] 1 1 1 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 4.4 5.0 6.0 7.5 10 ns tCH Clock HIGH 1.7 2.0 2.0 2.5 3.0 3.5 ns tCL Clock LOW 1.7 2.0 2.0 2.5 3.0 3.5 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise tCLZ Clock to Low-Z[13, 14, 15] tCHZ High-Z[13, 14, 15] tOEV tOELZ Clock to OE LOW to Output Valid OE LOW to Output Low-Z[13, 14, 15] 2.6 2.8 3.5 4.0 4.5 ns 1.0 1.0 1.0 2.0 2.0 2.0 ns 0 0 0 0 0 0 ns 2.6 2.6 2.8 3.5 4.0 4.5 ns 2.6 2.6 2.8 3.5 4.5 4.5 ns 0 [13, 14, 15] tOEHZ 2.6 0 2.6 OE HIGH to Output High-Z Set-up Times 0 2.6 0 2.8 0 3.5 0 4.0 ns 4.5 ns tAS Address Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tADS ADSC, ADSP Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tADVS ADV Set-up Before CLK Rise GW, BWE, BW[A:D] Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tWES 0.8 1.2 1.2 1.5 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns tADH 0.4 0.5 0.5 0.5 0.5 0.5 ns 0.4 0.5 0.5 0.5 0.5 0.5 ns 0.4 0.5 0.5 0.5 0.5 0.5 ns tDH ADSP , ADSC Hold After CLK Rise ADV Hold After CLK Rise GW,BWE, BW[A:D] Hold After CLK Rise Data Input Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns Hold Times tADVH tWEH Shaded areas contain advance information. Notes: 12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 15. This parameter is sampled and not 100% tested. 16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 17. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05217 Rev. *C Page 10 of 17 CY7C1339F Switching Waveforms Read Cycle Timing[18] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BW[A:D] tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) High-Z Q(A1) tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Notes: 18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document #: 38-05217 Rev. *C Page 11 of 17 CY7C1339F Switching Waveforms (continued) Write Cycle Timing[18, 19] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BW[A :D] tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Document #: 38-05217 Rev. *C Extended BURST WRITE UNDEFINED Page 12 of 17 CY7C1339F Switching Waveforms (continued) Read/Write Cycle Timing[18, 20, 21] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BW[A:D] tCES tCEH CE ADV OE tDS tCO tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Note: 20. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 21. GW is HIGH. Document #: 38-05217 Rev. *C Page 13 of 17 CY7C1339F Switching Waveforms (continued) ZZ Mode Timing [22, 23] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 250 Ordering Code CY7C1339F-250AC CY7C1339F-250BGC CY7C1339F-250AI 225 A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial BG119 A101 BG119 A101 BG119 A101 CY7C1339F-225BGI BG119 CY7C1339F-200AC A101 CY7C1339F-200BGC CY7C1339F-200AI BG119 A101 CY7C1339F-200BGI BG119 CY7C1339F-166AC A101 CY7C1339F-166BGC CY7C1339F-166AI 133 Operating Range CY7C1339F-225AC CY7C1339F-225AI 166 Package Type CY7C1339F-250BGI CY7C1339F-225BGC 200 Package Name BG119 A101 CY7C1339F-166BGI BG119 CY7C1339F-133AC A101 CY7C1339F-133BGC CY7C1339F-133AI CY7C1339F-133BGI BG119 A101 BG119 119-ball BGA (14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial 119-ball BGA (14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial 119-ball BGA(14 x 22 x 2.4mm) Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 23. DQs are in high-Z when exiting ZZ sleep mode Document #: 38-05217 Rev. *C Page 14 of 17 CY7C1339F Ordering Information (continued) Speed (MHz) 100 Ordering Code CY7C1339F-100AC CY7C1339F-100BGC CY7C1339F-100AI CY7C1339F-100BGI Package Name Package Type Operating Range A101 100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial BG119 A101 BG119 119-ball BGA(14 x 22 x 2.4mm) 100-lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial 119-ball BGA(14 x 22 x 2.4mm) Shaded areas contain advanced information. Please contact your local Cypress sales representative for availability of these parts. Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A 51-85050-*A Document #: 38-05217 Rev. *C Page 15 of 17 CY7C1339F Package Diagrams (continued) 51-85115-*B i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-05217 Rev. *C Page 16 of 17 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1339F Document History Page Document Title: CY7C1339F 4-Mbit (128K x 32) Pipelined Sync SRAM Document Number: 38-05217 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 119284 01/06/03 HGK New Data Sheet *A 123850 01/18/03 AJH Added power-up requirements to AC test loads and waveforms information *B 200660 See ECN REF Final Data Sheet *C 213342 See ECN VBL Update Ordering Info section: unshade active parts. -133AI & BGI Document #: 38-05217 Rev. *C Page 17 of 17