PD84002 RF power transistor The LdmoST plastic family Features ■ Excellent thermal stability ■ Common source configuration ■ Broadband performances POUT = 2 W with 13 dB gain @ 870 MHz ■ Plastic package ■ ESD protection ■ Supplied in tape and reel ■ In compliance with the 2002/95/EC european directive SOT-89 Figure 1. Pin connection Description Source The PD84002 is a common source N-channel, enhancement-mode lateral Field-Effect RF power transistor. It is designed for high gain, broad band commercial and industrial applications. It operates at 7 V in common source mode at frequencies of up to 1 GHz. PD84002’s superior gain and efficiency makes it an ideal solution for portable radio and UHF RFID reader. Figure 2. Source Gate Drain Device summary Order code Marking Package Packaging PD84002 8402 SOT-89 Tape and reel December 2007 Rev 1 1/16 www.st.com 16 Contents PD84002 Contents 1 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 ESD protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 DC curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 RF curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Schematic and BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 2/16 8.1 Thermal Pad and Via design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.2 Soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PD84002 Electrical data 1 Electrical data 1.1 Maximum ratings Table 1. Absolute maximum ratings (TCASE = 25°C) Symbol Value Unit V(BR)DSS Drain-source voltage 25 V VGS Gate-source voltage -0.5 to +15 V Drain current 2 A Power dissipation 6 W 150 °C -65 to +150 °C Value Unit 21 °C/W ID PDISS TJ TSTG 1.2 Parameter Max. operating junction temperature Storage temperature Thermal data Table 2. Symbol RthJC Thermal data Parameter Junction - case thermal resistance 3/16 Electrical characteristics 2 PD84002 Electrical characteristics TCASE = +25 oC 2.1 Static Table 3. Static Symbol 2.2 Test conditions Min VDS = 25 V 1 µA IGSS VGS = 5 V VDS = 0 V 1 µA VGS(Q) VDS = 7.5 V VDS(ON) VGS = 10 V ID = 0.25 A CISS VGS = 0 V VDS = 7.5 V COSS VGS = 0 V CRSS VGS = 0 V ID = 100 mA 3.9 V 0.27 V f = 1 MHz 16 pF VDS = 7.5 V f = 1 MHz 16 pF VDS = 7.5 V f = 1 MHz 1.2 pF Dynamic Dynamic Test conditions Min Typ Max Unit POUT VDD = 7.5 V, IDQ = 100 mA, PIN = 0.1 W, f = 870 MHz 2 GPS VDD = 7.5 V, IDQ = 100 mA, POUT = 2 W, f = 870 MHz 13 15 dB ND VDD = 7.5 V, IDQ = 100 mA, POUT = 2 W, f = 870 MHz 60 65 % Load VDD = 7.5 V, IDQ = 100 mA, POUT = 2 W, f = 870 MHz mismatch All phase angles W 20:1 VSWR ESD protection characteristics Table 5. ESD protection characteristics Test conditions Class Human body model 2 Machine model M3 Moisture sensitivity level Table 6. 4/16 Unit VGS = 0 V Symbol 2.4 Max IDSS Table 4. 2.3 Typ Moisture sensitivity level Test methodology Rating J-STD-020B MSL 3 PD84002 3 Impedances Impedances Figure 3. Impedances Table 7. Impedances F(MHz) ZGS ZDL 860 1,80 + j 7,79 3,88 + j 2,41 870 1,84 + j 7,96 3,89 + j 2,69 880 1,83 + j 8,01 4,01+ j 2,96 890 1,76 + j 8,11 4,17 + j 3,16 900 1,70 + j 8,20 4,27 + j 3,32 910 1,63 + j 8,30 4,37 + j 3,40 920 1,57 + j 8,48 4,41 + j 3,46 930 1,43 + j 8,64 4,36 + j 3,51 940 1,41 + j 8,83 4,28 + j 3,51 5/16 DC curves 4 PD84002 DC curves Figure 4. DC output characteristics Figure 5. ID vs VGS ID vs Vgs VGS=10V VGS=9V VGS=8V VGS=7V PD84002 VGS=6V VGS=5V VGS=4V Figure 6. Capacitances vs drain voltage 30 Capacitance (pF) 25 CRSS COSS CISS 20 15 10 5 0 0 2 4 6 8 Vdd (V) 6/16 10 12 14 16 PD84002 RF curves RF curves Figure 7. Output power and efficiency vs frequency 7.2 V / 100 mA / Pin = 19 dBm Figure 8. 18 4 60 16 3 50 2 40 0 820 Pout 840 860 880 900 920 14 12 30 Eff 940 960 980 10 20 1000 8 820 Freq (MHz) Figure 9. Input return loss vs frequency 7.2 V / 100 mA Harmonics (dB) 0 -10 -10 IRL (dB) 860 880 900 920 940 960 980 1000 Figure 10. Harmonics vs frequency 7.2 V / 100 mA -5 -15 Pin=19 dBm -25 -30 -35 820 840 Freq (MHz) 0 -20 Pin = 19dBm Gain (dB) 70 1 Gain vs frequency 7.2 V - 100 mA 7.2V 100mA 5 Efficiency (%) Pout (W) 5 H2 H3 -20 -30 -40 -50 -60 -70 840 860 880 900 920 940 960 980 1000 Freq (MHz) -80 820 840 860 880 900 920 940 960 980 1000 Freq (MHz) 7 70 6 60 5 50 4 40 3 30 2 Pout 20 Id 1 0 820 Efficiency (%) Pout (W) Figure 11. Output power and efficiency vs frequency 9 V / 100 mA / Pin = 22 dBm 10 0 840 860 880 900 920 940 960 980 1000 Freq (MHz) 7/16 Schematic and BOM 6 PD84002 Schematic and BOM Figure 12. Schematic Vcc 1+ MSub 2- R3 B2 B1 C3 FR4 H=20 mil R2 C1 L1 C2 R1 TL4 RFin TL1 C4 TL2 C6 Table 8. C10 C5 RFout C11 TL3 C8 LDMOS PD84002 Components part list Component ID Description B1 8/16 C7 TL6 TL5 C9 Value Case size Manufacturer Part Code Ferrite Bead Panasonic EXCELDRC35C B2 Ferrite Bead Panasonic EXCELDRC35C C1, C2 Capacitor 120 pF 0603 Murata GRM39-C0G121J50D500 C3 Capacitor 1 uF 0603 Murata GRM39-X5R105K16D52K C4, C5 Capacitor 39 pF 0603 Murata GRM39-C0G390J50D500 C6, C10 Capacitor 3.3 pF 0603 Murata GRM39-C0G3R3C50Z500 C7 Capacitor 8.2 pF 0603 Murata GRM39-C0G8R2D50Z500 C8 Capacitor 22 pF 0603 Murata GRM39-C0G220J50D500 C9 Capacitor 12 pF 0603 Murata GRM39-C0G120J50D500 C11 Capacitor 2.7 pF 0603 Murata GRM39-C0G2R7C50Z500 L1 Inductor 12.55 nH Coilcraft 1606-10 R1 Resistor 150 Ω R2 Potentiometer 10 KΩ R3 Resistor 1K 0603 0603 Tyco electronics Bourns electronics 3214W-1-103E Tyco electronics 01623440-1 PD84002 Table 8. Photo Components part list (continued) Component ID Description Value Case size TL1 Transmission line W=0.92 mm L=13.6 mm TL2 Transmission line W=0.92 mm L=3.5 mm TL3 Transmission line W=0.92 mm L=4.2 mm TL4 Transmission line W=0.92 mm L=3.8 mm TL5 Transmission line W=0.92 mm L=3.7 mm TL6 Transmission line W=0.92 mm L=11.3 mm RF in, RF out SMA-CONN 50 Ω 60 mils PD84002 LDMOS Board 7 Manufacturer Part Code JOHNSON 142-0701-801 STMicroelectronics PD84002 FR-4 THk=0.020" 2OZ Cu Both Sides Photo Figure 13. Photo 9/16 Package mechanical data 8 PD84002 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/16 PD84002 Package mechanical data Table 9. SOT-89 mechanical data Dim. mm. Min Typ Inch Max Min Typ Max A 1.4 1.6 55.1 63.0 B 0.44 0.56 17.3 22.0 B1 0.36 0.48 14.2 18.9 C 0.35 0.44 13.8 17.3 C1 0.35 0.44 13.8 17.3 D 4.4 4.6 173.2 181.1 D1 1.62 1.83 63.8 72.0 E 2.29 2.6 90.2 102.4 e 1.42 1.57 55.9 61.8 e1 2.92 3.07 115.0 120.9 H 3.94 4.25 155.1 167.3 L 0.89 1.2 35.0 47.2 Figure 14. Package dimensions 11/16 Package mechanical data 8.1 PD84002 Thermal pad and via design Thernal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device. The via pattern is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025 plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 15. Pad layout details 12/16 PD84002 8.2 Package mechanical data Soldering profile Figure 16 shows the recommeded solder for devices that have Pb-free terminal plating and where a Pb-free solder is used. Figure 16. Recommended solder profile Figure 17 shows the recommeded solder for devices with Pb-free terminal plating used with leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 17. Recommended solder profile for leaded devices 13/16 Package mechanical data Figure 18. Reel information 14/16 PD84002 PD84002 9 Revision history Revision history Table 10. Document revision history Date Revision 05-Dec-2007 1 Changes Initial release. 15/16 PD84002 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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