19-2127; Rev 0; 8/01 ±15kV ESD-Protected USB Level Translator in UCSP Applications Cell Phones Features ♦ ±15kV ESD Protection on D+ and D♦ Allows Single-Ended or Differential Logic I/O ♦ Internal Linear Regulator Allows Direct Powering from the USB ♦ Internal 1.5kΩ Termination Resistor for Low/FullSpeed ♦ Supports Low-Speed and Full-Speed USB Communications ♦ Complies with USB Standard 1.1 ♦ Three-State Outputs ♦ Re-Enumerate with Power Applied ♦ Up to 15mA Available from the +3.3V Linear Regulator to Power External Circuitry ♦ No Power-Supply Sequencing Required ♦ Dual Function Logic Minimizes System Connections ♦ Operates with VL of 1.8V to 3.6V, Ensuring Compatibility with Low-Voltage ASICs ♦ Available in Miniature Chip-Scale Package Ordering Information PC Peripherals PART Data Cradles TEMP. RANGE PIN-PACKAGE PDAs MAX3340EEUD -40°C to +85°C 14 TSSOP MP3 Players MAX3340EEBE* -40°C to +85°C 16 UCSP** *Future product—contact factory for availability. **UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and environment. Refer to the UCSP Reliability Notice in the UCSP Reliability section of this data sheet for more information. Pin Configurations BOTTOM VIEW TOP VIEW RCV 1 14 VL VP 2 13 VTRM MODE 3 12 D+ VM 4 1 MAX3340E OE/ENUMERATE 5 10 GND B VCC SUSP 7 8 SPEED VP RCV VM MODE D+ OE/ SUSP ENUMERATE D- VL VTRM A RENB TSSOP 4 MAX3340E C 9 3 D 11 D- RENB 6 2 SPEED VCC GND UCSP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3340E General Description The MAX3340E bidirectional level translator converts logic-level signals to USB signals, and USB signals to logic-level signals. It includes the 1.5kΩ USB termination resistor internally, and supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB operation. It has built-in ±15kV ESD protection circuitry to guard the USB I/O pins, D+ and D-. The MAX3340E operates with VL at voltages as low as 1.8V, ensuring compatibility with low-voltage ASICs. The MAX3340E features a logic selectable suspend mode that lowers current draw to less than 200µA. The MAX3340E has a unique re-enumerate feature that allows changes in USB communication protocol while the power is on. The MAX3340E is fully compliant with USB specification 1.1, and the full-speed and lowspeed operation under USB specification 2.0. The MAX3340E is available in the miniature 4 x 4 chipscale package, as well as the small 14-pin TSSOP, and is rated for the -40°C to +85°C extended temperature range. ±15kV ESD-Protected USB Level Translator in UCSP MAX3340E ABSOLUTE MAXIMUM RATINGS (All voltages refer to GND unless otherwise noted) VCC ...........................................................................-0.3V to +6V VL ...........................................................................-0.3V to +5.5V D+, D-......................................................-0.3V to (VTRM + 0.3V) VP, VM, SUSP, OE/ENUMERATE, MODE, SPEED, RENB, RCV ................................................-0.3V to (VL + 0.3V) VTRM ..........................................................-0.3V to (VCC + 0.3V) Maximum Continuous Output Current ..............................±50mA Short-Circuit Duration (D+, D- to VCC or GND)..........Continuous Continuous Power Dissipation (TA = +70°C) 14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW 16-Pin UCSP (derate 7.4mW/°C above +70°C) ...........589mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Solder Profile (MAX3340EEBE) .......................................(Note 1) Lead Temperature (soldering 10s) ..................................+300°C Note 1: For UCSP solder profile information visit www.maxim-ic.com/1st_pages/UCSP.htm Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS USB Supply Voltage VCC USB Supply Current ICC Transmitter-enabled, OE/ENUMERATE low, output static USB Supply Current (Suspend Mode) ICC SUSP high, OE/ENUMERATE floating, D+, D- static MIN TYP MAX UNITS 5.5 V 3 5 mA 90 200 µA 3.3 3.6 V 4 LINEAR REGULATOR VTRM Voltage IVTRM = 0 or 15mA, COUT = 1µF PSRR 10kHz, IVTRM = 15mA, COUT = 1µF External Capacitor Continuous Output Current IVTRM 3.0 55 dB 1 µF 15 mA ESD PROTECTION (D+, D-) Human Body Model ±15 kV IEC1000-4-2 Air-Gap Discharge ±9 kV IEC1000-4-2 Contact Discharge ±5 kV LOGIC-SIDE I/O VL Input Range VL VL Supply Current IL Input High Voltage (Note 3) VIH Input Low Voltage (Note 3) VIL 1.8 RCV, VP, VM open, output static 3.6 40 (2/3) x VL V 0.4 Output High Voltage (Note 3) VOH ISOURCE = +1mA Output Low Voltage (Note 3) VOL ISINK = -1mA OE/ENUMERATE Input High Voltage VEH OE/ENUMERATE Input Low Voltage VEL (2/3) x VL V V 0.4 VL - 0.4 V V 0.4 OE/ENUMERATE Input Impedance V µA 400 V kΩ USB-SIDE I/O Output Voltage Low 2 VOLD D+, D-; 1.5kΩ from D+ or D- to 3.6V, ISINK = 1mA _______________________________________________________________________________________ 0.3 V ±15kV ESD-Protected USB Level Translator in UCSP (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Voltage High VOHD D+, D-; 15kΩ from D+ and D- to GND, ISOURCE = 1mA 2.8 V Input Impedance ZINP D+, D-, OE/ENUMERATE floating 300 kΩ Single-Ended Input Voltage High VIHD D+, D- for VP/VM 2.0 Single-Ended Input Voltage Low VILD D+, D- for VP/VM V 0.8 D+, D- Receiver Hysteresis 200 Driver Output Impedance (Note 4) ROUT Internal Resistor D+, D- steady state drive IVTRM = 15mA RPULLUP 6 1.425 Termination Voltage IVTRM = 0 High-Z State Input Leakage D+, D-; SUSP high Input Common-Mode Voltage Range 1.5 V mV 18 Ω 1.575 kΩ 3 3.6 V -10 10 µA 0.8 2.5 V TIMING CHARACTERISTICS (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 17 ns SPEED INDEPENDENT TIMING CHARACTERISTICS RENB to Receive Three-State Delay Disable-Time tPVZ (Figure 1a) RENB to Receiver Delay EnableTime tPZV (Figure 1a) D+/D- RCV Propagation Delay tPLH CLOAD = 25pF 25 ns D+/D- RCV Propagation Delay tPHL CLOAD = 25pF 25 ns D+/D- to VP Propagation Delay tPLH CLOAD = 25pF 12 ns D+/D- to VP Propagation Delay tPHL CLOAD = 25pF 12 ns RCV Rise-Time tR CLOAD = 25pF 10 ns RCV Fall-Time tF CLOAD = 25pF 10 ns 15 ns FULL-SPEED TIMING CHARACTERISTICS OE/ENUMERATE to Transmit Delay Enable-Time tPZD (Figure 1b) OE/ENUMERATE to Driver ThreeState Delay Disable-Time tPDZ (Figure 1b) 17 ns VP/VM to D+/D- Propagation Delay (MODE 1) tPLH (Figure 3) 25 ns 15 ns _______________________________________________________________________________________ 3 MAX3340E ELECTRICAL CHARACTERISTICS (continued) MAX3340E ±15kV ESD-Protected USB Level Translator in UCSP TIMING CHARACTERISTICS (continued) (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER VM/VP to D+/D- Propagation Delay (MODE 1) SYMBOL tPHL CONDITIONS MIN TYP MAX UNITS (Figure 3) 25 ns VP and VM Rise-Time tR Single-ended receiver, CLOAD = 25pF 10 ns VP and VM Fall-Time tF Single-ended receiver, CLOAD = 25pF 10 ns D+, D- Rise-Time MODE = 1 (Note 5) tR CLOAD = 50pF 4 20 ns D+, D- Fall-Time (Note 5) MODE = 1 tF CLOAD = 50pF 4 20 ns Rise- and Fall-Time Matching MODE = 1 (Note 5) tR/tF CLOAD = 50pF 90 110 % Output Signal Crossover Voltage MODE = 1 (Note 5) VCRS CLOAD = 50pF 1.3 2 V Time to Ignore SE0 14 VP to D+/D- Propagation Delay MODE = 0 (Note 5) tP CLOAD = 50pF (Figure 2) D+/D- Rise-Time MODE = 0 (Note 5) tR CLOAD = 50pF D+, D- Fall-Time MODE = 0 (Note 5) tF Rise- and Fall-Time Matching MODE = 0 (Note 5) Output Signal Crossover MODE = 0 (Note 5) ns 30 ns 4 20 ns CLOAD = 50pF 4 20 ns tR/tF CLOAD = 50pF 90 110 % VCRS CLOAD = 50pF 1.3 2 V 15 LOW-SPEED TIMING CHARACTERISTICS OE/ENUMERATE to Transmit Delay Enable-Time tPZD (Figure 1b) OE/ENUMERATE to Driver ThreeState Delay Disable-Time tPDZ (Figure 1b) VP/VM to D+/D- Propagation Delay (MODE = 1) tPLH (Figure 3) CLOAD = 50pF to 600pF VM/VP to D+/D- Propagation Delay (MODE = 1) tPHL (Figure 3) CLOAD = 50pF to 600pF 4 ns 17 ns 30 200 ns 30 200 ns _______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translator in UCSP (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Transition Rise-Time MODE = 1 (Note 5) tR CLOAD = 50pF to 600pF 75 300 ns Transition Fall-Time MODE = 1 (Note 5) tF CLOAD = 50pF to 600pF 75 300 ns tR/tF CLOAD = 50pF to 600pF 80 125 % Rise- and Fall-Time Matching MODE = 1 (Note 5) Time to Ignore SE0 210 Output Signal Crossover Voltage MODE = 1 (Note 5) ns VCRS CLOAD = 50pF to 600pF 1.3 2 V VP to D+/D- Propagation Delay MODE = 0 tP (Figure 2) CLOAD = 50pF to 600pF 30 200 ns Transition Rise-Time MODE = 0 (Note 5) tR CLOAD = 50pF to 600pF 75 300 ns Transition Fall-Time MODE = 0 (Note 5) tF CLOAD = 50pF to 600pF 75 300 ns Rise- and Fall-Time Matching MODE = 0 (Note 5) tR/tF CLOAD = 50pF to 600pF 80 125 % Output Signal Crossover Voltage MODE = 0 (Note 5) VCRS CLOAD = 50pF to 600pF 1.3 2 V Note 2: Limits are 100% production tested at TA = +25°C. Limits over the entire operating temperature range are guaranteed by design and characterization but are not production tested. Note 3: Logic side refers to RCV, VP, VM, SUSP, SPEED, MODE, and RENB. Note 4: Excludes external resistors. In order to comply with USB specification 1.1, external 24Ω (±1%) series resistors are recommended at D+ and D-. Note 5: Not guaranteed if VP = VM = high. _______________________________________________________________________________________ 5 MAX3340E TIMING CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +5V, VL =+3.3V TA = +25°C, unless otherwise noted.) SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. VCC 6.0 TA = +25°C 5.5 TA = -40°C TA = +85°C 6.75 5.0 6.50 TA = +25°C 6.25 6.00 5.75 TA = -40°C 1.80 2.25 2.70 3.15 3.60 TA = +85°C 25 23 TA = +25°C 21 19 TA = -40°C 17 15 5.50 4.5 27 MAX3340 toc03 TA = +85°C TIME TO ENTER SUSPEND MODE vs. VCC MAX3340 toc02 MAX3340 toc01 6.5 7.00 PROPAGATION DELAY (ns) 4.00 4.25 4.50 4.75 5.00 5.25 4.00 5.50 4.25 4.50 4.75 5.25 VCC (V) VCC (V) SKEW VS. VCC (MODE 0) (HIGH SPEED) SKEW VS. VCC (MODE 0) (LOW SPEED) OE/ENUMERATE, VP, VM TIMING 2.30 2.20 5.50 MAX3340 toc06 11.0 MAX3340 toc04 2.40 T = +85°C 9.0 A T = -40°C SKEW (ns) 2.10 2.00 T = +25°C 1.90 0 7.0 B T = +25°C 5.0 0 1.80 T = +85°C 1.70 C T = -40°C 3.0 0 1.60 (FIGURE 4A) 1.0 1.50 4.25 4.50 4.75 5.00 5.25 4.00 5.50 4.25 4.50 4.75 5.00 5.25 5.50 200ns/div VCC (V) VCC (V) A: VP, 2V/div B: VM, 2V/div C: OE/ENUMERATE, 5V/div VTRM vs. VCC OE/ENUMERATE, VP, VM TIMING MAX3340 toc07 SUSPEND RESPONSE MAX3340 toc09 3.5 MAX3340 toc08 4.00 IVTRM = 15mA 3.4 A VTRM (V) 0 B A 0 3.3 3.2 0 C B 3.1 0 0 (FIGURE 4A) 3.0 20ns/div A: VP, 2V/div B: VM, 2V/div C: OE/ENUMERATE, 5V/div 6 5.00 VL (V) MAX3340 toc05 PROPAGATION DELAY (ns) 7.0 TIME TO ENTER SUSPEND MODE (ns) SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. VL SKEW (ns) MAX3340E ±15kV ESD-Protected USB Level Translator in UCSP 4.00 4.25 4.50 4.75 VCC (V) 5.00 5.25 5.50 100ns/div A: SUSP, 2V/div B: RCV, 2V/div _______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translator in UCSP RISE- AND FALL-TIME MATCHING (LOW-SPEED) RISE- AND FALL-TIME MATCHING (FULL-SPEED) MAX3340 toc10 MAX3340 toc11 f = 750kHz f = 6MHz D+ D+ D- D- 0 0 100ns 20ns Pin Description PIN NAME FUNCTION TSSOP CSP 1 D2 RCV 2 D1 VP System-Side Data Input/Output. Drive OE/ENUMERATE high to make VP a receiver output. Drive OE/ENUMERATE low to make VP a driver input. VP and VM work together, see Table 1 for details. Receiver Output. Single-ended CMOS output. RCV responds to the differential input on D+ and D-. (See Table 1) 3 C2 MODE Mode Control Input. Selects single-ended (Mode Zero) or differential (Mode One) input for the system side when converting logic level signals to USB level signals. MODE is pulled to VCC with an internal 10µA current. If MODE is forced high or left floating, Mode One is selected. If MODE is forced low, Mode Zero is selected. Refer to Table 1. 4 C1 VM System-Side Data Input/Output. Drive OE/ENUMERATE high to make VM a receiver output. Drive OE/ENUMERATE low to make VM a driver input. VM and VP work together, see Table 1 for details. 5 B1 OE/ ENUMERATE Output Enable. Drive OE/ENUMERATE high to enable VP/VM outputs. Float to disconnect RPULLUP. 6 A1 RENB Receive Enable Input. When RENB is forced high, RCV and VM/VP respond to signals at D+/D-. When RENB is forced low, only RCV responds to signals at D+/D-, VM/VP are high impedance. Normally connected to OE/ENUMERATE. 7 B2 SUSP Suspend Input. Drive SUSP low for normal operation. Force SUSP high for low-power state. In low-power state RCV is low, D+/D- are high impedance if OE/ENUMERATE is floating, and VP/VM are active outputs. _______________________________________________________________________________________ 7 MAX3340E Typical Operating Characteristics (continued) (VCC = +5V, VL = +3.3V TA = +25°C, unless otherwise noted.) ±15kV ESD-Protected USB Level Translator in UCSP MAX3340E Pin Description (continued) PIN TSSOP CSP NAME FUNCTION USB Transmission Speed Select Input. If SPEED is forced high, full-speed (12Mbps) is selected and the internal 1.5kΩ pullup resistor is connected to D+. If SPEED is forced low, low-speed (1.5Mbps) is selected and the internal 1.5kΩ pullup resistor is connected to D-. 8 A2 SPEED 9 A3 VCC USB-Side Power-Supply Input. Connect VCC to the incoming USB power supply. Bypass VCC to GND with 0.1µF ceramic and 10µF electrolytic capacitors. 10 A4 GND Ground — B3, C3 N.C. No Connect. There are no solder bumps at these locations. 11 B4 D- USB Differential Data Input/Output. Connect to the USB’s D- signal through a 24.3Ω ±1% resistor. 12 C4 D+ USB Differential Data Input/Output. Connect to the USB’s D+ signal through a 24.3Ω ±1% resistor. 13 D4 VTRM 14 D3 VL Regulated Output Voltage. 3.3V output derived from the VCC input. Bypass VTRM to GND with a 1µF (or more) low-ESR capacitor such as ceramic or plastic film types. Up to 15mA may be drawn from VTRM for powering external components. System-Side Power-Supply Input. Connect to the system’s logic-level power supply, 1.8V to 3.6V. Detailed Description ESD protection The MAX3340E is a bidirectional level translator that converts single-ended or differential logic level signals to differential USB signals, and converts differential USB signals to single-ended or differential logic level signals. It includes an internal 1.5kΩ pullup resistor that may be connected to either D+ to D- for full-speed or low-speed operation (Functional Diagram). The MAX3340E can be energized without concern about power-supply sequencing. Additionally, the USB I/O pins, D+ and D-, are ESD protected to ±15kV. The MAX3340E can get its USB-side power, VCC, directly from the USB connection, and can operate with systemside power, VL, down to 1.8V and still meet the USB physical layer specifications. MAX3340E supports both full-speed (12Mbps) and low-speed (1.5Mbps), USB specification 1.1 operation. To protect the MAX3340E against ESD, D+ and D- have extra protection against static electricity to protect the device up to ±15kV. The ESD structures withstand high ESD in all states; normal operation, suspend, and powered down. In order for the 15kV ESD structures to work correctly a 1µF or greater capacitor must be connected from VTRM to GND. ESD protection can be tested in various ways; the D+ and D- input/output pins are characterized for protection to the following limits: The MAX3340E has a unique re-enumerate feature which works when power is on. Floating OE/ENUMERATE will disconnect the internal 1.5kΩ termination resistor from both D+ and D-, re-enumerating the USB. This is useful if changes in communication protocol are required while power is applied, and while the USB cable is connected. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. 8 1) ±15kV using the Human Body Model. 2) ±5kV using the Contact Discharge method specified in IEC 1000-4-2. 3) ±9kV using the IEC 1000-4-2 Air-Gap method. _______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translator in UCSP IEC 1000-4-2 The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX3340E helps you design equipment that meets Level 2 of IEC 1000-4-2, without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 1000-4-2 is a higher peak current in IEC 1000-4-2, because series resistance is lower in the IEC 1000-4-2 model. Hence, the ESD withstand voltage measured to IEC 1000-4-2 is generally lower than that measured using the Human Body Model. Figure 6a shows the IEC 1000-4-2 model. RC 1MΩ CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1500Ω DISCHARGE RESISTANCE DEVICE UNDER TEST STORAGE CAPACITOR Figure 5a. Human Body ESD Test Models IP 100% 90% Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES 36.8% 10% 0 The Air-Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized. Machine Model The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. Of course, all pins require this protection during manufacturing, not just RS-232 inputs and outputs. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports. Cs 100pF MAX3340E Human Body Model Figure 5a shows the Human Body Model, and Figure 5b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. 0 tRL TIME tDL CURRENT WAVEFORM Figure 5b. Human Body Model Current Waveform RC 50MΩ to 100MΩ CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 6a. IEC 1000-4-2 ESD Test Model _______________________________________________________________________________________ 9 MAX3340E ±15kV ESD-Protected USB Level Translator in UCSP Applications Information Device Control OE/ENUMERATE OE/ENUMERATE is a dual-function control input. It controls the direction of communication, and can also be used to re-establish a device on the USB. With OE/ENUMERATE low, the MAX3340E transfers data from the system side to the USB side. With OE/ENUMERATE high, the MAX3340E transfers data from the USB side to the system side. If OE/ENUMERATE is floating for more than 200ns (typ), the internal 1.5kΩ resistor is disconnected from both D+ and D-, signaling the USB to re-enumerate the device. This is useful if changes in the USB transmission protocol are required while operating. MODE MODE is a control input that selects whether differential or single-ended logic signals are recognized by the system side of the MAX3340E (Table 1). MODE has an internal pullup to VCC. If MODE is left floating or forced high, differential input is selected. With differential input selected, outputs D+ and D- follow the differential inputs at VP and VM. If VP and VM are both forced low, an SE0 condition is forced on the USB. Drive MODE and VM low for single-ended input mode. With single-ended input selected, the differential signal on D+ and D- is controlled by VP. If VM is high when MODE is low, D- and D+ are both low forcing an SEO condition. RENB Drive RENB (receive enable) high to enable VP and VM as receive outputs. When RENB is forced low VP and VM are high impedance. RCV is unaffected by RENB. Connect RENB to OE/ENUMERATE for normal operation. SUSP SUSP, or suspend, is a control input. When SUSP is forced high the MAX3340E enters low-power state. In this state the quiescent supply current into VCC is less than 200µA if OE/ENUMERATE is floating and D+ and D- are static. In this mode RCV is forced low, and D+ and D- are high-impedance inputs (Table 1d). In suspend mode, VP and VM remain active as receive outputs, VTRM stays on, and the MAX3340E continues to receive data from the USB. 10 SPEED SPEED is a control input that selects between lowspeed (1.5Mbps) and full-speed (12Mbps) USB transmission. Internally, it selects whether the 1.5kΩ pullup resistor is connected to D+ (full-speed) or D- (lowspeed) (Functional Diagram). Force SPEED high to select full-speed, or force SPEED low to select lowspeed. VTRM VTRM is the 3.3V output of the internal linear voltage regulator. The regulator is used to power the internal portions of the USB side of the MAX3340E. VTRM can be used to power external devices with the ability to source up to 15mA. The VTRM regulator’s supply input is VCC. Connect a 1.0µF (or greater) ceramic or plastic capacitor from VTRM to GND, as close to VTRM as possible. D+ and DD+ and D- are the transmitter I/O connections, and are ESD protected to ±15kV using the Human Body Model, making the MAX3340E ideal for applications where a robust transmitter is required. VCC In most applications VCC is derived from the USB +5V output. If supplying VCC with an alternative power supply, the input range is 4.0V to 5.5V. Bypass VCC to GND with a 10µF and a 0.1µF capacitor. Place the 0.1µF capacitor closest to the MAX3340E. External Components External Resistors Two external resistors are required for USB connection, each of them 24.3Ω, ±1%, 1/8W (or greater). Place one resistor in series between D+ of the MAX3340E and D+ of the USB connector. Place the other resistor in series between D- of the MAX3340E and D- of the USB connector. The Typical Operating Circuit shows these connections. External Capacitors Four external capacitors are recommended for proper operation. Use a 0.1µF ceramic for decoupling VL, a 0.1µF ceramic and a 10µF electrolytic for decoupling VCC, and a 1.0µF (or greater) ceramic or plastic filter capacitor on VTRM. Return all capacitors to GND. Powering External Components with VTRM VTRM is the output of the internal 3.3V linear regulator, and requires an external ceramic capacitor, as detailed in the VTRM section above. VTRM can source up to 15mA at 3.3V for powering external devices. Note that the source of power for the internal regulator is usually ______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translator in UCSP Data Transfer Receiving Data from the USB Data received from the USB are output to VP/VM in either of two ways, differentially or single-ended. To receive data from the USB, force MODE high or let it float, force OE/ENUMERATE and RENB high, and force SUSP low. Differential data arriving at D+/D- will appear as differential logic signals at VP/VM, and as a single- ended logic signal at RCV. If both D+ and D- are low, then VP and VM are low, signaling an SE0 condition on the bus; RCV is undefined. See Table 1. Transmitting Data to the USB The MAX3340E outputs data to the USB differentially on D+ and D-. The logic driving signals may be either differential or single-ended. For sending differential logic, force MODE high or let it float, force OE/ENUMERATE, RENB and SUSP low, and apply data to VP and VM. If sending single-ended logic, force MODE low, force RENB, SUSP, OE/ENUMERATE, and VM low, and apply data to VP. With VP low, D+ is low and D- high, resulting in a Logic 0. With VP high, D+ is high and D- low resulting in a Logic 1 state. See Table 1. VL VL RENB VL/2 VP 0 VL/2 0 tP tPZV tPVZ 2V VOH - 0.3V D+/D- VP/VM VOL + 0.3V 0.8V Figure 2. Mode 0 Timing Figure 1a. Enable and Disable Timing, Receiver VL VL OE VL/2 VP/VM 0 VL/2 0 tPZD tPDZ tPLH VOHD - 0.3V D+/D- tPHL 2V D+/D- VOLD + 0.3V Figure 1b. Enable and Disable Timing, Transmitter 0.8V Figure 3. Mode 1 Timing ______________________________________________________________________________________ 11 MAX3340E the USB provided 5V; if so, any devices powered from VTRM will lose power if the USB connection is broken. If D+ or D- is shorted to +5V (a fault condition), VTRM follows a diode drop below. If any external circuitry is powered from VTRM, it is recommended that the circuitry be either +5V tolerant, or that an external protection zener is used. MAX3340E ±15kV ESD-Protected USB Level Translator in UCSP TEST POINT MAX3340E MAX3340E TEST POINT 200Ω VM or VP or RCV VP or VM + 5pF - GND or VCC (b) LOAD FOR VP, VM AND RCV (a) LOAD FOR ENABLE AND DISABLE TIME, VP/VM MAX3340E 3.3V D+ or D- TEST POINT 24Ω MAX3340E 24Ω TEST POINT 200Ω D+ or D- 1.5kΩ CL (c) LOAD FOR D+/D- 25pF 15kΩ 50pF + - (d) LOAD FOR ENABLE AND DISABLE TIME, D+/D- Figure 4. Test Circuits 12 ______________________________________________________________________________________ GND or VCC ±15kV ESD-Protected USB Level Translator in UCSP MAX3340E Table 1a. Truth Table Transmit (MODE = 0) OE/ENUMERATE = 0 (TRANSMIT), RENB = 0 INPUT VP OUTPUT VM D+ D- RESULT RCV 0 0 0 1 0 0 1 0 0 X Logic 0 SEO 1 0 1 0 1 Logic 1 1 1 0 0 X SEO Table 1b. Truth Table Transmit (MODE = 1) OE/ENUMERATE = 0 (TRANSMIT), RENB = 0 INPUT OUTPUT RESULT VP VM D+ D- RCV 0 0 0 0 X SEO 0 1 0 1 0 Logic 0 1 0 1 0 1 Logic 1 1 1 1 1 X Undefined Table 1c. Truth Table Receive OE/ENUMERATE = 0 (RECEIVE), RENB = 1 INPUT OUTPUT RESULT D+ D- VP VM RCV 0 0 0 0 X SEO 0 1 0 1 0 Logic 0 1 0 1 0 1 Logic 1 1 1 1 1 X Undefined Table 1d. Function Select SUSP OE/ENUMERATE RENB D+/D- RCV VP/VM FUNCTION 0 0 0 Driving Active High-Z Normal driving (differential receiver active) 0 0 1 Driving Active Active Conflict state: not permitted 0 1 0 High-Z Active High-Z RPULLUP connected 0 1 1 High-Z Active Active Receiving 1 0 or 1 0 or 1 High-Z 0 Active Low-power state 0 Float 0 or 1 High-Z Active High-Z RPULLUP disconnected 1 Float 0 or 1 High-Z 0 Active RPULLUP disconnected ______________________________________________________________________________________ 13 ±15kV ESD-Protected USB Level Translator in UCSP MAX3340E Typical Operating Circuit SYSTEM POWER 0.1µF CERAMIC 0.1µF CERAMIC ASIC 10µF ELECTROLYTIC USB CABLE PC VCC USB POWER 24.3Ω 1% VL D+ VP D+ 24.3Ω 1% VM D- RCV D- MAX3340E RENB OE/ENUMERATE GND SUSP GND 15kΩ 15kΩ SPEED MODE VTRM 1.0µF CERAMIC UCSP Reliability The UCSP represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. CSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a CSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. 14 Mechanical stress performance is a greater consideration for a CSP package. CSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Table 2 shows the testing done to characterize the CSP reliability performance. In conclusion, the UCSP is capable of performing reliably through environmental stresses as indicated by the results in the table. Additional usage data and recommendations are detailed in the UCSP application note, which can be found on Maxim’s website at www.maxim-ic.com. ______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translator in UCSP MAX3340E Table 2. Reliability Test Data TEST Temperature Cycle Operating Life Moisture Resistance Low-Temperature Storage Low-Temperature Operational Solderability ESD High-Temperature Operating Life CONDITIONS DURATION NO. OF FAILURES PER SAMPLE SIZE -35°C to +85°C, -40°C to +100°C 150 cycles, 900 cycles 0/10, 0/200 TA = +70°C 240hr 0/10 +20°C to +60°C, 90% RH 240hr 0/10 -20°C 240hr 0/10 -10°C 24hr 0/10 8hr steam age — 0/15 ±2000V, Human Body Model — 0/5 TJ = +150°C 168hr 0/45 Functional Diagram VCC LINEAR REGULATOR MAX3340E VTRM VL 1.5kΩ SPEED INTERNAL POWER OE/ENUMERATE D+ RENB MODE DSUSP LEVEL SHIFTER AND CONTROL LOGIC RCV VP VM GND ______________________________________________________________________________________ 15 ±15kV ESD-Protected USB Level Translator in UCSP TSSOP,NO PADS.EPS MAX3340E Package Information 16 ______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translator in UCSP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3340E Package Information (continued)