19-2127; Rev 1; 6/02 ±15kV ESD-Protected USB Level Translators in UCSP The MAX3340E/MAX3343E bidirectional level translators convert logic-level signals to USB signals, and USB signals to logic-level signals. They include the 1.5kΩ USB termination resistor internally, and support both full-speed (12Mbps) and low-speed (1.5Mbps) USB operation. They have built-in ±15kV ESD protection circuitry to guard the USB I/O pins, D+ and D-. The MAX3340E/MAX3343E operate with VL at voltages as low as 1.8V, ensuring compatibility with low-voltage ASICs. The MAX3340E/MAX3343E feature a logicselectable suspend mode that lowers current draw to less than 200µA. The MAX3340E/MAX3343E have a unique re-enumerate feature that allows changes in USB communication protocol while the power is on. The MAX3340E/MAX3343E are fully compliant with USB specification 1.1, and the full-speed and low-speed operation under USB specification 2.0. The MAX3340E/MAX3343E are available in the miniature 4 x 4 chip-scale package, as well as the small 14pin TSSOP, and are rated for the -40°C to +85°C extended temperature range. Features ♦ ±15kV ESD Protection on D+ and D♦ Internal Linear Regulator Allows Direct Powering from the USB ♦ Internal 1.5kΩ Termination Resistor for Low/FullSpeed ♦ Support Low-Speed and Full-Speed USB Communications ♦ Comply with USB Standard 1.1 ♦ Three-State Outputs ♦ Re-Enumerate with Power Applied ♦ Up to 15mA Available from the +3.3V Linear Regulator to Power External Circuitry ♦ No Power-Supply Sequencing Required ♦ Operate with VL of 1.8V to 3.6V, Ensuring Compatibility with Low-Voltage ASICs ♦ Available in Miniature Chip-Scale Package Ordering Information Applications PART Cell Phones PC Peripherals TEMP RANGE PIN-PACKAGE MAX3340EEUD -40°C to +85°C 14 TSSOP MAX3340EEBE-T* -40°C to +85°C 16 UCSP** Data Cradles MAX3343EEUD -40°C to +85°C 14 TSSOP PDAs MAX3343EEBE-T* -40°C to +85°C 16 UCSP** MP3 Players *Future product—contact factory for availability. **UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and environment. Refer to the UCSP Reliability Notice in the UCSP Reliability section of this data sheet for more information. Pin Configurations BOTTOM VIEW TOP VIEW RCV 1 14 VL VP 2 13 VTRM MODE 3 12 D+ VM 4 OE/ENUMERATE (OE) 5 MAX3340E MAX3343E 3 4 MAX3340E/MAX3343E D 11 D10 GND 9 VCC SUSP 7 8 SPEED TSSOP 2 VP RCV VL VTRM VM MODE D+ OE/ SUSP ENUMERATE (OE) D- C RENB (ENUMERATE) 6 () ARE FOR MAX3343E ONLY. 1 B A RENB SPEED (ENUMERATE) VCC GND UCSP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3340E/MAX3343E General Description ±15kV ESD-Protected USB Level Translators in UCSP MAX3340E/MAX3343E ABSOLUTE MAXIMUM RATINGS (All voltages refer to GND, unless otherwise noted.) VCC ...........................................................................-0.3V to +6V VL ...........................................................................-0.3V to +5.5V D+, D-......................................................-0.3V to (VTRM + 0.3V) VP, VM, SUSP, OE/ENUMERATE, MODE, SPEED, RENB, RCV, OE, ENUMERATE ..................-0.3V to (VL + 0.3V) VTRM ..........................................................-0.3V to (VCC + 0.3V) Maximum Continuous Output Current ..............................±50mA Short-Circuit Duration (D+, D- to VCC or GND)..........Continuous Continuous Power Dissipation (TA = +70°C) 14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW 16-Pin UCSP (derate 7.4mW/°C above +70°C) ...........589mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Solder Profile (MAX334_EEBE) .......................................(Note 1) Lead Temperature (soldering 10s) ..................................+300°C Note 1: For UCSP solder profile information visit www.maxim-ic.com/1st_pages/UCSP.htm Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS USB Supply Voltage VCC USB Supply Current ICC Transmitter-enabled, OE/ENUMERATE low, output static USB Supply Current (Suspend Mode) ICC SUSP high, OE/ENUMERATE floating, D+, D- static MIN TYP MAX UNITS 5.5 V 3 5 mA 90 200 µA 3.3 3.6 V 4 LINEAR REGULATOR VTRM Voltage IVTRM = 0 or 15mA, COUT = 1µF PSRR 10kHz, IVTRM = 15mA, COUT = 1µF External Capacitor Continuous Output Current IVTRM 3.0 55 dB 1 µF 15 mA ESD PROTECTION (D+, D-) Human Body Model ±15 kV IEC1000-4-2 Air-Gap Discharge ±9 kV IEC1000-4-2 Contact Discharge ±5 kV LOGIC-SIDE I/O VL Input Range VL VL Supply Current IL Input High Voltage (Note 2) Input Low Voltage (Note 2) 1.8 RCV, VP, VM open, output static VIH V VIL 0.4 VOH ISOURCE = +1mA Output Low Voltage (Note 2) VOL ISINK = -1mA OE/ENUMERATE Input High Voltage VEH MAX3340E OE/ENUMERATE Input Low Voltage VEL MAX3340E OE/ENUMERATE Input Impedance (2/3) x VL OE Input High Voltage VEH MAX3343E OE Input Low Voltage VEL MAX3343E ENUMERATE Input High Voltage VEH MAX3343E V V 0.4 VL - 0.4 V V 0.4 MAX3340E V µA (2/3) x VL Output High Voltage (Note 2) 2 3.6 40 400 VL - 0.4 V 0.4 VL - 0.4 _______________________________________________________________________________________ V kΩ V V ±15kV ESD-Protected USB Level Translators in UCSP (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER SYMBOL ENUMERATE Input Low Voltage VEL MAX UNITS MAX3343E CONDITIONS MIN TYP 0.4 V 0.3 V USB-SIDE I/O Output Voltage Low VOLD D+, D-; 1.5kΩ from D+ or D- to 3.6V, ISINK = 1mA Output Voltage High VOHD D+, D-; 15kΩ from D+ and D- to GND, ISOURCE = 1mA 2.8 V Input Impedance, MAX3340E ZINP D+, D-, OE/ENUMERATE floating 300 kΩ Single-Ended Input Voltage High VIHD D+, D- for VP/VM 2.0 V Single-Ended Input Voltage Low VILD D+, D- for VP/VM 0.8 D+, D- Receiver Hysteresis 200 Driver Output Impedance (Note 3) ROUT Internal Resistor D+, D- steady state drive IVTRM = 15mA RPULLUP 1.425 Termination Voltage IVTRM = 0 High-Z State Input Leakage D+, D-; SUSP high Input Common-Mode Voltage Range Differential Input Sensitivity 6 Peak voltage 1.5 V mV 18 Ω 1.575 kΩ 3 3.6 V -10 10 µA 0.8 2.5 V 200 mV TIMING CHARACTERISTICS (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 17 ns SPEED INDEPENDENT TIMING CHARACTERISTICS RENB to Receive Three-State Delay Disable Time tPVZ (Figure 1a) MAX3340E RENB to Receiver Delay Enable Time tPZV (Figure 1a) MAX3340E OE to Receive Three-State Delay Disable Time tPVZ (Figure 1a) MAX3343E OE to Receiver Delay Enable Time tPZV (Figure 1a) MAX3343E D+/D- RCV Propagation Delay tPLH CLOAD = 25pF 25 ns D+/D- RCV Propagation Delay tPHL CLOAD = 25pF 25 ns D+/D- to VP Propagation Delay tPLH CLOAD = 25pF 12 ns D+/D- to VP Propagation Delay 15 ns 17 15 ns ns tPHL CLOAD = 25pF 12 ns RCV Rise-Time tR CLOAD = 25pF 10 ns RCV Fall-Time tF CLOAD = 25pF 10 ns _______________________________________________________________________________________ 3 MAX3340E/MAX3343E ELECTRICAL CHARACTERISTICS (continued) MAX3340E/MAX3343E ±15kV ESD-Protected USB Level Translators in UCSP TIMING CHARACTERISTICS (continued) (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FULL-SPEED TIMING CHARACTERISTICS OE/ENUMERATE to Transmit Delay Enable Time tPZD (Figure 1b) MAX3340E OE/ENUMERATE to Driver Three State Delay Disable Time tPDZ (Figure 1b) MAX3340E 17 ns OE to Transmit Delay Enable Time tPZD (Figure 1b) MAX3343E 70 ns OE to Driver Three-State Delay Disable Time tPDZ (Figure 1b) MAX3343E 17 ns VP/VM to D+/D- Propagation Delay (MODE 1) tPLH (Figure 3) 25 ns VM/VP to D+/D- Propagation Delay (MODE 1) tPHL (Figure 3) 25 ns 15 ns VP and VM Rise-Time tR Single-ended receiver, CLOAD = 25pF 10 ns VP and VM Fall-Time tF Single-ended receiver, CLOAD = 25pF 10 ns D+, D- Rise-Time MODE = 1 (Note 4) tR CLOAD = 50pF 4 20 ns D+, D- Fall-Time (Note 4) MODE = 1 tF CLOAD = 50pF 4 20 ns Rise- and Fall-Time Matching MODE = 1 (Note 4) tR/tF CLOAD = 50pF 90 110 % Output Signal Crossover Voltage MODE = 1 (Note 4) VCRS CLOAD = 50pF 1.3 2 V Time to Ignore SE0 14 VP to D+/D- Propagation Delay MODE = 0 (Note 4) tP CLOAD = 50pF (Figure 2) D+/D- Rise-Time MODE = 0 (Note 4) tR CLOAD = 50pF D+, D- Fall-Time MODE = 0 (Note 4) tF Rise- and Fall-Time Matching MODE = 0 (Note 4) Output Signal Crossover MODE = 0 (Note 4) ns 30 ns 4 20 ns CLOAD = 50pF 4 20 ns tR/tF CLOAD = 50pF 90 110 % VCRS CLOAD = 50pF 1.3 2 V 15 LOW-SPEED TIMING CHARACTERISTICS OE/ENUMERATE to Transmit Delay Enable Time tPZD (Figure 1b) MAX3340E OE/ENUMERATE to Driver ThreeState Delay Disable Time tPDZ (Figure 1b) MAX3340E 4 _______________________________________________________________________________________ ns 17 ns ±15kV ESD-Protected USB Level Translators in UCSP (VCC = +4V to +5.5V, GND = 0, VL = +1.8V to +3.6V, D+ to GND = 15kΩ, D- to GND = 15kΩ, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V, VL = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS OE to Transmit Delay Enable Time tPZD (Figure 1b) MAX3343E OE to Driver Three-State Delay Disable Time tPDZ (Figure 1b) MAX3343E VP/VM to D+/D- Propagation Delay (MODE = 1) tPLH (Figure 3) CLOAD = 50pF to 600pF VM/VP to D+/D- Propagation Delay (MODE = 1) tPHL Transition Rise-Time MODE = 1 (Note 4) Transition Fall-Time MODE = 1 (Note 4) Rise- and Fall-Time Matching MODE = 1 (Note 4) MIN TYP MAX 15 ns 17 ns 30 200 ns (Figure 3) CLOAD = 50pF to 600pF 30 200 ns tR CLOAD = 50pF to 600pF 75 300 ns tF CLOAD = 50pF to 600pF 75 300 ns tR/tF CLOAD = 50pF to 600pF 80 125 % Time to Ignore SE0 210 Output Signal Crossover Voltage MODE = 1 (Note 4) UNITS ns VCRS CLOAD = 50pF to 600pF 1.3 2 V VP to D+/D- Propagation Delay MODE = 0 tP (Figure 2) CLOAD = 50pF to 600pF 30 200 ns Transition Rise-Time MODE = 0 (Note 4) tR CLOAD = 50pF to 600pF 75 300 ns Transition Fall-Time MODE = 0 (Note 4) tF CLOAD = 50pF to 600pF 75 300 ns Rise- and Fall-Time Matching MODE = 0 (Note 4) tR/tF CLOAD = 50pF to 600pF 80 125 % Output Signal Crossover Voltage MODE = 0 (Note 4) VCRS CLOAD = 50pF to 600pF 1.3 2 V Note 2: Logic side refers to RCV, VP, VM, SUSP, SPEED, MODE, RENB, OE/ENUMERATE, OE, and ENUMERATE. Note 3: Excludes external resistors. In order to comply with USB specification 1.1, external 24Ω (±1%) series resistors are recommended at D+ and D-. Note 4: Not guaranteed if VP = VM = high. _______________________________________________________________________________________ 5 MAX3340E/MAX3343E TIMING CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +5V, VL =+3.3V TA = +25°C, unless otherwise noted.) SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. VCC 6.0 TA = +25°C 5.5 TA = -40°C TA = +85°C 6.75 5.0 6.50 TA = +25°C 6.25 6.00 5.75 TA = -40°C 1.80 2.25 2.70 3.15 3.60 TA = +85°C 25 23 TA = +25°C 21 19 TA = -40°C 17 15 5.50 4.5 27 MAX3340 toc03 TA = +85°C TIME TO ENTER SUSPEND MODE vs. VCC MAX3340 toc02 MAX3340 toc01 6.5 7.00 PROPAGATION DELAY (ns) 4.00 4.25 4.50 4.75 5.00 5.25 4.00 5.50 4.25 4.50 4.75 5.25 VCC (V) VCC (V) SKEW VS. VCC (MODE 0) (HIGH SPEED) SKEW VS. VCC (MODE 0) (LOW SPEED) MAX3340E OE/ENUMERATE, VP, VM TIMING 2.30 2.20 5.50 MAX3340 toc06 11.0 MAX3340 toc04 2.40 T = +85°C 9.0 A T = -40°C SKEW (ns) 2.10 2.00 T = +25°C 1.90 0 7.0 B T = +25°C 5.0 0 1.80 T = +85°C 1.70 C T = -40°C 3.0 0 1.60 (FIGURE 4A) 1.0 1.50 4.25 4.50 4.75 5.00 5.25 4.00 5.50 4.25 4.50 4.75 5.00 5.25 200ns/div 5.50 VCC (V) VCC (V) MAX3340E OE/ENUMERATE, VP, VM TIMING A: VP, 2V/div B: VM, 2V/div C: OE/ENUMERATE, 5V/div VTRM vs. VCC MAX3340 toc07 SUSPEND RESPONSE MAX3340 toc09 3.5 MAX3340 toc08 4.00 IVTRM = 15mA 3.4 A VTRM (V) 0 B A 0 3.3 3.2 0 C B 3.1 0 0 (FIGURE 4A) 3.0 20ns/div A: VP, 2V/div B: VM, 2V/div C: OE/ENUMERATE, 5V/div 6 5.00 VL (V) MAX3340 toc05 PROPAGATION DELAY (ns) 7.0 TIME TO ENTER SUSPEND MODE (ns) SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. VL SKEW (ns) MAX3340E/MAX3343E ±15kV ESD-Protected USB Level Translators in UCSP 4.00 4.25 4.50 4.75 VCC (V) 5.00 5.25 5.50 100ns/div A: SUSP, 2V/div B: RCV, 2V/div _______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translators in UCSP RISE- AND FALL-TIME MATCHING (LOW-SPEED) RISE- AND FALL-TIME MATCHING (FULL-SPEED) MAX3340 toc10 MAX3340 toc11 f = 750kHz f = 6MHz D+ D+ D- D- 0 0 100ns 20ns Pin Description PIN NAME FUNCTION TSSOP CSP 1 D2 RCV Receiver Output. Single-ended CMOS output. RCV responds to the differential input on D+ and D-. (See Tables 1, 2) 2 D1 VP System-Side Data Input/Output. Drive OE/ENUMERATE (OE) high to make VP a receiver output. Drive OE/ENUMERATE (OE) low to make VP a driver input. VP and VM work together. See Table 1 (Table 2). Mode Control Input. Selects single-ended (Mode Zero) or differential (Mode One) input for the system side when converting logic-level signals to USB-level signals. MODE is pulled to VCC with an internal 10µA current (MAX3340E only). If MODE is forced high or left floating (MAX3340E), Mode One is selected. If MODE is forced low, Mode Zero is selected. See Table 1 (Table 2). 3 C2 MODE 4 C1 VM System-Side Data Input/Output. Drive OE/ENUMERATE (OE) high to make VM a receiver output. Drive OE/ENUMERATE (OE) low to make VM a driver input. VM and VP work together. See Table 1 (Table 2). OE ENUMERATE Output Enable. Drive OE/ENUMERATE high to enable VP/VM outputs. Float to disconnect RPULLUP. 5 B1 (OE) Output Enable. Drive OE high to enable the receiver. Drive OE low to enable the driver input. _______________________________________________________________________________________ 7 MAX3340E/MAX3343E Typical Operating Characteristics (continued) (VCC = +5V, VL = +3.3V TA = +25°C, unless otherwise noted.) ±15kV ESD-Protected USB Level Translators in UCSP MAX3340E/MAX3343E Pin Description (continued) PIN TSSOP CSP NAME RENB 6 FUNCTION Receive Enable Input. When RENB is forced high, RCV and VM/VP respond to signals at D+/D-. When RENB is forced low, only RCV responds to signals at D+/D-, VM/VP are high impedance. Normally connected to OE/ENUMERATE. A1 Enumerate Input. Drive ENUMERATE low to disconnect the internal 1.5kΩ resistor, and (ENUMERATE) enumerate the USB. With ENUMERATE high, the internal 1.5kΩ resistor is connected to either D+ or D-, depending on the state of SPEED. Suspend Input. Drive SUSP low for normal operation. Force SUSP high for low-power state. In low-power state RCV is low, D+/D- are high impedance if OE/ENUMERATE (OE) is floating, and VP/VM are active outputs. 7 B2 SUSP 8 A2 SPEED 9 A3 VCC USB-Side Power-Supply Input. Connect VCC to the incoming USB power supply. Bypass VCC to GND with 0.1µF ceramic and 10µF electrolytic capacitors. 10 A4 GND Ground 11 B4 D- USB Differential Data Input/Output. Connect to the USB’s D- signal through a 24.3Ω ±1% resistor. 12 C4 D+ USB Differential Data Input/Output. Connect to the USB’s D+ signal through a 24.3Ω ±1% resistor. 13 D4 VTRM Regulated Output Voltage. 3.3V output derived from the VCC input. Bypass VTRM to GND with a 1µF (or more) low-ESR capacitor such as ceramic or plastic film types. Up to 15mA can be drawn from VTRM for powering external components. 14 D3 VL System-Side Power-Supply Input. Connect to the system’s logic-level power supply, 1.8V to 3.6V. Bypass to GND with a 1.0µF capacitor. USB Transmission Speed Select Input. If SPEED is forced high, full-speed (12Mbps) is selected and the internal 1.5kΩ pullup resistor is connected to D+. If SPEED is forced low, low-speed (1.5Mbps) is selected and the internal 1.5kΩ pullup resistor is connected to D- () are for the MAX3343E only. Detailed Description The MAX3340E/MAX3343E are bidirectional level translators that convert single-ended or differential logiclevel signals to differential USB signals, and convert differential USB signals to single-ended or differential logic-level signals. They include an internal 1.5kΩ pullup resistor that may be connected to either D+ or D- for full-speed or low-speed operation (Functional Diagram). The MAX3340E/MAX3343E can be energized without concern about power-supply sequencing. Additionally, the USB I/O pins, D+ and D-, are ESD protected to ±15kV. The MAX3340E/MAX3343E can get their USB-side power, VCC, directly from the USB con- 8 nection, and can operate with system-side power, VL, down to 1.8V and still meet the USB physical layer specifications. The MAX3340E/MAX3343E support both full-speed (12Mbps) and low-speed (1.5Mbps), USB specification 1.1 operation. The MAX3340E/MAX3343E have a unique re-enumerate feature that works when power is on. Floating OE/ENUMERATE (MAX3340E), or driving ENUMERATE low (MAX3343E), disconnects the internal 1.5kΩ termination resistor from both D+ and D-, re-enumerating the USB. This is useful if changes in communication protocol are required while power is applied, and while the USB cable is connected. _______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translators in UCSP VL VL VL/2 RENB, OE VP 0 VL/2 0 tP tPZV tPVZ 2V VOH - 0.3V D+/D- VP/VM VOL + 0.3V 0.8V Figure 2. Mode 0 Timing Figure 1a. Enable and Disable Timing, Receiver VL VL VL/2 OE VP/VM 0 VL/2 0 tPDZ tPZD tPLH VOHD - 0.3V D+/D- tPHL 2V D+/D- VOLD + 0.3V Figure 1b. Enable and Disable Timing, Transmitter Differences between the MAX3343E and the MAX3340E The MAX3443E OE to D+/D- enable time is under 35ns (typ), while the MAX3340E enters SE0 mode for ~150ns at the assertion of OE. The MAX3343E separates the OE function from the enumerate control, unlike the MAX3340E. Also, the MAX3343E eliminates the receiveenable input (RENB) found on the MAX3340E, as the MAX3343E receivers are enabled by forcing OE high. Additionally, the MAX3343E features lower suspend mode current. Applications Information Device Control OE/ENUMERATE (MAX3340E) OE/ENUMERATE is a dual-function control input. It controls the direction of communication, and can also be 0.8V Figure 3. Mode 1 Timing used to re-establish a device on the USB. With OE/ENUMERATE low, the MAX3340E transfers data from the system side to the USB side. With OE/ENUMERATE high, the MAX3340E transfers data from the USB side to the system side. If OE/ENUMERATE is floating for more than 200ns (typ), the internal 1.5kΩ resistor is disconnected from both D+ and D-, signaling the USB to re-enumerate the device. This is useful if changes in the USB transmission protocol are required while operating. OE (MAX3343E) OE controls the direction of communication through the device. With OE low, the MAX3343E transfers data from the system side to the USB side. With OE high, the MAX3343E transfers data from the USB side to the system side. _______________________________________________________________________________________________________ 9 MAX3340E/MAX3343E Timing Diagrams MAX3340E/MAX3343E ±15kV ESD-Protected USB Level Translators in UCSP ENUMERATE (MAX3343E) The MAX3343E allows software control of USB enumeration. USB specification 1.1 requires a 1.5kΩ pullup resistor to D+ or D- to set the transmission speed (see SPEED). Enumerating the USB requires removing the 1.5kΩ resistor from the circuit, and is accomplished with the MAX3343E by driving ENUMERATE low. With ENUMERATE high, the voltage at SPEED determines how the internal resistor is connected (see the Functional Diagram). VTRM VTRM is the 3.3V output of the internal linear voltage regulator. The regulator is used to power the internal portions of the USB side of the MAX3340E/MAX3343E. VTRM can be used to power external devices with the ability to source up to 15mA. The VTRM regulator’s supply input is VCC. Connect a 1.0µF (or greater) ceramic or plastic capacitor from VTRM to GND, as close to VTRM as possible. MODE MODE is a control input that selects whether differential or single-ended logic signals are recognized by the system side of the MAX3340E/MAX3343E (Tables 1, 2). MODE has an internal pullup to VCC (MAX3340E only). If MODE is forced high or left floating (MAX3340E only), differential input is selected. With differential input selected, outputs D+ and D- follow the differential inputs at VP and VM. If VP and VM are both forced low, an SE0 condition is forced on the USB. Drive MODE and VM low for single-ended input mode. With single-ended input selected, the differential signal on D+ and D- is controlled by VP. If VM is high when MODE is low, D- and D+ are both low forcing an SEO condition. D+ and DD+ and D- are the transmitter I/O connections, and are ESD protected to ±15kV using the Human Body Model, making the MAX3340E/MAX3343E ideal for applications where a robust transmitter is required. RENB (MAX3340E) Drive RENB (receive enable) high to enable VP and VM as receive outputs. When RENB is forced low VP and VM are high impedance. RCV is unaffected by RENB. Connect RENB to OE/ENUMERATE for normal operation. SUSP SUSP, or suspend, is a control input. When SUSP is forced high the MAX3340E/MAX3343E enter low-power state. In this state the quiescent supply current into VCC is less than 200µA if OE/ENUMERATE is floating and D+ and D- are static. In this mode RCV is forced low, and D+ and D- are high-impedance inputs (Table 1d). In suspend mode, VP and VM remain active as receive outputs, VTRM stays on, and the MAX3340E/ MAX3343E continue to receive data from the USB. SPEED SPEED is a control input that selects between lowspeed (1.5Mbps) and full-speed (12Mbps) USB transmission. Internally, it selects whether the 1.5kΩ pullup resistor is connected to D+ (full-speed) or D- (lowspeed) (Functional Diagram). Force SPEED high to select full-speed, or force SPEED low to select lowspeed. 10 VCC In most applications VCC is derived from the USB +5V output. If supplying VCC with an alternative power supply, the input range is 4.0V to 5.5V. Bypass V CC to GND with a 10µF and a 0.1µF capacitor. Place the 0.1µF capacitor closest to the MAX3340E/MAX3343E. External Components External Resistors Two external resistors are required for USB connection, each of them 24.3Ω, ±1%, 1/8W (or greater). Place one resistor in series between D+ of the MAX3340E/ MAX3343E and D+ of the USB connector. Place the other resistor in series between D- of the MAX3340E/ MAX3343E and D- of the USB connector. The Typical Operating Circuit shows these connections. External Capacitors Four external capacitors are recommended for proper operation. Use a 0.1µF ceramic for decoupling VL, a 0.1µF ceramic and a 10µF electrolytic for decoupling VCC, and a 1.0µF (or greater) ceramic or plastic filter capacitor on VTRM. Return all capacitors to GND. Powering External Components with VTRM VTRM is the output of the internal 3.3V linear regulator, and requires an external ceramic capacitor, as detailed in the VTRM section above. VTRM can source up to 15mA at 3.3V for powering external devices. Note that the source of power for the internal regulator is usually the USB provided 5V; if so, any devices powered from VTRM will lose power if the USB connection is broken. If D+ or D- is shorted to +5V (a fault condition), VTRM follows a diode drop below. If any external circuitry is powered from VTRM, it is recommended that the circuitry be either +5V tolerant, or that an external protection zener is used. ______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translators in UCSP MAX3340E MAX3343E 200Ω + 5pF - GND or VCC MAX3340E MAX3343E 25pF (b) LOAD FOR VP, VM AND RCV (a) LOAD FOR ENABLE AND DISABLE TIME, VP/VM D+ or D- TEST POINT VM or VP or RCV VP or VM 3.3V MAX3340E/MAX3343E TEST POINT MAX3340E MAX3343E TEST POINT 24Ω MAX3340E MAX3343E 24Ω TEST POINT 200Ω D+ or D- 1.5kΩ CL 15kΩ (c) LOAD FOR D+/D- 50pF + - GND or VCC (d) LOAD FOR ENABLE AND DISABLE TIME, D+/D- Figure 4. Test Circuits Data Transfer Receiving Data from the USB (MAX3340E) Data received from the USB are output to VP/VM in either of two ways, differentially or single-ended. To receive data from the USB, force OE/ENUMERATE and RENB high, and force SUSP low. Differential data arriving at D+/D- appears as differential logic signals at VP/VM, and as a single-ended logic signal at RCV. If both D+ and D- are low, then VP and VM are low, signaling an SE0 condition on the bus; RCV is undefined. See Table 1. Receiving Data from the USB (MAX3343E) Data received from the USB are output to VP/VM and RCV in either of two ways, differentially or single ended. To receive data from the USB, force OE high, and force SUSP low. Differential data arriving at D+/D- appears as differential logic signals at VP/VM, and as a singleended logic signal at RCV. If both D+ and D- are low, then VP and VM are low, signaling an SE0 condition on the bus; RCV is undefined. See Table 2. Transmitting Data to the USB (MAX3340E) The MAX3340E outputs data to the USB differentially on D+ and D-. The logic driving signals may be either differential or single-ended. For sending differential logic, force MODE high or let it float, force OE/ENUMERATE, RENB and SUSP low, and apply data to VP and VM. If sending single-ended logic, force MODE low, force RENB, SUSP, OE/ENUMERATE, and VM low, and apply data to VP. With VP low, D+ is low and D- high, resulting in a Logic 0. With VP high, D+ is high and D- low resulting in a Logic 1 state. See Table 1. Transmitting Data to the USB (MAX3343E) The MAX3343E outputs data to the USB differentially on D+ and D-. The logic driving signals may be either differential or single ended. For sending differential logic, force MODE high, force OE and SUSP low, and apply data to VP and VM. If sending single-ended logic, force MODE, SUSP, OE, and VM low, and apply data to VP. With VP low, D+ is low and D- high, resulting in a logic 0 state. With VP high, D+ is high and D- low resulting in a logic 1 state. See Table 2. ______________________________________________________________________________________ 11 MAX3340E/MAX3343E ±15kV ESD-Protected USB Level Translators in UCSP Table 1a. MAX3340E Truth Table, Transmit (MODE = 0) OE/ENUMERATE = 0 (TRANSMIT), RENB = 0 INPUT OUTPUT RESULT VP 0 VM 0 D+ 0 D1 RCV 0 0 1 0 0 X SEO Logic 0 1 0 1 0 1 Logic 1 1 1 0 0 X SEO Table 1b. MAX3340E Truth Table, Transmit (MODE = 1) OE/ENUMERATE = 0 (TRANSMIT), RENB = 0 INPUT OUTPUT RESULT VP VM D+ D- RCV 0 0 0 0 X SEO 0 1 0 1 0 Logic 0 1 0 1 0 1 Logic 1 1 1 1 1 X Undefined Table 1c. MAX3340E Truth Table, Receive OE/ENUMERATE = 1 (RECEIVE), RENB = 1 INPUT OUTPUT RESULT D+ D- VP VM RCV 0 0 0 0 X SEO 0 1 0 1 0 Logic 0 1 0 1 0 1 Logic 1 1 1 1 1 X Undefined Table 1d. MAX3340E Function Select 12 SUSP OE/ENUMERATE RENB D+/D- RCV VP/VM FUNCTION 0 0 0 Driving Active High-Z Normal driving (differential receiver active) 0 0 1 Driving Active Active Conflict state: not permitted 0 1 0 High-Z Active High-Z RPULLUP connected 0 1 1 High-Z Active Active Receiving 1 0 or 1 0 or 1 High-Z 0 Active Low-power state 0 Float 0 or 1 High-Z Active High-Z RPULLUP disconnected 1 Float 0 or 1 High-Z 0 Active RPULLUP disconnected ______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translators in UCSP MAX3340E/MAX3343E Table 2a. MAX3343E Truth Table, Transmit (MODE = 0) OE = 0 (TRANSMIT) INPUT OUTPUT RESULT VP VM D+ D- RCV 0 0 0 1 0 0 1 0 0 X SE0 1 0 1 0 1 Logic 1 1 1 0 0 X SE0 Logic 0 Table 2b. MAX3343E Truth Table, Transmit (MODE = 1) OE = 0 (TRANSMIT) INPUT OUTPUT RESULT VP VM D+ D- RCV 0 0 0 0 X SE0 0 1 0 1 0 Logic 0 1 0 1 0 1 Logic 1 1 1 1 1 X Undefined Table 2c. MAX3343E Truth Table, Receive OE = 1 (RECEIVE) INPUT OUTPUT RESULT D+ D- VP VM RCV 0 0 0 0 X SE0 0 1 0 1 0 Logic 0 1 0 1 0 1 Logic 1 1 1 1 1 X Undefined Table 2d. MAX3343E Function Select SUSP ENUMERATE OE D+/D- RCV VP/VM 0 0 0 Driving Active High-Z Normal driving 0 0 1 High-Z Active Active Normal receiving, RPULLUP disconnected 0 1 0 Driving Active High-Z Normal driving 0 1 1 High-Z Active Active Normal receiving, RPULLUP connected 1 0 0 or 1 High-Z 0 Active Suspend mode, RPULLUP disconnected 1 1 0 or 1 High-Z 0 Active Suspend mode, RPULLUP connected FUNCTION ______________________________________________________________________________________ 13 MAX3340E/MAX3343E ±15kV ESD-Protected USB Level Translators in UCSP ESD protection To protect the MAX3340E/MAX3343E against ESD, D+ and D- have extra protection against static electricity to protect the devices up to ±15kV. The ESD structures withstand high ESD in all states; normal operation, suspend, and powered down. In order for the 15kV ESD structures to work correctly a 1µF or greater capacitor must be connected from VTRM to GND. ESD protection can be tested in various ways; the D+ and D- input/output pins are characterized for protection to the following limits: 1) ±15kV using the Human Body Model. 2) ±5kV using the Contact Discharge method specified in IEC 1000-4-2. 3) ±9kV using the IEC 1000-4-2 Air-Gap method. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 5a shows the Human Body Model, and Figure 5b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. IEC 1000-4-2 The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX3340E/MAX3343E help you design equipment that meets Level 2 of IEC 1000-4-2, without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 1000-4-2 is a higher peak current in IEC 1000-4-2, because series resistance is lower in the IEC 1000-4-2 model. Hence, the ESD withstand voltage measured to IEC 1000-4-2 is generally lower than that measured using the Human Body Model. Figure 6a shows the IEC 1000-4-2 model. The Air-Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized. 14 RC 1MΩ CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF RD 1500Ω DISCHARGE RESISTANCE DEVICE UNDER TEST STORAGE CAPACITOR Figure 5a. Human Body ESD Test Models IP 100% 90% Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES 36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM Figure 5b. Human Body Model Current Waveform RC 50MΩ to 100MΩ CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 6a. IEC 1000-4-2 ESD Test Model ______________________________________________________________________________________ DEVICE UNDER TEST ±15kV ESD-Protected USB Level Translators in UCSP SYSTEM POWER 0.1µF CERAMIC 0.1µF CERAMIC ASIC 10µF ELECTROLYTIC USB CABLE PC VCC USB POWER 24.3Ω 1% VL D+ VP MAX3340E MAX3343E VM RCV D+ 24.3Ω 1% D- D- (RENB) ENUMERATE (OE/ENUMERATE) OE GND SUSP GND 15kΩ 15kΩ SPEED MODE VTRM 1.0µF CERAMIC () ARE FOR THE MAX3340E Machine Model The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. Of course, all pins require this protection during manufacturing, not just RS-232 inputs and outputs. Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports. UCSP Reliability The UCSP represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. CSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a CSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater consideration for a CSP package. CSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Table 3 shows the testing done to characterize the CSP reliability performance. In conclusion, the UCSP is capable of performing reliably through environmental stresses as indicated by the results in the table. Additional usage data and recommendations are detailed in the UCSP application note, which can be found on Maxim’s web- site at www.maximic.com. ______________________________________________________________________________________ 15 MAX3340E/MAX3343E Typical Operating Circuit MAX3340E/MAX3343E ±15kV ESD-Protected USB Level Translators in UCSP Table 3. Reliability Test Data TEST Temperature Cycle Operating Life Moisture Resistance Low-Temperature Storage Low-Temperature Operational Solderability ESD High-Temperature Operating Life CONDITIONS DURATION NO. OF FAILURES PER SAMPLE SIZE -35°C to +85°C, -40°C to +100°C 150 cycles, 900 cycles 0/10, 0/200 TA = +70°C 240hr 0/10 +20°C to +60°C, 90% RH 240hr 0/10 -20°C 240hr 0/10 -10°C 24hr 0/10 8hr steam age — 0/15 ±2000V, Human Body Model — 0/5 TJ = +150°C 168hr 0/45 Functional Diagram VCC LINEAR REGULATOR MAX3340E MAX3343E VTRM VL 1.5kΩ SPEED INTERNAL POWER OE (OE/ENUMERATE) D+ ENUMERATE (RENB) MODE DSUSP LEVEL SHIFTER AND CONTROL LOGIC RCV VP VM GND () ARE FOR MAX3340E 16 ______________________________________________________________________________________ ±15kV ESD-Protected USB Level Translators in UCSP TSSOP,NO PADS.EPS ______________________________________________________________________________________ 17 MAX3340E/MAX3343E Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 4x4 UCSP.EPS MAX3340E/MAX3343E ±15kV ESD-Protected USB Level Translators in UCSP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.