POWERINT DI-52

®
Design Idea DI-52
DPA-Switch™
60 W DC-DC Converter
Application
Device
Power Output
Input Voltage
Output Voltage
Topology
Telecom
DPA426R
60 W
36-75 VDC
12 V
Forward Sync. Rect.
Design Highlights
Resistor R1 programs the under/over voltages and linearly
reduces the maximum duty cycle with input voltage to
prevent core saturation during load transients. Components
D1, D2, C9, and L2 implement a resonant clamp circuit to
catch and re-circulate the transformer leakage energy during
normal operation, with Zener VR1 providing absolute
clamping for transient conditions.
• Low component count
• High efficiency: 91.5% at 36 VDC using synchronous
rectification
• Capacitor coupled synchronous rectification allows higher
output voltages without overstressing MOSFET gates
• No current sense resistor or current transformer required
• Output overload, open loop and thermal protection
• 300 kHz switching frequency to allow sufficient
transformer reset time
• 3.55 x 2.1 x 0.6 inch (approx. 13.4 W/cubic inch)
Capacitor C21 charges the gate of Q2, the forward synchronous
rectifier MOSFET. Resistor R21 limits gate oscillation and
R22 provides gate pull down. Zener diode VR20 limits the
Q2 gate voltage during conduction and also reverse charges
(resets) C21 during the Q2 off time.
Operation
A similar drive technique is used for the catch synchronous
rectifier MOSFET Q1 (with C22, R23, R24, and VR21).
MOSFET Q1 is driven by the transformer (T1) reset voltage
and operates only when Q2 is off. Diode D20 provides a
DPA-Switch greatly simplifies the design compared to a discrete
implementation. The capacitor coupled synchronous rectifier
drive used in this design is useful for higher voltage outputs, still
allowing passive MOSFET drive without gate overvoltage,
which would result from direct resistor drive.
C7 1 nF
1.5 kV
R14
10 Ω
T1
6,7
+ VIN
36-75 VDC
1
L1
1 µH
2.5 A
D1
ESD1
R1
619 kΩ
1%
R21
R22
R20 10 Ω 10 kΩ
0.5 Ω
1W
9,8
10,9
VR21 R23
15 V 10 Ω
C23
C24
100 µF 100 µF
16 V 16 V
C25
1 µF
50 V
12 V, 5 A
D20
12 CWQ
10 FN
RTN
Q1
Si4486
L3
2.2 mH
40 mA
5
2
D4
BAV19WS
R10
38 kΩ
1%
R7 U2
10 kΩ
C8
1 µF
U1
DPA426R
D
DPA-Switch
L
CONTROL
D2
ESD1
S
VR1
SMBJ
150 A
X
C
D3
BAV19WS
R6
150 Ω
R4
1.0 Ω
F
R3
11 kΩ
1%
U2
PC357
NT
C5
0.22 µF
C6
68 µF
10 V
Figure 1. DPA426R - 60 W, 12 V, 5 A, DC-DC Converter.
.
DI-52
4,5
R24
10 kΩ
C22
1 nF
D3
BAV19WS
4
L2
220 µH
-VIN
C20
C21
1 nF 2.2 nF
VR20
15 V
Q2
Si4486
C9
150 pF
200 V
C1-C4
0.22 µF
100 V
L4
40 µH
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C13
100 nF
R12
5.1 Ω
C17
1 µF
C15
10 µF
10 V
U3
LMV431
AIM5X
R9
220 Ω
R11
10 kΩ
1%
PI-3550-062403
July 2003
DI-52
conduction path for the output inductor (L4) current when the
transformer reset is complete.
Key Design Points
• Transformer core reset is critical in this design. MOSFET
gate loading will affect the transformer-reset waveform.
Capacitors C20, C22 and CQ1GS will all load transformer
reset. Choose values to ensure sufficient reset at low line
and safe maximum drain voltage at high line. Also use
300 kHz operation for longest reset time.
• Capacitors C20 and C22 will capacitively drive MOSFET
gate capacitances CQ2GS and CQ1GS, respectively. C20 and
C22 should be chosen to ensure that gate drive voltage
attains turn-on threshold of MOSFET (VgTH) at worst case
conditions (low line for forward MOSFET).
• Reduce transformer leakage inductance by filling each
winding layer across the entire width of the bobbin.
90
Efficiency (%)
Core Material
Ferroxcube P/N: EFD25, ungapped
Bobbin
10-pin EFD25 surface mount bobbin
Winding Details
Primary 5T + 5T, 4 x 26 AWG
Bias 5T, 1 x 30 AWG
12 V 6T, 4 x 26 AWG
Winding Order and
Pin Numbers
Bias (2-5), Primary-1 (4-NC),
12 V (9,10-6,7), Primary-2 (NC-1)
Primary Inductance
Pin (1-4): 190 µH ±25% @ 300 kHz
Primary Resonant
Frequency
3.8 MHz (minimum)
Leakage Inductance
1 µH (maximum)
Table 1. Transformer Construction Information.
PI-3551-060503
100
TRANSFORMER PARAMETERS
INDUCTOR PARAMETERS
Core Material
Ferroxcube P/N: EFD20-3F3
gap for inductance required
Bobbin
10-pin EFD20 surface mount bobbin
Winding Details
Main 18T, 3 x 24 AWG
Winding Order and
Pin Numbers
Main (4,5-9,10)
Inductance
Pin (4,5-9,10): 40 µH ±10%
@ 300 kHz
80
70
36 VDC
48 VDC
72 VDC
60
50
0
1
2
3
4
5
Table 2. L4 Output Inductor Design Parameters.
Pout (W)
Figure 2. Efficiency vs. Output Power.
A
7/03
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