White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* 512K x 72 SYNCHRONOUS PIPELINE BURST ZBL SRAM FEATURES DESCRIPTION Fast clock speed: 150, 133, and 100MHz Fast access times: 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns High performance 3-1-1-1 access rate The WEDC SyncBurst - SRAM employs high-speed, low-power CMOS design that is fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 512K x 36 SSRAMs into a single BGA package to provide 512K x 72 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The ZBL or Zero Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied “High or Low.” Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. 2.5V ± 5% power supply Common data inputs and data outputs Byte write enable and global write control Six chip enables for depth expansion and address pipeline Internally self-timed write cycle Burst control pin (interleaved or linear burst sequence) Automatic power-down for portable applications Commercial, industrial and military temperature ranges Packaging: • 152 PBGA package 17 x 23mm * This product is under development, is not qualified or characterized and is subject to change without notice. BENEFITS 30% space savings compared to equivalent TQFP solution Reduced part count 24% I/O reduction Laminate interposer for optimum TCE match Low Profile Reduce layer count for board routing Suitable for hi-reliability applications User configurable as 1M x 36 or 2M x 18 Upgradable to 1M x 72 (contact factory for availability) White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* FUNCTIONAL BLOCK DIAGRAM 512K x 36 SSRAM A0-18 SA BWa# BWa# BWb# BWb# BWc# BWc# DQPA DQPA BWd# BWd# DQA0-7 DQA0-7 WE0# WE0# DQPB DQPB OE0# OE0# DQB0-7 DQB0-7 CLK0# CLK DQPC DQPC CKE0# CKE# DQC0-7 DQC0-7 CS10# CS1# DQPD DQPD CS20# CS2# DQD0-7 DQD0-7 CS20 CS2 ADV0 ADV LB0# LB0# ZZ ZZ 512K x 36 SSRAM SA BWe # BWa# BWf # BWb# BWg# BWc# DQPA DQPE BWh# BWd# DQA0-7 DQE0-7 WE1# WE0# DQPB DQPF OE1# OE0# DQB0-7 DQF0-7 CLK1# CLK DQPC DQPG CKE1# CKE DQC0-7 DQG0-7 CS113# CS1# DQPH DQPH CS21# CS2# DQD0-7 DQH0-7 CS21# CS2 ADV1 ADV LB0# ZZ White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* PIN CONFIGURATION (TOP VIEW) A B C D E F G H J K L M N P R T U 1 CKE0# CLK0 BWA# BWC# CS10# A7 A18 A9 A8 A17 ADV1 CKE1# CLK1 BWE# BWG# CS11# 2 ADV0 WE0# CS20# BWB# BWD# CS20 DQC0 DQC1 A6 DQF4 DQF5 OE1# WE1# CS21# BWF# BWH# CS21 3 OE0# DQB7 DQC2 DQC3 DQC4 DQC5 DQC7 DQC6 DQF2 DQF3 DQF6 DQF7 DQPF DQF1 DQF0 DQG0 DQG3 4 DQB2 DQB5 DQPC VSS VCCQ VCCQ VSS VCC VSS VCC VCC VSS VCCQ VSS DQG1 DQG2 DQPG 5 DQB4 DQB3 DQPB VSS VCCQ VCCQ VCC VCC VSS VCC VCC VCCQ VCCQ VSS DQG4 DQG5 DQG6 6 DQB6 DQB0 DQB1 VSS VCCQ VSS VCC VCC VSS VCC VSS VSSQ VCCQ VSS DQH1 DQH0 DQG7 7 DNU DQA7 DQD7 DQD6 DQD5 DQD4 DQD3 DQD2 DQD1 DQD0 DQE6 DQE7 DQE5 DQE4 DQH2 DQH4 DQH3 8 DQA6 DQA3 DQA4 DQA5 DQPD DNU* A1 A2 A4 A14 A12 A10 DQE3 DQE2 DQE1 DQH7 DQH5 9 DQA2 DQA1 DQA0 DQPA ZZ A0 A3 A5 A16 A15 A13 A11 LBO# DQE0 DQPE DQPH DQH6 NOTES: DNU means Do Not Use and are reserved for future use. * Pin F8 reserved for A19 upgrade to 1M x 72. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* FUNCTION DESCRIPTION The WEDPZ512K72S-XBX is an ZBL SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE#, LBO# and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable (CKE#) pin allows the operation of the chip to be suspended as long as necessary. When CKE# is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL SSRAM latches external address and initiates a cycle when CKE and ADV are driven low at the rising edge of the clock. Output Enable (OE#) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE# is driven low, the write enable input signals WE# are driven high, and ADV driven low. The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE# must be driven low for the device to drive out the requested data. Write operation occurs when WE# is driven low at the rising edge of the clock. BW#[h:a] can be used for byte write operation. The pipe-lined ZBL SSRAM uses a latelate write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE# and address are registered, and the data associated with that address is required two cycles later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO# pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after two cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates after two cycles of wake up time. BURST SEQUENCE TABLE (Interleaved Burst, LBO# = High) LBO# Pin High First Address Case 1 (Linear Burst, LBO# = Low) Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 1 0 1 1 0 0 0 LBO# Pin High Case 1 Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0 Fourth Address NOTE: LBO pin must be tied to High or Low, and Floating State must not be allowed. First Address Fourth Address White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* TRUTH TABLES SYNCHRONOUS TRUTH TABLE CE#x H X L X L X L X L X X ADV L H L H L H L H L H X WE# X X H X H X L X L X X BW#x X X X X X X L L H H X OE# X X L L H H X X X X X CKE# L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Address Accessed N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address Operation Deselect Continue Deselect Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock NOTES: 1) X means “Don’t Care.” 2) The rising edge of clock is symbolized by ( ↑ ). 3) A continue deselect cycle can only be entered if a deselect cycle is executed first. 4) WRITE# = L means Write operation in WRITE TRUTH TABLE. WRITE# = H means Read operation in WRITE TRUTH TABLE. 5) Operation finally depends on status of asynchronous input pins (ZZ and OE#). 6) CE#x refers to the combination of CS#1 and CS#2. WRITE TRUTH TABLE WE# H L L L L L L BW#a X L H H H L H BW#b X H L H H L H BW#c X H H L H L H BW#d X H H H L L H Operation Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP NOTES: 1) X means “Don’t Care.” 2) All inputs in this table must meet setup and hold time around the rising edge of CLK (↑ ). 3) Replace BW#a with BW#e, BW#b, with BW#f, BW#c with BW#g and BW#d with BW#h for operation of IC2. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* ABSOLUT MAXIMUM RATINGS* VIN Voltage or any other pin relative to VSS -0.3V to +3.6V Voltage on VCC supply relative to VSS -0.3V to +3.6V Storage temperature (BGA) -55°C to +150°C * Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS (-55°C TA +125°C) Description Symbol Min Max Units Input High (Logic 1) Voltage VIH Conditions 1.7 VCC +0.3 V Notes 1 Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1 2 Input Leakage Current IIL VCC = Max, 0V VIN VCC -4 +4 µA Output Leakage Current ILO Output(s) Disabled, VOUT = VSS to VCCQ -2 +2 µA Output High Voltage VOH IOH = -1.0mA 2.0 --- V 1 Output Low Voltage VOL IOL = 1.0mA --- 0.4 V 1 Supply Voltage VCC 2.375 2.625 V 1 2.375 2.625 V 1 150MHz (Max) 133MHz (Max) 100MHz (Max) Units Notes 1 I/O Power Supply VCCQ NOTES: 1) All voltages referenced to VSS (GND) 2) ZZ pin has an internal pull-up and input leakage = ± 20 µA. DC CHARACTERISTICS (-55°C TA + 125°C) Description Symbol Conditions Power Supply Current: Operating IDD Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle Time ≥ TCYC MIN; VCC = MAX; Output Open 700 650 600 mA Power Supply Current: Standby ISB2 Device Deselected; VCC = MAX; All Inputs ≤ VIL or ≥ VIH All Inputs Static; CLK Frequency = MAX Output Open, ZZ ≥ VCC - 0.2V 120 120 120 mA Clock Running Standby Current ISB Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 or VCC - 0.2; f = MAX ; ZZ ≤ VIL 180 180 160 mA NOTE: IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. BGA CAPACITANCE THERMAL RESISTANCE (TA = + 25°C, f = 1MHz) Description Control Input Capacitance (LBO#, ZZ) Symbol Max Units Notes CIC 16 pF 1 Parameter Thermal Resistance: Die Junction to Ambient Symbol Max Unit θJA 28.7 °C/W Control Input Capacitance CI 8 pF 1 Thermal Resistance: Die Junction to Ball θJB 16.0 °C/W Input/Output Capacitance (DQ) CO 10 pF 1 Thermal Resistance: Die Junction to Case θJC 7.1 °C/W Address Capacitance CA 16 pF 1 6 Clock Capacitance CCK NOTE: 1) This parameter is not tested but guaranteed by design. pF 1 Note: Refer to Application Note “PBGA Thermal Resistance Corrleation” for further information regarding WEDC’s thermal modeling. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* AC CHARACTERISTICS (-55°C TA +125°C) Parameter Symbol 150MHz Min 133MHz Max Min 100MHz Max Max 10.0 Units Clock Time tCYC 6.7 Clock Access Time tCD -- 3.8 -- 4.2 -- 5.0 ns Output enable to Data Valid tOE -- 3.8 -- 4.2 -- 5.0 ns Clock High to Output Low-Z tLZC 1.5 -- 1.5 -- 1.5 -- ns Output Hold from Clock High tOH 1.5 -- 1.5 -- 1.5 -- ns Output Enable Low to output Low-Z tLZOE 0.0 -- 0.0 -- 0.0 -- ns Output Enable High to Output High-Z tHZOE -- 3.0 -- 3.5 -- 3.5 ns Clock High to Output High-Z tHZC -- 3.0 -- 3.5 -- 3.5 ns Clock High Pulse Width tCH 2.5 -- 2.5 -- 3.0 -- ns Clock Low Pulse Width tCL 2.5 -- 2.5 -- 3.0 -- ns Address Setup to Clock High tAS 1.5 -- 1.5 -- 1.5 -- ns CKE Setup to Clock High tCES 1.5 -- 1.5 -- 1.5 -- ns Data Setup to Clock High tDS 1.5 -- 1.5 -- 1.5 -- ns Write Setup to Clock High tWS 1.5 -- 1.5 -- 1.5 -- Address Advance to Clock High tADVS 1.5 Chip Select Setup to Clock High tCSS 1.5 Address Hold to Clock high tAH 0.5 -- 0.5 -- 0.5 -- ns CKE Hold to Clock High tCEH 0.5 -- 0.5 -- 0.5 -- ns Data Hold to Clock High tDH 0.5 -- 0.5 -- 0.5 -- ns Write Hold to Clock High tWH 0.5 -- 0.5 -- 0.5 -- ns tADVH 0.5 -- 0.5 -- 0.5 -- ns Address Advance to Clock High 7.5 Min 1.5 ns ns 1.5 1.5 ns 1.5 ns 0.5 -0.5 --0.5 -ns Chip Select Hold to Clock High tCSH NOTES: 1) All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CS#x is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2) Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled. 3) A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low. Both cases must meet setup and hold times. AC TEST CONDITIONS Parameter Value Input Pulse Level 0 to 2.5V Input Rise and Fall Time 1.0V/ns Input and Output Timing Reference Levels 1.25V Output Load See Output Load (A & B) OUTPUT LOAD (A) OUTPUT LOAD (B) (for TLZC, TLZOE, THZOE, and THZC) Dout RL=50Ω Zo=50Ω +2.5V VL=1.25V 50pF* 1667Ω Dout *Including Scope and Jig Capacitance 1538Ω 5pF* White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE Description Conditions Symbol ZZ ≥ VIH ISB2Z 20 mA ZZ active to input ignored tZZ 2 cycle Current during SNOOZE MODE ZZ inactive to input sampled tRZZ ZZ active to snooze current tZZI ZZ inactive to exit snooze current tRZZI Min Max Units 2 cycle 2 cycle O ns SNOOZE MODE TIMING DIAGRAM CLOCK t ZZ t RZZ ZZ t ZZI ISUPPLY ALL INPUTS (except ZZ) t RZZI I ISB2Z DESELECT or READ Only Deselect or Read Only Normal Operation Cycle Output (Q) HIGH-Z DON'T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* TIMING WAVEFORM OF READ CYCLE tCH tCL CLKX tCYC tCES tCEH CKEX# tAS tAH A1 Address A2 tWS tWH tCSS tCSH tADVS tADVH A3 WRITE# CSX# ADVX OE# tOE tHZOE tLZOE Q1-1 Data Out NOTES: tCD tOH Q2-1 tHZC Q2-2 Q2-3 Q2-4 WRITE# = L means WEx# = L, and BWx# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#. Q3-1 Q3-2 Q3-3 Q3-4 Don¢t Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* TIMING WAVEFORM OF WRITE CYCLE tCH tCL CLKX tCYC tCES tCEH CKEX# Address A2 A1 A3 WRITE# CSX# ADVX OE# tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tHZOE Data Out Q0-3 NOTES: Q0-4 WRITE# = L means WEx# = L, and BWx# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#. Don’t Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* TIMING WAVEFORM OF SINGLE READ/WRITE tCH tCL CLKX tCYC tCES tCEH CKEX# Address A1 A2 A3 A4 Q1 Q3 A5 A6 A8 A7 A9 WRITE# CSX# ADVX OE# tOE tLZOE Data Out D2 NOTES: Q6 Q7 tDH tDS Data In Q4 WRITE# = L means WEx# = L, and BWx# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#. D5 Don’t Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* TIMING WAVEFORM OF CKE OPERATION tCL tCH CLKX tCES tCEH tCYC CKEX# Address A1 A2 A3 A4 A5 A6 WRITE# CSX# ADVX OE# tCD tLZC Data Out tHZC Q1 Q3 tDH tDS Data In Q4 D2 NOTES: WRITE# = L means WEx# = L, and BWx# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#. Don¢t Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* TIMING WAVEFORM OF CE OPERATION tCH tCL CLKX tCYC tCEH tCES CKEX# Address A1 A2 A3 A4 A5 WRITE# CSX# ADVX OE# tHZC tOE tLZOE Data Out Q1 tCD tLZC Q4 Q2 tDS tDH Data In D3 NOTES: WRITE# = L means WEx# = L, and BWx# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#. D5 Don’t Care Undefined White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* PACKAGE DIMENSION: 152 BUMP PBGA BOTTOM VIEW 9 8 7 6 5 4 3 ∅ 0.762 (0.030) NOM 2 1 A B C D E F G 23.1 (0.909) MAX 20.32 (0.800) NOM 1.27 (0.050) NOM H J K L M N P R T U 1.27 (0.050) NOM 0.61 (0.024) NOM 10.16 (0.400) NOM 2.03 (0.080) MAX 17.1 (0.673) MAX ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION WED P Z 512K 72 S - XXX B X DEVICE GRADE: M = Military I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE: B = 152 Plastic Ball Grid Array (PBGA) FREQUENCY (MHz) 100 = 100MHz 133 = 133MHz 150 = 150MHz 2.5V Voltage CONFIGURATION, 512K x 72 SSRAM ZBL PLASTIC WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6 White Electronic Designs WEDPZ512K72S-XBX PRELIMINARY* Document Title 512K x 72 Synchronous SRAM – NBL Revision History Rev # History Release Date Status Rev 0 Rev 1 Initial Release Changes (Pg. 1, 5, 6, 13) 1.1 Block Diagram: Change DQD to DQPD, Font Consistency 1.2 Electrical Characteristics Note 2: Change reference to mA instead of MA. 1.3 DC Characteristics: Adjust location of Units & Notes for ISB2. 1.4 AC Characteristics: Change temperature range to (-55°C ≤ TA ≤ +125°C) 1.5 Package Dimension: Adjust length line to end of package 1.6 Block Diagram: Adjust look for consistency 1.7 DC Characteristics: ISB2 condition should read All Inputs ≤ VIL or ≥ VIH instead of > VIH 1.8 Figure 2: Inputs transition should not be shown fully connected. 1.9 Figure 6: Unknown text deleted from timing diagram 1.10 Package Dimension: Ball diameter arrow corrected to point to ball. Change (Pg. 1) 1.1 Change status from Advanced to Preliminary Changes (Pg. 1, 2) 1.1 Block Diagram: Address lines should be A0-18 1.2 Pin Configuration: Add Note *Pin F8 reserved for A19 upgrade to 1Mx72. Changes (Pg. 1, 5) 1.1 BGA Capacitance: Remove references to temperature in individual conditions 1.2 Change CI from 10pF to 8pF 1.3 Change CA from 20pF to 16pF 1.4 Change CCK from 7pF to 6pF 1.5 Add Control Input Capacitance (CIC) 16pF Changes (Pg. 5) 1.1 Add Thermal Resistance table 1.2 Update current values 1.3 Update package mechanical drawing Changes (Pg. 1, 13, 14, 15) 1.1 Change mechanical drawing to new style February 2001 April 2001 Advanced Advanced November 2001 Preliminary November 2001 Preliminary November 2002 Preliminary May 2003 Preliminary November 2003 Preliminary Rev 2 Rev 3 Rev 4 Rev 5 Rev 6 White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2003 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Rev. 6