ETC WED2ZL361MV-BC

WED2ZL361MV
White Electronic Designs
1Mx36 Synchronous Pipeline Burst NBL SRAM
FEATURES
DESCRIPTION
n Fast clock speed: 166, 150, 133, and 100MHz
The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC’s 32Mb
SyncBurst SRAMs integrate two 1M x 18 SRAMs into a
single BGA package to provide 1M x 36 configuration. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address,
data inputs, and all control signals except output enable and linear burst order are synchronized to input
clock. Burst order control must be tied “High or Low.”
Asynchronous inputs include the sleep mode enable
(ZZ). Output Enable controls the outputs at any given
time. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.
n Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
n Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
n Single +3.3V ± 5% power supply (VDD)
n Snooze Mode for reduced-standby power
n Individual Byte Write control
n Clock-controlled and registered addresses, data
I/Os and control signals
n Burst control (interleaved or linear burst)
n Packaging:
• 119-bump BGA package
n Low capacitive bus loading
FIG. 1
PIN CONFIGURATION
BLOCK DIAGRAM
(TOP VIEW)
3
4
5
6
7
SA
SA
SA
SA
VDD
B
SA
CE 2
SA
ADV
SA
CE 2
NC
C
NC
SA
SA
VDD
SA
SA
NC
D
DQ C
DQP C
V SS
NC
V SS
DQP B
DQ B
E
DQ C
DQ C
V SS
CE 1
V SS
DQ B
DQ B
F
VDD
DQ C
V SS
OE
V SS
DQ B
VDD
G
DQ C
DQ C
BW C
SA
BW B
DQ B
DQ B
H
DQ C
DQ C
V SS
WE
V SS
DQ B
DQ B
J
VDD
VDD
NC
VDD
NC
VDD
VDD
K
DQ D
DQ D
V SS
CLK
V SS
DQ A
DQ A
L
DQ D
DQ D
BW D
NC
BW A
DQ A
DQ A
M
VDD
DQ D
V SS
CKE
V SS
DQ A
VDD
N
DQ D
DQ D
V SS
SA 1
V SS
DQ A
DQ A
P
DQ D
DQP D
V SS
SA 0
V SS
DQP A
DQ A
R
NC
SA
LBO
VDD
NC
SA
NC
T
NC
NC
SA
SA
SA
NC
ZZ
U
VDD
NC
NC
NC
NC
NC
VDD
December 2002 Rev. 2
ECO #15834
BWa
BWb
2
SA
BWc
BWd
1
VDD
A
1M x 18
CLK
CKE
ADV
LBO
CE1
CE2
CE2
OE
WE
ZZ
1M x 18
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
Address Bus
(SA0 SA19)
-
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
DQa
DQPa
1
- DQd
- DQPd
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WED2ZL361MV
White Electronic Designs
FUNCTION DESCRIPTION
The WED2ZL361MV is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa. All inputs (with the exception of OE, LBO and ZZ)
are synchronized to rising clock edges.
Write operation occurs when WE is driven low at the
rising edge of the clock. BW[d:a] can be used for byte
write operation. The pipe-lined NBL SSRAM uses a
late-late write cycle to utilize 100% of the bandwidth. At
the first rising edge of the clock, WE and address are
registered, and the data associated with that address
is required two cycle later.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been deselected in order to load a new address for next operation.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial
state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low,
linear burst sequence is selected. And when this pin is
high, Interleaved burst sequence is selected.
Clock Enable (CKE) pin allows the operation of the chip
to be suspended as long as necessary. When CKE is
high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.
Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE
is driven low, the write enable input signals WE are
driven high, and ADV driven low. The internal array is
read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven
out of the SRAM. During read operation OE must be
driven low for the device to drive out the requested data.
BURST SEQUENCE TABLE
(Linear Burst, LBO = Low)
(Interleaved Burst, LBO = High)
LBO Pin High
First Address
Fourth Address
Case 1
A1
A0
0
0
0
1
1
0
1
1
Case 2
A1
A0
0
1
0
0
1
1
1
0
Case 3
A1
A0
1
0
1
1
0
0
0
1
Case 4
A1
A0
1
1
1
0
0
1
0
0
LBO Pin High
First Address
Fourth Address
NOTE 1: LBO pin must be tied to High or Low, and Floating State
must not be allowed.
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Case 1
A1
A0
0
0
0
1
1
0
1
1
Case 2
A1
A0
0
1
1
0
1
1
0
0
Case 3
A1
A0
1
0
1
1
0
0
0
1
Case 4
A1
A0
1
1
0
0
0
1
1
0
WED2ZL361MV
White Electronic Designs
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CEx
ADV
WE
BWx
OE
CKE
Address Accessed
Operation
H
L
X
X
X
L
CLK
N/A
Deselect
X
H
X
X
X
L
N/A
Continue Deselect
L
L
H
X
L
L
External Address
Begin Burst Read Cycle
X
H
X
X
L
L
Next Address
Continue Burst Read Cycle
L
L
H
X
H
L
External Address
NOP/Dummy Read
X
H
X
X
H
L
Next Address
Dummy Read
L
L
L
L
X
L
External Address
Begin Burst Write Cycle
X
H
X
L
X
L
Next Address
Continue Burst Write Cycle
L
L
L
H
X
L
N/A
NOP/Write Abort
X
H
X
H
X
L
Next Address
Write Abort
X
X
X
X
X
H
Current Address
Ignore Clock
NOTES:
1. X means “Don’t Care.”
2. The rising edge of clock is symbolized by ( )
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE).
6. CEx refers to the combination of CE1, CE2 and CE2.
WRITE TRUTH TABLE
WE
BWa
BWb
BWc
BWd
H
X
X
X
X
Operation
Read
L
L
H
H
H
Write Byte a
L
H
L
H
H
Write Byte b
L
H
H
L
H
Write Byte c
L
H
H
H
L
Write Byte d
L
L
L
L
L
Write All Bytes
L
H
H
H
H
Write Abort/NOP
NOTES:
1. X means “Don’t Care.”
2. All inputs in this table must meet setup and hold time around the rising edge of
CLK ( ).
3
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WED2ZL361MV
White Electronic Designs
A BSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS
VIN (DQx)
VIN (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.3V to +4.6V
-0.3V to +4.6V
-0.3V to +4.6V
-65°C to +150°C
100mA
*Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS VOLTAGE REFERENCED TO:
VSS = 0V, TA = 0°C TO +70°C; COMMERCIAL OR TA = -40°C TO +85°C; INDUSTRIAL
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
Conditions
VIH
V IL
ILI
0V £ VIN £ VDD
ILO
Output(s) Disabled, 0V £ VIN £ VDD
VOH
IOH = -4.0mA
VOL
IOL = 8.0mA
VDD
Min
2.0
-0.3
-5
-5
2.4
–
3.135
Max
VDD +0.5
0.8
5
5
–
0.4
3.465
Units
V
V
µA
µA
V
V
V
Notes
1
1
2
1
1
1
NOTES:
1. All voltages referenced to VSS (GND)
2. ZZ pin has an internal pull-up, and input leakage = ± 10µA.
DC CHARACTERISTICS
Description
Symbol
Conditions
166
MHz
150
MHz
133
MHz
100
MHz
840
800
760
640
mA
1, 2
30
60
60
60
60
mA
2
30
60
60
60
60
mA
2
240
220
180
160
mA
2
Typ
Power Supply
Current: Operating
I DD
Device Selected; All Inputs £ VIL or ³ VIH; Cycle
Time = TCYC MIN; VDD = MAX; Output Open
Power Supply
Current: Standby
I SB 2
Device Deselected; VDD = MAX; All Inputs£ VSS + 0.2
or VDD - 0.2; All Inputs Static; CLK Frequency = 0;
Power Supply
Current: Current
I SB 3
Clock Running
I SB 4
Units Notes
ZZ £ VIL
Standby Current
Device Selected; All Inputs £ VIL or ³ VIH; Cycle
Time = TCYC MIN; VDD = MAX; Output Open;
ZZ ³ VDD - 0.2V
Device Deselected; VDD = MAX; All Inputs
£ VSS + 0.2 or VDD - 0.2; Cycle Time = TCYC
MIN; ZZ £ VIL
NOTES:
1. IDD is specified with no output current and increases with faster cycle times.
IDD increases with faster cycle times and greater output loading.
2. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.
BGA CAPACITANCE
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
Symbol
CI
CO
CA
CCK
Conditions
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
NOTES:
1. This parameter is sampled.
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Typ
5
6
5
3
Max
7
8
7
5
Units
pF
pF
pF
pF
Notes
1
1
1
1
WED2ZL361MV
White Electronic Designs
AC CHARACTERISTICS
Symbol
166MHz
Parameter
Min
Clock Time
Max
150MHz
Min
Max
Max
7.5
100MHz
Min
Max
10.0
Units
tCYC
6.0
Clock Access Time
t CD
--
3.5
--
3.8
--
4.2
--
5.0
Output enable to Data Valid
t OE
--
3.5
--
3.8
--
4.2
--
5.0
ns
Clock High to Output Low-Z
t LZC
1.5
--
1.5
--
1.5
--
1.5
--
ns
Output Hold from Clock High
6.7
133MHz
Min
ns
ns
t OH
1.5
--
1.5
--
1.5
--
1.5
--
ns
Output Enable Low to output Low-Z
t LZOE
0.0
--
0.0
--
0.0
--
0.0
--
ns
Output Enable High to Output High-Z
t HZOE
--
3.0
--
3.0
--
3.5
--
3.5
ns
Clock High to Output High-Z
t HZC
--
3.0
--
3.0
--
3.5
--
3.5
ns
Clock High Pulse Width
t CH
2.2
--
2.5
--
3.0
--
3.0
--
ns
Clock Low Pulse Width
t CL
2.2
--
2.5
--
3.0
--
3.0
--
ns
Address Setup to Clock High
tAS
1.5
--
1.5
--
1.5
--
1.5
--
ns
CKE Setup to Clock High
tCES
1.5
--
1.5
--
1.5
--
1.5
--
ns
Data Setup to Clock High
t DS
1.5
--
1.5
--
1.5
--
1.5
--
ns
Write Setup to Clock High
tWS
1.5
--
1.5
--
1.5
--
1.5
--
ns
Address Advance to Clock High
tADVS
1.5
--
1.5
--
1.5
--
1.5
--
ns
Chip Select Setup to Clock High
tCSS
1.5
--
1.5
--
1.5
--
1.5
--
ns
t AH
0.5
--
0.5
--
0.5
--
0.5
--
ns
CKE Hold to Clock High
tCEH
0.5
--
0.5
--
0.5
--
0.5
--
ns
Data Hold to Clock High
t DH
0.5
--
0.5
--
0.5
--
0.5
--
ns
Write Hold to Clock High
t WH
0.5
--
0.5
--
0.5
--
0.5
--
ns
Address Advance to Clock High
tADVH
0.5
--
0.5
--
0.5
--
0.5
--
ns
Chip Select Hold to Clock High
tCSH
0.5
--
0.5
--
0.5
--
0.5
--
ns
Address Hold to Clock high
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is
sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE High with ADV Low.
Both cases must meet setup and hold times.
AC TEST CONDITIONS
TA = 0°C TO +70°C, VDD = 3.3V ± 5%; COMMERCIAL OR TA = -40°C TO +85°C, VDD = 3.3V ± 5%; INDUSTRIAL
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
OUTPUT LOAD (A)
Value
0 to 3.0V
1.0V/ns
1.5V
See Output Load (A)
OUTPUT LOAD (B)
(FOR tLZC, tLZOE, tHZOE, AND tHZC)
+3.3V
Dout
RL=50Ω
VL=1.5V
Zo=50Ω
3.9 Ω
Dout
30pF*
353 Ω
5pF*
*Including Scope and Jig Capacitance
5
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WED2ZL361MV
White Electronic Designs
SNOOZE MODE
When ZZ becomes a logic HIGH, ISB2Z is guaranteed
after the setup time tZZ is met. Any READ or WRITE
operation pending when the device enters SNOOZE
MODE is not guaranteed to complete successfully.
Therefore, SNOOZE MODE must not be initiated until
valid pending operations are completed.
SNOOZE MODE is a low-current, “power-down” mode
in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the
device enters SNOOZE MODE, all inputs except ZZ
become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to
enter SNOOZE MODE.
SNOOZE MODE
Description
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
Conditions
ZZ ³ V IH
Symbol
ISB2Z
tZZ
tRZZ
tZZI
tRZZI
Min
Max
10
2(t KC )
2(t KC )
2(t KC )
Units
mA
ns
ns
ns
ns
FIG. 2 SNOOZE MODE TIMING DIAGRAM
CLOCK
t ZZ
t RZZ
ZZ
t ZZI
ISUPPLY
t RZZI
I ISB2Z
ALL INPUTS
(except ZZ)
Output (Q)
DESELECT or READ Only
HIGH-Z
DON’T CARE
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Notes
1
1
1
1
WED2ZL361MV
White Electronic Designs
FIG. 3 TIMING WAVEFORM OF READ CYCLE
tCH
tCL
Clock
tAS
tAH
A1
Address
A2
tWS
tWH
tCSS
tCSH
tADVS
tADVH
A3
WRITE
CEx
ADV
OE
tOE
tHZOE
tLZOE
Q1-1
Data Out
NOTES:
tCD
tOH
Q2-1
tHZC
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
Don’t Care
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
Undefined
7
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WED2ZL361MV
White Electronic Designs
FIG. 4 TIMING WAVEFORM OF WRITE CYCLE
tCH
tCL
Clock
Address
A2
A1
A3
WRITE
CEx
ADV
OE
tDS
Data In
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
tDH
D3-2
D3-3
D3-4
tHZOE
Data Out
Q0-3
NOTES:
Q0-4
Don’t Care
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
White Electronic Designs Corporation • Westborough MA • (508) 366-5151
Undefined
8
WED2ZL361MV
White Electronic Designs
FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE
tCH
tCL
Clock
Address
A1
A2
A3
A4
Q1
Q3
A5
A6
A8
A7
A9
WRITE
CEx
ADV
OE
tOE
tLZOE
Data Out
Q6
Q7
tDH
tDS
Data In
Q4
D2
D5
Don’t Care
NOTES:
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
Undefined
9
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WED2ZL361MV
White Electronic Designs
FIG. 6 TIMING WAVEFORM OF CKE OPERATION
tCL
tCH
Clock
tCES tCEH
tCYC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CEx
ADV
OE
tCD
tLZC
Data Out
tHZC
Q1
Q3
tDH
tDS
Data In
Q4
D2
NOTES:
Don’t Care
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
White Electronic Designs Corporation • Westborough MA • (508) 366-5151
Undefined
10
WED2ZL361MV
White Electronic Designs
FIG. 7
TIMING WAVEFORM OF CE OPERATION
tCH
tCL
Clock
tCYC
Address
A1
A2
A3
A4
A5
WRITE
CEx
ADV
OE
tHZC
tOE
tLZOE
Data Out
Q1
tCD
tLZC
Q2
Q4
tDS tDH
Data In
D3
NOTES:
D5
Don’t Care
WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
Undefined
11
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WED2ZL361MV
White Electronic Designs
PACKAGE DIMENSION: 119 BUMP PBGA
1.90 (0.075)
MAX
7.62 (0.300)
TYP
17.00 (0.669) TYP
A
A1
CORNER
B
C
D
E
F
1.27 (0.050)
TYP
G
H
20.32 (0.800)
TYP
23.00 (0.905)
TYP
J
K
L
M
N
P
R
T
U
0.711 (0.028)
MAX
1.27 (0.050) TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined.
ORDERING INFORMATION
COMMERCIAL TEMP RANGE (0°C TO 70°C)
Part Number
WED2ZL361MV35BC
WED2ZL361MV38BC
WED2ZL361MV42BC
WED2ZL361MV50BC
Configuration
1M
1M
1M
1M
x
x
x
x
36
36
36
36
tCD
(ns)
3.5
3.8
4.2
5.0
Clock
(MHz)
166
150
133
100
INDUSTRIAL TEMP RANGE (-40°C TO +85°C)
Part Number
WED2ZL361MV35BCI
WED2ZL361MV38BCI
WED2ZL361MV42BCI
WED2ZL361MV50BCI
Configuration
1M
1M
1M
1M
x
x
x
x
36
36
36
36
tCD
(ns)
3.5
3.8
4.2
5.0
Clock
(MHz)
166
150
133
100
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