WED2ZLRSP01S 512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM FEATURES n n n n n n n DESCRIPTION Fast clock speed: 166, 150, 133, and 100MHz The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the first organized as a 512K x 32, and the second a 256K x 32. Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +2.5V ± 5% power supply (VDD) Snooze Mode for reduced-standby power All Synchronous inputs pass through registers controlled by a positive edge triggered, single clock input per array. The NBL or No Bus Latency Memory provides 100% bus utilizaton, with no loss of cycles caused by change in modal operation (Write to Read/Read to Write). All inputs except for Asynchronous Output Enable and Burst Mode control are synchronized on the positive or rising edge of Clock. Burst order control must be tied either HIGH or LOW, Write cycles are internally self-timed, and writes are initiated on the rising edge of clock. This feature eliminates the need for complex off-chip write pulse generation and proved increased timing flexibility for incoming signals. Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals n Burst control (interleaved or linear burst) n Packaging: • 209-bump BGA package n Low capacitive bus loading FIG. 1 PIN CONFIGURATION (TOP VIEW) A B C D E F G H J K L M N P R T U V W April 2002 Rev. 0 ECO #15203 1 VSS NC A_ADR A_ADR A_ADR A_ADR A_ADR NC VSS VSS VSS NC B_ADR B_ADR B_ADR B_ADR B_ADR NC VSS 2 A_DATB 0 A_DATB 4 A_ADR VSS A_CLK VSS A_ADR A_DAT C 0 A_DAT C 4 VSS B_DATB 0 B_DATB 4 B_ADR VSS B_CLK VSS NC B_DATC 4 B_DATC 0 3 A_DAT B 1 A_DAT B 5 A_OE A_CKE A_GWE A_CS 2 A_CS 1 A_DAT C1 A_DAT C5 V SS B_DATB 1 B_DATB 5 B_OE B_CKE B_GWE B_CS 2 B_CS 1 B_DAT C 5 B_DAT C 1 4 A_DAT B 2 A_DAT B 6 A_ADV V CC V CC V CC A_CS 2 A_DAT C2 A_DAT C6 V SS B_DATB 2 B_DATB 6 B_ADV V CC V CC V CC B_CS 2 B_DAT C 6 B_DAT C 2 5 A_DAT B 3 A_DAT B 7 A_BWE B V CC V CC V CC A_BWE C A_DAT C3 A_DAT C7 V SS B_DAT3 B_DAT7 B_BWE B V CC V CC V CC B_BWEc B_DAT C 7 B_DAT C 3 1 6 VSS VSS VSS V CC V CC V CC VSS VSS VSS VSS VSS VSS VSS V CC V CC V CC VSS VSS VSS 7 A_DAT A0 A_DAT A4 A_BWE A V CC V CC V CC A_BWE D A_DATD 0 A_DATD 4 VSS B_DAT A 0 B_DAT A 4 B_BWE A V CC V CC V CC B_BWED B_DATD4 B_DATD0 8 A_DAT A1 A_DAT A5 A_ZZ V CC V CC V CC A_LBO A_DATD 1 A_DATD 5 VSS B_DAT A 1 B_DAT A 5 B_ZZ V CC V CC V CC B_LBO B_DATD5 B_DATD1 9 A_DAT A 2 A_DAT A 6 A_ADR V CC V CC V CC A_ADR A_DATD 2 A_DATD 6 VSS B_DATA 2 B_DATA 6 B_ADR V CC V CC V CC B_ADR B_DATD6 B_DATD2 10 A_DAT A 3 A_DAT A 7 A_ADR A_ADR A_ADR 1 A_ADR A_ADR A_DATD 3 A_DATD 7 VSS B_DATA 3 B_DATA 7 B_ADR B_ADR B_ADR1 B_ADR B_ADR B_DATD7 B_DATD3 11 V SS NC A_ADR A_ADR A_ADR0 A_ADR A_ADR NC V SS V SS V SS NC B_ADR B_ADR B_ADR 0 B_ADR B_ADR NC V SS White Electronic Designs Corporation • (502) 366-5151• www.whiteedc.com WED2ZLRSP01S FIG. 1 PIN CONFIGURATION, CONT. B LOCK D IAGRAM White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 2 WED2ZLRSP01S FUNCTION DESCRIPTION The WWED2ZLRSP01S is an NBL Dual Array SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges, and all features are available on each of the independent arrays. Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-lined NBL SSRAM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. Clock Enable (CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL SSRAM latches external address and initiates a cycle when CKE and ADV are driven low at the rising edge of the clock. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates after 2 cycles of wake up time. Output Enable (OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, the write enable input signals WE are driven high, and ADV driven low. The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE must be driven low for the device to drive out the requested data. BURST SEQUENCE TABLE (Linear Burst, LBO = Low) (Interleaved Burst, LBO = High) Case 1 LBO Pin High First Address Fourth Address Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 Case 1 LBO Pin High First Address Fourth Address Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed. 3 White Electronic Designs Corporation • (502) 366-5151• www.whiteedc.com WED2ZLRSP01S TRUTH TABLES S YNCH RONOUS T RUTH T ABLE CE X ADV WE BW X OE CKE CLK Address Accessed Operation H X L X L X L X L X X L H L H L H L H L H X X X H X H X L X L X X X X X X X X L L H H X X X L L H H X X X X X L L L L L L L L L L H N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address Deselect Continue Deselect Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock NOTES: 1. X means “Don’t Care.” 2. The rising edge of clock is symbolized by () 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins (ZZ and OE). 6. CEx refers to the combination of CE1, CE2 and CE2. 7. Applies to each of the independent arrays. WRITE T RUTH T ABLE WE BWa BWb BWc BWd Operation H L L L L L L X L H H H L H X H L H H L H X H H L H L H X H H H L L H Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP NOTES: 1. X means “Don’t Care.” 2. All inputs in this table must meet setup and hold time around the rising edge of CLK (). 3. Applies to each of the independent arrays. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 4 WED2ZLRSP01S ABSOLUTE M AXIMUM R ATINGS * Voltage on VDD Supply Relative to VSS -0.3V to +3.6V VIN (DQx) -0.3V to +3.6V VIN (Inputs) -0.3V to +3.6V Storage Temperature (BGA) -55°C to +125°C Short Circuit Output Current 100mA *Stress greater than those listed under “Absolute Maximum Ratings”: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. E LECTRICAL C HARACTERISTICS (0°C Description Symbol Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage V IH V IL I LI ILO VOH VOL VDD £ TA £ 70°C) Conditions 0V £ VIN £ VDD Output(s) Disabled, 0V £ VIN £ VDD IOH = -1.0mA IOL = 1.0mA Min Max Units Notes 1.7 -0.3 -5 -5 2.0 --2.375 VDD +0.3 0.7 5 5 --0.4 2.625 V V µA µA V V V 1 1 2 1 1 1 NOTES: 1. All voltages referenced to VSS (GND) 2. ZZ pin has an internal pull-up, and input leakage is higher. DC C HARACTERISTICS Description Power Supply Current: Operating Power Supply Current: Standby Symbol IDD ISB2 Power Supply Current: Current ISB3 Clock Running Standby Current ISB4 Conditions 166 150 133 100 MHz MHz MHz MHz Units Notes 650 600 560 500 mA 1, 2 30 60 60 60 60 mA 2 20 40 40 40 40 mA 2 140 120 100 80 mA 2 Typ Device Selected; All Inputs £ VIL or ³ VIH; Cycle Time = tCYC MIN; VDD = MAX; Output Open Device Deselected; VDD = MAX; All Inputs £ VSS + 0.2 or VDD - 0.2; All Inputs Static; CLK Frequency = 0; ZZ £ VIL Device Selected; All Inputs £ VIL or ³ VIH; Cycle Time =tCYC MIN; VDD = MAX; Output Open; ZZ ³ VDD - 0.2V Device Deselected; VDD = MAX; All Inputs £ VSS + 0.2 or VDD - 0.2; Cycle Time = tCYC MIN; ZZ £ VIL NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time. BGA C APACITANCE Description Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance Symbol Conditions Typ Max Units Notes CI CO CA CCK TA = 25°C; f = 1MHz TA= 25°C; f = 1MHz TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz 5 6 5 3 7 8 7 5 pF pF pF pF 1 1 1 1 NOTES: 1. This parameter is sampled. 5 White Electronic Designs Corporation • (502) 366-5151• www.whiteedc.com WED2ZLRSP01S AC C HARACTERISTICS Symbol Parameter 166MHz Min Clock Time Clock Access Time Output enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE Setup to Clock High Data Setup to Clock High Write Setup to Clock High Address Advance to Clock High Chip Select Setup to Clock High Address Hold to Clock high CKE Hold to Clock High Data Hold to Clock High Write Hold to Clock High Address Advance to Clock High Chip Select Hold to Clock High t CYC tCD tOE t LZC t OH t LZOE t HZOE t HZC tCH tCL tAS tCES tDS tWS tADVS tCSS t AH tCEH tDH t WH tADVH tCSH 6.0 — — 1.5 1.5 0.0 — — 2.2 2.2 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 3.5 3.5 — — — 3.0 3.0 — — — — — — — — — — — — 150MHz Min 133MHz Max 6.7 — — 1.5 1.5 0.0 — — 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 3.8 3.8 — — — 3.0 3.0 — — — — — — — — — — — — Min 7.5 — — 1.5 1.5 0.0 — — 3.0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 4.2 4.2 — — — 3.5 3.5 — — — — — — — — — — — — 100MHz Min 10.0 — — 1.5 1.5 0.0 — — 3.0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 5.0 5.0 — — — 3.5 3.5 — — — — — — — — — — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edgeswhen ADV is sampled low and CEx is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE High with ADV Low. Both cases must meet setup and hold times. 4. Applies to each of the independent arrays. AC T EST C ONDITIONS (T A = 0 TO 70°C, V DD = 2.5V ± 5%, UNLESS O THERWISE S PECIFIED ) Parameter Value Input Pulse Level Input Rise and Fall Time (Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load 0 to 2.5V 1.0V/ns 1.25V See Output Load (A) O UTPUT L OAD (B) O UTPUT L OAD (A) ( FOR tLZC , t LZOE , t HZOE , *Including Scope and Jig Capacitance White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 6 AND t HZC ) WED2ZLRSP01S SNOOZE MODE When ZZ becomes a logic HIGH, ISB 2Z is guaranteed after the setup time t ZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. S NOOZE MODE Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current FIG. 2 Conditions Symbol ZZ ³ VIH I SB 2Z tZZ t RZZ tZZI t RZZI Min Max Units Notes 10 2(t KC ) mA ns ns ns ns 1 1 1 1 2(t KC ) 2(t KC ) SNOOZE MODE TIMING DIAGRAM 7 White Electronic Designs Corporation • (502) 366-5151• www.whiteedc.com WED2ZLRSP01S FIG. 3 TIMING WAVEFORM OF READ CYCLE Note: Applies to both independent arrays. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 8 WED2ZLRSP01S FIG. 4 TIMING WAVEFORM OF WRITE CYCLE Note: Applies to both independent arrays. 9 White Electronic Designs Corporation • (502) 366-5151• www.whiteedc.com WED2ZLRSP01S FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE Note: Applies to both independent arrays. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 10 WED2ZLRSP01S FIG. 6 TIMING WAVEFORM OF CKE OPERATION Note: Applies to both independent arrays. 11 White Electronic Designs Corporation • (502) 366-5151• www.whiteedc.com WED2ZLRSP01S FIG. 7 TIMING WAVEFORM OF CE OPERATION Note: Applies to both independent arrays. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 12 WED2ZLRSP01S PACKAGE DIMENSION: 119 BUMP PBGA ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION C OMMERCIAL T EMP R ANGE (0°C Part Number WED2ZLRSP01S35BC WED2ZLRSP01S38BC WED2ZLRSP01S42BC WED2ZLRSP01S50BC WED2ZLRSP01S38BI WED2ZLRSP01S42BI WED2ZLRSP01S50BI Configuration 512K 512K 512K 512K 512K 512K 512K x x x x x x x 32/256K 32/256K 32/256K 32/256K 32/256K 32/256K 32/256K x x x x x x x 32 32 32 32 32 32 32 TO 70°C) t CD Clock Operating (ns) (MHz) Range Range 3.5 3.8 4.2 5.0 3.8 4.2 5.0 166 150 133 100 150 133 100 Commercial Commercial Commercial Commercial Industrial Industrial Industrial 0° - 70° C 0° - 70°C 0° - 70°C 0° - 70°C -40° - 85°C -40° - 85°C -40° - 85°C 13 Temperature White Electronic Designs Corporation • (502) 366-5151• www.whiteedc.com