WEDPZ512K72S-XBX 512K x 72 Synchronous Pipeline Burst ZBL SRAM *PRELIMINARY FEATURES DESCRIPTION ! Fast clock speed: 150, 133, and 100MHz The WEDC SyncBurst - SRAM employs high-speed, lowpower CMOS design that is fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 512K x 36 SSRAMs into a single BGA package to provide 512K x 72 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The ZBL or Zero Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied “High or Low.” Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. ! Fast access times: 3.8ns, 4.2ns, and 5.0ns ! Fast OE access times: 3.8ns, 4.2ns, and 5.0ns ! High performance 3-1-1-1 access rate ! 2.5V ± 5% power supply ! Common data inputs and data outputs ! Byte write enable and global write control ! Six chip enables for depth expansion and address pipeline ! Internally self-timed write cycle ! Burst control pin (interleaved or linear burst sequence) ! Automatic power-down for portable applications ! Commercial, industrial and military temperature ranges ! Packaging: *Preliminary product that is not fully characterized, non-qualified and is subject to change without notice. •152 PBGA package 17 x 23mm FUNCTIONAL BLOCK DIAGRAM BENEFITS 512K x 36 SSRAM ! 30% space savings compared to equivalent TQFP solution ! Reduced part count ! 24% I/O reduction ! Laminate interposer for optimum TCE match ! Low Profile ! Reduce layer count for board routing ! Suitable for hi-reliability applications A0-18 SA BWa BWa BWb BWb BWc BWc DQPA DQPA BWd BWd DQA0-7 DQA0-7 WE0 WE0 DQPB DQPB OE0 OE0 DQB0-7 DQB0-7 CLK0 CLK DQPC DQPC CKE0 CKE DQC0-7 DQC0-7 CS10 CS1 DQPD DQPD CS20 CS2 DQD0-7 DQD0-7 CS20 CS2 ADV0 ADV LBO LBO ZZ ! User configurable as 1M x 36 or 2M x 18 ZZ 512K x 36 SSRAM ! Upgradable to 1M x 72 (contact factory for availability) SA BWe BWa BWf BWb BWg BWc DQPA DQPE BWh BWd DQA0-7 DQE0-7 WE1 WEO DQPB DQPF OE1 OEO DQB0-7 DQF0-7 CLK1 CLK DQPC DQPG CKE1 CKE DQC0-7 DQG0-7 CS11 CS1 DQPH DQPH CS21 CS2 DQD0-7 DQH0-7 CS21 CS2 ADV1 ADV LBO ZZ November 2003 Rev. 6 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPZ512K72S-XBX PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 A - ADV0 OE 0 DQB2 DQB4 DQB6 DNU DQA 6 DQA 2 B CKE0 WE0 DQB7 DQB5 DQB3 DQB0 DQA 7 DQA 3 DQA 1 C CLK0 CS20 DQC 2 DQPC DQPB DQB1 DQD 7 DQA 4 DQA 0 D BWa BWb DQC 3 VSS VSS VSS DQD 6 DQA 5 DQPA E BWc BWd DQC 4 VDDQ VDDQ VDDQ DQD 5 DQPD ZZ F CS10 CS20 DQC 5 VDDQ VDDQ VSS DQD 4 DNU* A0 G A7 DQC 0 DQC 7 VSS VDD VDD DQD 3 A1 A3 H A18 DQC 1 DQC 6 VDD VDD V DD ` DQD 2 A2 A5 J A9 A6 DQF 2 VSS VSS VSS DQD 1 A4 A16 K A8 DQF 4 FQF3 VDD VDD VDD DQD 0 A14 A15 L A17 DQF 5 DQF 6 VDD VDD VSS DQE 6 A12 A13 M ADV1 OE 1 DQF 7 VSS VDDQ VDDQ DQE 7 A10 A11 N CKE1 WE1 DQPF VDDQ VDDQ VDDQ DQE 5 DQE 3 LBO P CLK1 CS21 DQF 1 VSS VSS VSS DQE 4 DQE 2 DQE 0 R BWe BWf DQF 0 DQG 1 DQG 4 DQH 1 DQH 2 DQE 1 DQPE T BWg BWh DQG 0 DQG 2 DQG 5 DQH 0 DQH 4 DQH 7 DQPH U CS11 CS21 DQG 3 DQPG DQG 6 DQG 7 DQH 3 DQH 5 DQH 6 NOTE: DNU means Do Not Use and are reserved for future use. * Pin F8 reserved for A19 upgrade to 1M x 72. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 2 WEDPZ512K72S-XBX FUNCTION DESCRIPTION The WEDPZ512K72S-XBX is an ZBL SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. Write operation occurs when WE is driven low at the rising edge of the clock. BW[h:a] can be used for byte write operation. The pipe-lined ZBL SSRAM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycles later. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. Clock Enable (CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL SSRAM latches external address and initiates a cycle when CKE and ADV are driven low at the rising edge of the clock. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after two cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates after two cycles of wake up time. Output Enable (OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, the write enable input signals WE are driven high, and ADV driven low. The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE must be driven low for the device to drive out the requested data. BURST SEQUENCE TABLE (Interleaved Burst, LBO = High) Case 1 LBO Pin High A1 First Address Fourth Address Case 2 A0 A1 Case 3 A0 A1 (Linear Burst, LBO = Low) Case 4 A0 A1 Case 1 A0 0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 0 0 LBO Pin High A1 First Address Case 2 A0 A1 A0 Case 3 Case 4 A1 A0 A1 A0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 Fourth Address NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed. 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPZ512K72S-XBX TRUTH TABLES SYNCHRONOUS TRUTH TABLE CEx ADV WE BWx OE CKE H L X X X L CLK Address Accessed ↑ N/A Operation Deselect X H X X X L ↑ N/A Continue Deselect L L H X L L ↑ External Address Begin Burst Read Cycle X H X X L L ↑ Next Address Continue Burst Read Cycle L L H X H L ↑ External Address NOP/Dummy Read X H X X H L ↑ Next Address Dummy Read L L L L X L ↑ External Address Begin Burst Write Cycle X H X L X L ↑ Next Address Continue Burst Write Cycle L L L H X L ↑ N/A NOP/Write Abort X H X H X L ↑ Next Address Write Abort X X X X X H ↑ Current Address Ignore Clock NOTES: 1. X means “Don’t Care.” 2. The rising edge of clock is symbolized by ( ↑ ). 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins (ZZ and OE). 6. CEx refers to the combination of CS 1, CS 2 and CS 2. WRITE TRUTH TABLE WE BWa BWb BWc BWd Operation H X X X X Read L L H H H Write Byte a L H L H H Write Byte b L H H L H Write Byte c L H H H L Write Byte d L L L L L Write All Bytes L H H H H Write Abort/NOP NOTES: 1. X means “Don’t Care.” 2. All inputs in this table must meet setup and hold time around the rising edge of CLK (↑ ). 3. Replace BW A with BW E , BW B , with BW F , BW C with BW G and BW D with BW H for operation of IC 2 . White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 4 WEDPZ512K72S-XBX ABSOLUTE MAXIMUM RATINGS* VIN Voltage or any other pin relative to V SS Voltage on V DD supply relative to VSS Storage temperature (BGA) -0.3V to +3.6V -0.3V to +3.6V -55°C to +150°C *Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS (-55°C - TA - +125°C) Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage I/O Power Suply Symbol Conditions V IH VIL I IL VDD = Max, 0V - VIN - VDD I LO Output(s) Disabled, VOUT = VSS to VDDQ V OH IOH = -1.0mA V OL IOL = 1.0mA VDD V DDQ Min 1.7 -0.3 -4 -2 2.0 --2.375 2.375 Max VDD +0.3 0.7 +4 +2 --0.4 2.625 2.625 Units V V µA µA V V V V Notes 1 1 2 1 1 1 1 NOTES: 1. All voltages referenced to V SS (GND) 2. ZZ pin has an internal pull-up, and input leakage = ± 20 µA. DC CHARACTERISTICS (-55°C - TA - + 125°C) Description Power Supply Current: Operating Power Supply Current: Standby Clock Running Standby Current Symbol Conditions IDD ISB2 ISB Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle Time ≥ TCYC MIN; VDD = MAX; Output Open Device Deselected; VDD = MAX; All Inputs ≤ VIL or ≥ VIH All Inputs Static; CLK Frequency = MAX Output Open, ZZ ≥ VDD - 0.2V Device Deselected; VDD = MAX; All Inputs ≤ VSS + 0.2 or VDD - 0.2; f = max ; ZZ ≤ VIL 150 133 100 MHz MHz MHz Units Notes (Max) (Max) (Max) 700 650 600 mA 1 120 120 120 mA 180 180 160 mA NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. BGA CAPACITANCE THERMAL RESISTANCE (TA = + 25°C, f = 1MHZ) Description Symbol Max Units Notes Control Input Capacitance (LBO, zz) CIC 16 pF 1 Control Input Capacitance CI 8 pF 1 Input/Output Capacitance (DQ) CO 10 pF 1 Address Capacitance CA 16 pF 1 Clock Capacitance CCK 6 pF 1 Parameter Symbol Max Unit Thermal Resistance: Die Junction to Ambient θJA 28.7 °C/W Thermal Resistance: Die Junction to Ball θJB 16.0 °C/W Thermal Resistance: Die Junction to Case θJC 7.1 °C/W Note: Refer to Application Note “PBGA Thermal Resistance Corrleation” for further information regarding WEDC’s thermal modeling. NOTES: 1. This parameter is not tested but guaranteed by design. 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPZ512K72S-XBX AC CHARACTERISTICS (-55°C - TA - +125°C) Symbol 150MHz Min Max 133MHz Min Max 100MHz Min Max tCYC 6.7 7.5 10.0 t CD -- 3.8 Parameter Clock Time Clock Access Time -- 4.2 Units ns -- 5.0 ns Output enable to Data Valid t OE -- 3.8 -- 4.2 -- 5.0 ns Clock High to Output Low-Z tLZC 1.5 -- 1.5 -- 1.5 -- ns Output Hold from Clock High tOH 1.5 -- 1.5 -- 1.5 -- ns Output Enable Low to output Low-Z t LZOE 0.0 -- 0.0 -- 0.0 -- ns Output Enable High to Output High-Z Clock High to Output High-Z t HZOE t HZC --- 3.0 3.0 --- 3.5 3.5 --- 3.5 3.5 ns ns Clock High Pulse Width t CH 2.5 -- 2.5 -- 3.0 -- ns Clock Low Pulse Width t CL 2.5 -- 2.5 -- 3.0 -- ns Address Setup to Clock High t AS 1.5 -- 1.5 -- 1.5 -- ns CKE Setup to Clock High tCES 1.5 -- 1.5 -- 1.5 -- ns Data Setup to Clock High tDS 1.5 -- 1.5 -- 1.5 -- ns Write Setup to Clock High tWS 1.5 -- 1.5 -- 1.5 -- ns Address Advance to Clock High tADVS 1.5 1.5 1.5 Chip Select Setup to Clock High tCSS 1.5 1.5 1.5 tAH 0.5 -- 0.5 -- 0.5 -- ns CKE Hold to Clock High tCEH 0.5 -- 0.5 -- 0.5 -- ns Data Hold to Clock High Write Hold to Clock High t DH tWH 0.5 0.5 --- 0.5 0.5 --- 0.5 0.5 --- ns ns Address Advance to Clock High t ADVH 0.5 -- 0.5 -- 0.5 -- ns Chip Select Hold to Clock High tCSH 0.5 -- 0.5 --- 0.5 -- ns Address Hold to Clock high ns ns NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CSx is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE High with ADV Low. Both cases must meet setup and hold times. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load OUTPUT LOAD (A) Value 0 to 2.5V 1.0V/ns 1.25V See Output Load (A & B) OUTPUT LOAD (B) (FOR TLZC, TLZOE, THZOE, AND THZC) Dout +2.5V RL=50Ω VL=1.25V Zo=50Ω 1667Ω Dout 50pF* 1538Ω *Including Scope and Jig Capacitance White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6 5pF* WEDPZ512K72S-XBX SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current FIG. 2 Conditions ZZ ≥ V IH Symbol I SB2Z tzz trzz t ZZI t RZZI Min Max 20 2 2 2 O Units mA cycle cycle cycle ns SNOOZE MODE TIMING DIAGRAM CLOCK t ZZ t RZZ ZZ t ZZI ISUPPLY ALL INPUTS (except ZZ) t RZZI I ISB2Z DESELECT or READ Only Deselect or Read Only Normal Operation Cycle Output (Q) HIGH-Z DON'T CARE 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPZ512K72S-XBX FIG. 3 TIMING WAVEFORM OF READ CYCLE tCH tCL CLKx tCYC tCES tCEH CKEx tAS tAH A1 Address A2 tWS tWH tCSS tCSH tADVS tADVH A3 WRITE CSx ADVx OE tOE tHZOE tLZOE Q1-1 Data Out NOTES: tCD tOH Q2-1 tHZC Q2-2 Q2-3 WRITE = L means WEx = L, and BWx = L CSx refers to the combination of CS10, CS20 and CS20, or CS11, CS21 and CS21. Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don¢t Care Undefined White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 8 WEDPZ512K72S-XBX FIG. 4 TIMING WAVEFORM OF WRITE CYCLE tCH tCL CLKx tCYC tCES tCEH CKEx Address A2 A1 A3 WRITE CSx ADVx OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tHZOE Data Out Q0-3 Q0-4 Don¢t Care NOTES: WRITE = L means WEx = L, and BWx = L CSx refers to the combination of CS10, CS20 and CS20, or CS11, CS21 and CS21. 9 Undefined White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPZ512K72S-XBX FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE tCH tCL CLKx tCYC tCES tCEH CKEx Address A1 A2 A3 A4 Q1 Q3 A5 A6 A8 A7 A9 WRITE CSx ADVx OE tOE tLZOE Data Out D2 NOTES: Q6 Q7 tDH tDS Data In Q4 D5 WRITE = L means WEx = L, and BWx = L CSx refers to the combination of CS10, CS20 and CS20, or CS11, CS21 and CS21. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 10 Don¢t Care Undefined WEDPZ512K72S-XBX FIG. 6 TIMING WAVEFORM OF CKE OPERATION tCL tCH CLKx tCES tCEH tCYC CKEx Address A1 A2 A3 A4 A5 A6 WRITE CSx ADVx OE tCD tLZC Data Out tHZC Q1 Q3 tDH tDS Data In Q4 D2 NOTES: WRITE = L means WE = L, and BWx = L CSx refers to the combination of CS10, CS20 and CS20, or CS11, CS21 and CS21. 11 Don¢t Care Undefined White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPZ512K72S-XBX FIG. 7 TIMING WAVEFORM OF CE OPERATION tCH tCL CLKX tCYC tCEH tCES CKEX Address A1 A2 A3 A4 A5 WRITE CSX ADVX OE tHZC tOE tLZOE Data Out Q1 tCD tLZC Q2 Q4 tDS tDH Data In D3 NOTES: WRITE = L means WE = L, and BWx = L CSx refers to the combination of CS10, CS20 and CS20, or CS11, and CS21. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 12 D5 Don¢t Care Undefined WEDPZ512K72S-XBX PACKAGE DIMENSION: 152 BUMP PBGA BOTTOM VIEW 9 8 7 6 5 4 3 2 ∅ 0.762 (0.030) NOM 1 A B C D E F G 23.1 (0.909) MAX 20.32 (0.800) NOM 1.27 (0.050) NOM H J K L M N P R T U 1.27 (0.050) NOM 0.61 (0.024) NOM 10.16 (0.400) NOM 2.03 (0.080) MAX 17.1 (0.673) MAX ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION WED P Z 512K 72 S - XXX B X DEVICE GRADE: M = Military -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE: B = 152 Plastic Ball Grid Array (PBGA) FREQUENCY (MHz) 100 = 100MHz 133 = 133MHz 150 = 150MHz 2.5 V Voltage CONFIGURATION, 512K x 72 SSRAM ZBL PLASTIC WHITE ELECTRONIC DESIGNS CORP. 13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPZ512K72S-XBX Document Title 512K x 72 Synchronous SRAM – NBL Revision History Rev # History Release Date Status Rev 0 Initial Release February 2001 Advanced Rev 1 Changes (Pg. 1, 5, 6, 13) April 2001 Advanced 1.1 Block Diagram: Change DQD to DQPD, Font Consistency 1.2 Electrical Characteristics Note 2: Change reference to mA instead of MA. 1.3 DC Characteristics: Adjust location of Units & Notes for ISB2. 1.4 AC Characteristics: Change temperature range to (-55°C ≤ TA ≤ +125°C) 1.5 Package Dimension: Adjust length line to end of package 1.6 Block Diagram: Adjust look for consistency 1.7 DC Characteristics: ISB2 condition should read All Inputs ≤ VIL or ≥ VIH instead of > VIH 1.8 Figure 2: Inputs transition should not be shown fully connected. 1.9 Figure 6: Unknown text deleted from timing diagram 1.10 Package Dimension: Ball diameter arrow corrected to point to ball. Rev 2 Change (Pg. 1) November 2001 Preliminary November 2001 Preliminary 1.1 Change status from Advanced to Preliminary Rev 3 Changes (Pg. 1, 2) 1.1 Block Diagram: Address lines should be A0-18 1.2 Pin Configuration: Add Note *Pin F8 reserved for A19 upgrade to 1Mx72. Rev 4 Changes (Pg. 1, 5) November 2002 Preliminary 1.1 BGA Capacitance: Remove references to temperature in individual conditions 1.2 Change CI from 10pF to 8pF 1.3 Change CA from 20pF to 16pF 1.4 Change CCK from 7pF to 6pF 1.5 Add Control Input Capacitance (CIC) 16pF Rev 5 Changes (Pg. 5) May 2003 Preliminary November 2003 Preliminary 1.1 Add Thermal Resistance table 1.2 Update current values 1.3 Update package mechanical drawing Rev 6 Changes (Pg. 1, 13, 14, 15) 1.1 Change mechanical drawing to new style White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 14