WED2ZL361MS White Electronic Designs 1Mx36 Synchronous Pipeline Burst NBL SRAM FEATURES Fast clock speed: 250, 225, 200, 166, 150, 133MHz Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Separate +2.5V ± 5% power supplies for Core, I/O (VCC, VCCQ) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging: DESCRIPTION The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 configuration. All synchronous inputs pass through registers controlled by a positiveedge-triggered single-clock input (CK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied “High or Low.” Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. 119-bump BGA package Low capacitive bus loading NOTE: NBL (No Bus Latency) is equivalent to ZBT™ PIN CONFIGURATION BLOCK DIAGRAM 2 SA 3 SA 4 SA 5 SA 6 SA 7 VCCQ B SA CE2 SA ADV# SA CE2# NC C NC SA SA VCC SA SA NC D DQc DQPc VSS NC VSS DQPb DQb E DQc DQc VSS CE1# VSS DQb DQb F VCCQ DQc VSS OE# VSS DQb VCCQ G DQc DQc BWc# SA BWb# DQb DQb H DQc DQc VSS WE# VSS DQb DQb J VCCQ VCC NC VCC NC VCC VCCQ K DQd DQd VSS CK VSS DQa DQa L DQd M VCCQ N DQd DQd BWd# NC BWa# DQa DQa DQd VSS CKE# VSS DQa VCCQ DQd VSS SA1 VSS DQa DQa P DQd DQPd VSS SA0 VSS DQPa DQa R NC SA LBO# VCC NC SA NC T NC NC SA SA SA NC ZZ U VCCQ NC NC NC NC NC VCCQ BWa# BWb# 1 VCCQ A BWc# BWd# (TOP VIEW) 1M x 18 CK CKE# ADV# LBO# CE1# CE2 CE2# OE# WE# ZZ CK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ 1M x 18 CK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ Address Bus (SA0 - SA19) DQc, DQd DQPc, DQPd DQa, DQb DQPa, DQPb DQa - DQd DQPa - DQPd White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs FUNCTION DESCRIPTION The WED2ZL361MS is an NBL SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE#, LBO# and ZZ) are synchronized to rising clock edges. Write operation occurs when WE# is driven low at the rising edge of the clock. BW#[d:a] can be used for byte write operation. The pipe-lined NBL SSRAM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE# and address are registered, and the data associated with that address is required two cycle later. All read, write and deselect cycles are initiated by the ADV# input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV#). ADV# should be driven to Low once the device has been deselected in order to load a new address for next operation. Subsequent addresses are generated by ADV# High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO# pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. Clock Enable (CKE#) pin allows the operation of the chip to be suspended as long as necessary. When CKE# is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL SSRAM latches external address and initiates a cycle when CKE# and ADV# are driven low at the rising edge of the clock. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates after 2 cycles of wake up time. Output Enable (OE#) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE# is driven low, the write enable input signals WE# are driven high, and ADV# driven low. The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE# must be driven low for the device to drive out the requested data. BURST SEQUENCE TABLE (INTERLEAVED BURST, LBO# = HIGH) (LINEAR BURST, LBO# = LOW) LBO# Pin High First Address ↓ Fourth Address Case 1 Case 2 Case 3 Case 4 A1 0 0 1 1 A1 0 0 1 1 A1 1 1 0 0 A1 1 1 0 0 A0 0 1 0 1 A0 1 0 1 0 A0 0 1 0 1 LBO# Pin A0 1 0 1 0 High First Address ↓ Fourth Address Case 1 Case 2 Case 3 Case 4 A1 0 0 1 1 A1 0 1 1 0 A1 1 1 0 0 A1 1 0 0 1 A0 0 1 0 1 A0 1 0 1 0 A0 0 1 0 1 A0 1 0 1 0 NOTE 1: LBO# pin must be tied to High or Low, and Floating State must not be allowed. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs TRUTH TABLES SYNCHRONOUS TRUTH TABLE CEx# ADV H L X H L L X H L L X H L L X H L L X H X X WE# X X H X H X L X L X X BWx# X X X X X X L L H H X OE# X X L L H H X X X X X CKE# L L L L L L L L L L H CK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Address Accessed N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address Operation Deselect Continue Deselect Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock NOTES: 1. X means “Don’t Care.” 2. The rising edge of clock is symbolized by ( ↑ ) 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE# = L means Write operation in WRITE TRUTH TABLE. WRITE# = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins (ZZ and OE#). 6. CEx# refers to the combination of CE1#, CE2 and CE2#. WRITE TRUTH TABLE WE# H L L L L L L BWa# BWb# BWc# BWd# X X X X L H H H H L H H H H L H H H H L L L L L H H H H Operation Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP NOTES: 1. X means “Don’t Care.” 2. All inputs in this table must meet setup and hold time around the rising edge of CK ( ↑ ). White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Supply Relative to VSS -0.3V to +3.6V Vin (DQx) -0.3V to +3.6V Vin (Inputs) -0.3V to +3.6V Storage Temperature (BGA) -55°C to +125°C Short Circuit Output Current 100mA *Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (Voltage Referenced to: VSS = OV, TA = 0°C; Commercial or -40°C ≤ TA ≤ 85°C; Industrial) Min Max Units Notes Input High (Logic 1) Voltage Description Symbol VIH Conditions 1.7 VCC +0.3 V 1 Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1 Input Leakage Current ILI -5 5 µA 2 Output Leakage Current ILO -5 5 µA Output High Voltage VOH 2.0 – V 1 Output Low Voltage VOL – 0.4 V 1 Supply Voltage VCC 2.375 2.625 V 1 0V ≤ VIN ≤ VCC Output(s) Disabled, 0V ≤ VIN ≤ VCC IOH = -1.0mA IOL = 1.0mA NOTES: 1. All voltages referenced to VSS (GND) 2. ZZ pin has an internal pull-up, and input leakage is higher. DC CHARACTERISTICS Description Symbol Conditions IDD Device Selected; All Inputs � VIL or � VIH; Cycle Time = TCYC MIN; VCC = MAX; Output Open Power Supply Current: Standby ISB2 Device Deselected; VCC = MAX; All Inputs� VSS + 0.2 or VCC - 0.2; All Inputs Static; CK Frequency = 0; ZZ � VIL Power Supply Current: Current ISB3 Device Selected; All Inputs � VIL or � VIH; Cycle Time = TCYC MIN; VCC = MAX; Output Open; ZZ � VCC - 0.2V Clock Running Standby Current ISB4 Device Deselected; VCC = MAX; All Inputs � VSS + 0.2 or VCC - 0.2; Cycle Time = TCYC MIN; ZZ � VIL Power Supply Current: Operating 250 MHz 200 MHz 166 MHz 133 MHz Units Notes 900 800 690 580 mA 1, 2 30 60 60 60 60 mA 2 20 40 40 40 40 mA 2 150 140 130 100 mA 2 Typ NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time. BGA CAPACITANCE Description Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance Symbol CI CO CA CCK Conditions TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ Typ 5 6 5 3 Max 7 8 7 5 Units pF pF pF pF Notes 1 1 1 1 NOTES: 1. This parameter is sampled. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs AC CHARACTERISTICS Parameter Symbol 250MHz Min Max 225MHz Min Max 4.4 200MHz Min Max 5.0 166MHz Min 150MHz Max 6.0 Min 133MHz Max Min 6.7 Max 7.5 Units Clock Time tCYC 4.0 Clock Access Time tCD -- 2.6 -- 2.8 -- 3.0 -- 3.5 -- 3.8 -- 4.2 ns ns Output enable to Data Valid tOE -- 2.6 -- 2.8 -- 3.0 -- 3.5 -- 3.8 -- 4.2 ns Clock High to Output Low-Z tLZC 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Output Hold from Clock High tOH 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Output Enable Low to output Low-Z tLZOE 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- 0.0 -- ns Output Enable High to Output High-Z tHZOE -- 2.6 -- 2.8 -- 3.0 -- 3.0 -- 3.0 -- 3.5 ns Clock High to Output High-Z tHZC -- 2.6 -- 2.8 -- 3.0 -- 3.0 -- 3.0 -- 3.5 ns Clock High Pulse Width tCH 1.7 -- 2.0 -- 2.0 -- 2.2 -- 2.2 -- 2.2 -- ns Clock Low Pulse Width tCL 1.7 -- 2.0 -- 2.0 -- 2.2 -- 2.2 -- 2.2 -- ns Address Setup to Clock High tAS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns CKE Setup to Clock High tCES 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Data Setup to Clock High tDS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Write Setup to Clock High tWS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Address Advance to Clock High tADVS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Chip Select Setup to Clock High tCSS 1.2 -- 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Address Hold to Clock high tAH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns CKE Hold to Clock High tCEH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Data Hold to Clock High tDH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Write Hold to Clock High tWH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Address Advance to Clock High tADVH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Chip Select Hold to Clock High tCSH 0.3 -- 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns ZZ High to Power Down tPDS 2 -- 2 -- 2 -- 2 -- 2 -- 2 -- cycle ZZ Low to Power Up tPUS 2 -- 2 -- 2 -- 2 -- 2 -- 2 -- cycle NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled. 3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low. Both cases must meet setup and hold times. AC TEST CONDITIONS (0 ≤ TA ≤ 70°C, VCC = 2.5V ± 5%; Commercial or -40°C ≤ Ta ≤ 85°C; VCC = 2.5V ± 5%; Industrial) Parameter Value Input Pulse Level 0 to 2.5V Input Rise and Fall Time (Measured at 20% to 80%) 1.0V/ns Input and Output Timing Reference Levels 1.25V Output Load See Output Load (A) OUTPUT LOAD (A) Dout OUTPUT LOAD (B) (for tLZC, tLZOE, tHZOE, and tHZC) RL=50Ω VL=1.25V Zo=50Ω +2.5V 30pF* 1667Ω Dout 1538Ω 5pF* *Including Scope and Jig Capacitance White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs SNOOZE MODE When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. SNOOZE MODE Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current Conditions ZZ ≥ VIH Symbol ISB2Z tZZ tRZZ tZZI tRZZI Min Max 10 2(tKC) 2(tKC) 2(tKC) Units mA ns ns ns ns Notes 1 1 1 1 FIG 1 SNOOZE MODE TIMING DIAGRAM CLOCK t ZZ t RZZ ZZ t ZZI ISUPPLY t RZZI I ISB2Z ALL INPUTS (except ZZ) Output (Q) DESELECT or READ Only HIGH-Z DON'T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs FIG 2 TIMING WAVEFORM OF READ CYCLE tCH tCL Clock tCES tCYC tCEH CKE# tAH tAS A1 Address A2 tWS tWH tCSS tCSH tADVS tADVH A3 WRITE# CEx# ADV OE# tOE tLZOE Data Out NOTES: tHZOE Q1-1 tCD tOH Q2-1 tHZC Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Dont Care Undefined WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs FIG 3 TIMING WAVEFORM OF WRITE CYCLE tCH tCL Clock tCYC tCSS tCSH CKE# Address A3 A2 A1 WRITE# CEx# ADV OE# tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tHZOE Data Out Q0-3 NOTES: Q0-4 Dont Care Undefined WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs FIG. 4 TIMING WAVEFORM OF SINGLE READ/WRITE tCH tCL Clock tCYC tCES tCEH CKE# Address A1 A2 A3 A4 Q1 Q2 A5 A6 A7 A8 A9 WRITE# CEx# ADV OE# tOE tLZOE Data In D2 NOTES: Q6 Q7 tDH tDS Data Out Q4 D5 Dont Care Undefined WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs FIG. 5 TIMING WAVEFORM OF CKE# OPERATION tCH tCL Clock tCES tCEH tCYC CKE# Address A1 A3 A2 A5 A4 A6 WRITE# CEx# ADV OE# tCD tLZC Data Out tHZC Q1 Q3 tDS Data In Q4 tDH D2 NOTES: Dont Care Undefined WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs FIG. 6 TIMING WAVEFORM OF CE# OPERATION tCH tCL Clock tCSS tCSH tCYC CKE# Address A1 A2 A3 A4 A5 WRITE# CEx# ADV OE# tOE tLZOE Data Out tHZC Q1 tCD tLZC Q2 Q4 tDS tDH Data In D3 NOTES: D5 Dont Care Undefined WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED2ZL361MS White Electronic Designs PACKAGE DIMENSION: 119 BUMP PBGA 2.79 (0.110) MAX 7.62 (0.300) TYP 17.00 (0.669) TYP R 1.52 (0.060) MAX (4x) A B A1 CORNER C D E F 1.27 (0.050) TYP G H 20.32 (0.800) TYP 23.00 (0.905) TYP J K L M N P R T U 0.711 (0.028) MAX 1.27 (0.050) TYP ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION COMMERCIAL TEMP RANGE (0°C TO 70°C) Part Number Configuration WED2ZL361MS26BC WED2ZL361MS28BC WED2ZL361MS30BC WED2ZL361MS35BC WED2ZL361MS38BC WED2ZL361MS42BC 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 tCD (ns) 2.6 2.8 3.0 3.5 3.8 4.2 INDUSTRIAL TEMP RANGE (-40°C TO +85°C) Clock (MHz) 250 225 200 166 150 133 Part Number Configuration WED2ZL361MS26BI* WED2ZL361MS28BI WED2ZL361MS30BI WED2ZL361MS35BI WED2ZL361MS38BI WED2ZL361MS42BI 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 tCD (ns) 2.6 2.8 3.0 3.5 3.8 4.2 Clock (MHz) 250 225 200 166 150 133 *Consult factory for availability. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Oct, 2002 Rev. 5 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com