EVALUATION KIT AVAILABLE MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs General Description Features The MAX11044/MAX11045/MAX11046 16-bit and MAX11054/MAX11055/MAX11056 14-bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 250ksps for each channel. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 accept a ±5V input. All inputs are overrange protected with internal ±20mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 20MHz, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX11044/MAX11045/MAX11046 are available in a 56-pin TQFN and 64-pin TQFP packages while the MAX11054/MAX11055/MAX11056 are available in TQFP only and operate over the extended -40°C to +85°C temperature range. o 16-Bit ADC (MAX11044/MAX11045/MAX11046) and 14-Bit ADC (MAX11054/MAX11055/MAX11056) Applications Automatic Test Equipment Power-Factor Monitoring and Correction Power-Grid Protection Multiphase Motor Control Vibration and Waveform Analysis 8-Channel ADC (MAX11046/MAX11056) 6-Channel ADC (MAX11045/MAX11055) 4-Channel ADC (MAX11044/MAX11054) o Single Analog and Digital Supply o High-Impedance Inputs Up to 1GΩ o On-Chip T/H Circuit for Each Channel o Fast 3µs Conversion Time o High Throughput: 250ksps for Each Channel o 16-Bit/14-Bit, High-Speed, Parallel Interface o Internal Clocked Conversions o 10ns Aperture Delay o 100ps Channel-to-Channel T/H Matching o Low Drift, Accurate 4.096V Internal Reference Providing an Input Range of ±5V o External Reference Range of 3.0V to 4.25V, Allowing Full-Scale Input Ranges of ±4.0V to ±5.2V o 56-Pin (8mm x 8mm) TQFN and 64-Pin (10mm x 10mm) TQFP Packages o Evaluation Kit Available Functional Diagram AVDD CLAMP S/H S/H 16-/14-BIT ADC 16-/14-BIT ADC BIDIRECTIONAL DRIVERS CH7† CLAMP CONFIGURATION REGISTERS AGNDS AGND BANDGAP REFERENCE REFIO 10kΩ 64 TQFP-EP* 4 DB4 MAX11045ETN+ 56 TQFN-EP* 6 DB3/CR3 MAX11045ECB+ 64 TQFP-EP* 6 DB0/CR0 MAX11046ETN+ 56 TQFN-EP* 8 MAX11046ECB+ 64 TQFP-EP* 8 MAX11054ECB+ 64 TQFP-EP* 4 MAX11055ECB+ 64 TQFP-EP* 6 MAX11056ECB+ 64 TQFP-EP* 8 WR RD CONVST SHDN DGND INT REF REF BUF EXT REF CHANNELS 56 TQFN-EP* EOC MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 PIN-PACKAGE MAX11044ETN+ CS INTERFACE AND CONTROL PART MAX11044ECB+ DB15** 8 x 16-/14-BIT REGISTERS CH0 DVDD Ordering Information RDC 4 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. RDC_SENSE* Pin Configurations appear at end of data sheet. *CONNECTED INTERNALLY TO RDC ON THE TQFN PARTS **MAX11044/MAX11045/MAX11046 †MAX11046/MAX11056 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-5036; Rev 5; 1/11 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND and DGND .....................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V CH0–CH7 to AGND ...............................................-7.5V to +7.5V REFIO, RDC to AGND ..................................-0.3V to the lower of (VAVDD + 0.3V) and +6V EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of (VDVDD + 0.3V) and +6V DB0–DB15 to AGND ....................................-0.3V to the lower of (VDVDD + 0.3V) and +6V Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................±50mA Continuous Power Dissipation 56-Pin TQFN (derate 47.6mW/°C above +70°C) ....3809.5mW 64-Pin TQFP (derate 43.5mW/°C above +70°C)........3478mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL No Missing Codes MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 16 14 > -2 -0.8 > -1 -0.6 16 14 Bits ±0.4 ±0.13 ±0.4 ±0.15 < +2 +0.8 < +1.2 +0.6 LSB LSB Bits Offset Error ±0.001 ±0.015 %FSR Channel Offset Matching ±0.001 ±0.015 %FSR Gain Error ±0.015 %FSR Positive Full-Scale Error ±0.015 %FSR Negative Full-Scale Error ±0.015 %FSR Positive Full-Scale Error Matching ±0.01 %FSR Negative Full-Scale Error Matching ±0.01 %FSR Offset Temperature Coefficient ±0.8 Channel Gain-Error Matching Between all channels µV/°C ±0.01 Gain Temperature Coefficient ±0.5 %FSR ppm/°C DYNAMIC PERFORMANCE Signal-to-Noise Ratio Signal-to-Noise and Distortion Ratio 2 SNR MAX11044/MAX11045/ MAX11046 fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 MAX11044/MAX11045/ MAX11046 SINAD fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 91 92.3 84.5 85.2 90.5 92 84.5 85.2 dB dB Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Spurious-Free Dynamic Range SYMBOL CONDITIONS SFDR MAX11044/MAX11045/ MAX11046 fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 MIN TYP 98 104 95 104 THD fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 -105 -98 -104 -95 -126 -100 dB ±1.22 x VREFIO V +1 µA dB fIN = 60Hz, full scale and ground on adjacent channel (Note 2) Channel-to-Channel Crosstalk UNITS dB MAX11044/MAX11045/ MAX11046 Total Harmonic Distortion MAX ANALOG INPUTS (CH0–CH7) Input Voltage Range (Note 3) Input Leakage Current -1 Input Capacitance 15 Input-Clamp Protection Current Each input simultaneously -20 pF +20 mA 1 250 ksps 1 1000 µs TRACK AND HOLD Throughput Rate Acquisition Time Per channel tACQ -3dB point Full-Power Bandwidth 4 -0.1dB point MHz > 0.2 Aperture Delay 10 ns Aperture-Delay Matching 100 ps Aperture Jitter 50 psRMS INTERNAL REFERENCE REFIO Voltage VREF 4.08 REFIO Temperature Coefficient 4.096 4.112 ±5 V ppm/°C EXTERNAL REFERENCE Input Current REF Voltage-Input Range -10 VREF +10 3.00 REF Input Capacitance 4.25 15 µA V pF DIGITAL INPUTS (CR0–CR3, RD, WR, CS, CONVST) Input Voltage High VIH VDVDD = 2.7V to 5.25V Input Voltage Low VIL VDVDD = 2.7V to 5.25V Input Capacitance CIN Input Current IIN Maxim Integrated 2 V 0.8 10 VIN = 0V or VDVDD V pF ±10 µA 3 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS (DB0–DB15, EOC) Output Voltage High VOH ISOURCE = 1.2mA Output Voltage Low VOL ISINK = 1mA DB0–DB15, VRD ≥ VIH or VCS ≥ VIH Three-State Output Capacitance DB0–DB15, VRD ≥ VIH or VCS ≥ VIH AVDD Digital Supply Voltage DVDD Analog Supply Current Digital Supply Current (Note 9) Shutdown Current Power-Supply Rejection IAVDD IDVDD V 0.25 Three-State Leakage Current Analog Supply Voltage VDVDD 0.4 0.4 V 10 µA 15 pF 4.75 5.25 V 2.70 5.25 V MAX11046/MAX11056, VAVDD = 5V MAX11045/MAX11055, VAVDD = 5V 48 39 MAX11044/MAX11054, VAVDD = 5V 30 MAX11046/MAX11056, VDVDD = 3.3V 7.0 MAX11045/MAX11055, VDVDD = 3.3V 6.5 MAX11044/MAX11054, VDVDD = 3.3V 5.5 IDVDD 10 IAVDD 10 PSR VAVDD = 4.9V to 5.1V (Note 5) MAX11044/MAX11045/ MAX11046 ±1 MAX11054/MAX11055/ MAX11056 ±0.25 mA mA µA LSB TIMING CHARACTERISTICS (Note 4) CONVST Rise to EOC tCON Acquisition Time tACQ CS Rise to CONVST Rise tQ Conversion time (Note 6) 1 Sample quiet time (Note 6) 3 µs 1000 µs 500 ns CONVST Rise to EOC Rise t0 EOC Fall to CONVST Fall t1 CONVST mode B0 = 0 only (Note 7) 0 ns CONVST Low Time t2 CONVST mode B0 = 1 only 20 ns ns 47 140 ns CS Fall to WR Fall t3 0 WR Low Time t4 20 ns CS Rise to WR Rise t5 0 ns Input Data Setup Time t6 10 ns Input Data Hold Time t7 1 ns CS Fall to RD Fall t8 0 ns RD Low Time t9 30 ns 4 Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RD Rise to CS Rise t10 0 ns RD High Time t11 10 ns RD Fall to Data Valid t12 RD Rise to Data Hold Time t13 35 (Note 7) ns 5 ns See the Definitions section at the end of the data sheet. Tested with alternating channels modulated at full scale and ground. See the Input Range and Protection section for more details. CLOAD = 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. fCONV = 250ksps. All data is read out. Note 5: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage. Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON). Note 7: Guaranteed by design. Note 1: Note 2: Note 3: Note 4: Typical Operating Characteristics (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. CODE (MAX1104_) 0.800 0.600 0.2 0.200 DNL (LSB) 0.4 0.400 0 -0.2 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V -0.4 -0.6 -0.8 0 -0.200 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V -0.400 -0.600 -0.800 MIN INL -0.2 MIN DNL -1.0 65536 57344 49152 40960 32768 24576 16384 8192 0 65536 Maxim Integrated 57344 49152 40960 32768 24576 16384 8192 0 OUTPUT CODE (DECIMAL) VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V MAX DNL 0.2 -0.6 -1.000 -1.0 MAX INL 0.6 INL AND DNL (LSB) 0.6 1.0 MAX11044 toc02 0.8 INL (LSB) 1.000 MAX11044 toc01 1.0 INL AND DNL vs. ANALOG SUPPLY VOLTAGE (MAX1104_) MAX11044 toc03 INTEGRAL NONLINEARITY vs. CODE (MAX1104_) 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) OUTPUT CODE (DECIMAL) 5 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Typical Operating Characteristics (continued) (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) INL AND DNL vs. TEMPERATURE (MAX1104_) 1.0 40 MAX11045 CONVERTING IAVDD (mA) MIN INL MAX DNL 35 MAX11046 STATIC 30 -0.5 TA = +25°C fSAMPLE = 250ksps MAX11045 STATIC VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps VRDC = 4.096V MIN DNL 25 MAX11044 CONVERTING MAX11044 STATIC 20 -15 10 35 60 4.75 85 4.85 4.95 5.05 VAVDD (V) ANALOG SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE 45 MAX11046 CONVERTING 40 12 10 5.25 5.15 TEMPERATURE (°C) MAX11044 toc06 -40 MAX11044 toc07 0 -1.5 TA = +25°C fSAMPLE = 250ksps MAX11046 CONVERTING MAX11045 CONVERTING 35 8 MAX11046 STATIC 30 MAX11045 STATIC IDVDD (mA) IAVDD (mA) MAX11046 CONVERTING 0.5 -1.0 VAVDD = 5.0V fSAMPLE = 250ksps 6 MAX11045 CONVERTING 4 MAX11044 CONVERTING 25 2 MAX11044 CONVERTING 20 -40 -15 10 MAX11044/MAX11045/MAX11046 STATIC MAX11044 STATIC 35 TEMPERATURE (°C) 6 MAX11044 toc05 MAX INL INL AND DNL (LSB) 45 MAX11044 toc04 1.5 ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE 60 85 0 2.75 3.25 3.75 4.25 4.75 5.25 VDVDD (V) Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Typical Operating Characteristics (continued) (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) VDVDD = 3.3V fSAMPLE = 250ksps CDBxx = 15pF 2.4 MAX11044 CONVERTING 3 TA = +25°C IAVDD 2 IDVDD IAVDD 3 2 IDVDD 1 1 1.2 4 MAX11044/MAX11045/MAX11046 STATIC 0 0 0 -15 10 35 -40 85 60 -15 10 35 2.75 85 60 4.112 MAX1960 toc10 TA = +25°C 4.09625 VAVDD = 5.0V 4.108 4.09620 4.104 4.09615 4.100 VREFIO (V) VREF (V) 4.25 4.75 5.25 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 4.09630 VRDC 4.09610 4.09605 UPPER TYPICAL LIMIT 4.096 4.092 4.09600 LOWER TYPICAL LIMIT 4.088 VREFIO 4.09595 4.084 4.09590 4.080 4.75 4.85 4.95 5.05 5.15 5.25 -40 -15 10 35 60 VAVDD (V) TEMPERATURE (°C) OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V 0.006 fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V 0.006 85 OFFSET ERROR MATCHING ERRORS (%FS) OFFSET ERROR MATCHING 0.002 -0.002 0.010 MAX11044 toc12 0.010 ERRORS (%FS) 3.75 VAVDD OR VDVDD (V) INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE OFFSET ERROR 0.002 -0.002 OFFSET ERROR -0.006 -0.006 -0.010 -0.010 4.75 4.85 4.95 5.05 VAVDD (V) Maxim Integrated 3.25 TEMPERATURE (°C) TEMPERATURE (°C) MAX1960 toc11 -40 MAX11044 toc13 IDVDD (mA) 4.8 3.6 4 5 SHUTDOWN CURRENT (µA) MAX11045 CONVERTING VAVDD = 5.0V VDVDD = 3.3V SHUTDOWN CURRENT (µA) MAX11046 CONVERTING MAX11044 toc09 5 MAX11044 toc08 7.2 6.0 ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPLY VOLTAGE ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE MAX11044 toc09a DIGITAL SUPPLY CURRENT vs. TEMPERATURE 5.15 5.25 -40 -15 10 35 60 85 TEMPERATURE (°C) 7 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Typical Operating Characteristics (continued) (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE 0.002 -0.002 0.006 GAIN ERROR MATCHING 0.002 -0.002 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V -20 GAIN ERROR ERRORS (%FS) ERRORS (%FS) GAIN ERROR fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V MAGNITUDE (dB) 0.006 0 MAX11044 toc15 fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V FFT PLOT (MAX1104_) 0.010 MAX11044 toc14 0.010 GAIN ERROR MATCHING -40 MAX11044 toc16 GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE -60 -80 -100 -0.006 -0.006 -120 -0.010 4.85 4.95 5.05 -140 -40 5.25 5.15 -15 10 35 85 60 -60 -80 -100 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS 94 SNR AND SINAD (dB) -40 75 100 95 MAX11044 toc17 fIN1 = 9838Hz fIN2 = 10235Hz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.01dBFS -20 MAGNITUDE (dB) 50 125 FREQUENCY (kHz) TWO-TONE IMD PLOT (MAX1104_) 93 SNR 92 SINAD 91 -120 -140 90 7.2 8.0 8.8 9.6 10.4 11.2 12.0 -15 10 35 85 60 TOTAL HARMONIC DISTORTION vs. TEMPERATURE (MAX1104_) SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE (MAX1104_) MAX11044 toc19 93.0 SNR SNR AND SINAD (dB) -104.5 -40 TEMPERATURE (°C) fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS -104.0 12.8 FREQUENCY (kHz) -103.5 -105.0 -105.5 92.5 92.0 SINAD fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 91.5 -106.0 -106.5 91.0 -40 -15 10 35 TEMPERATURE (°C) 8 25 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE AND DISTORTION RATIO vs. TEMPERATURE (MAX1104_) 0 THD (dB) 0 TEMPERATURE (°C) VAVDD (V) MAX11044 toc20 4.75 MAX11044 toc18 -0.010 60 85 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Typical Operating Characteristics (continued) (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION RATIO vs. FREQUENCY (MAX1104_) 92 -90 88 -106 -100 fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB from FS 86 84 -105 82 -107 4.85 4.95 5.05 5.15 -110 0.1 5.25 1 100 10 100 10 OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO AGNDS (MAX1104_) 200,000 MAX11044 toc24 -90 fIN = 60Hz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS INACTIVE CHANNEL AT AGNDS NUMBER OF OCCURANCES CROSSTALK (dB) 1 FREQUENCY (kHz) CROSSTALK vs. FREQUENCY -110 0.1 FREQUENCY (kHz) VAVDD (V) -100 -95 -120 -130 VCH_ = 0V VAVDD = 5.0V VRDC = 4.096V fSAMPLE = 250ksps 150,000 MAX11044 toc25 -105 THD (dB) -104 4.75 fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB from FS 90 SINAD (dB) THD (dB) -85 MAX11044 toc22 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -103 94 MAX11044 toc21 -102 THD vs. INPUT FREQUENCY (MAX1104_) MAX11044 toc23 THD vs. ANALOG SUPPLY VOLTAGE (MAX1104_) 100,000 50,000 0 32771 32770 32769 FREQUENCY (kHz) 32768 100 10 32767 1 32766 0.1 32765 -140 OUTPUT CODE (DECIMAL) CONVERSION TIME vs. ANALOG SUPPLY VOLATAGE 2.98 2.97 2.96 2.95 2.94 2.98 2.97 2.96 2.95 2.94 2.93 2.93 2.92 2.92 4.75 4.85 4.95 5.05 VAVDD (V) Maxim Integrated VAVDD = 5.0V 2.99 CONVERSION TIME (µs) CONVERSION TIME (µs) MAX11044 toc26 TA = +25°C 2.99 3.00 MAX11044 toc27 CONVERSION TIME vs. TEMPERATURE 3.00 5.15 5.25 -40 -15 10 35 60 85 TEMPERATURE (°C) 9 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description PIN MAX11044 (TQFN-EP) MAX11045 (TQFN-EP) MAX11046 (TQFN-EP) NAME 1 1 1 DB13 16-Bit Parallel Data Bus Digital Output Bit 13 2 2 2 DB12 16-Bit Parallel Data Bus Digital Output Bit 12 3 3 3 DB11 16-Bit Parallel Data Bus Digital Output Bit 11 4 4 4 DB10 16-Bit Parallel Data Bus Digital Output Bit 10 5 5 5 DB9 16-Bit Parallel Data Bus Digital Output Bit 9 6 6 6 DB8 7, 21, 50 7, 21, 50 7, 21, 50 DGND Digital Ground 8, 20, 51 8, 20, 51 8, 20, 51 DVDD Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input. 9 9 9 DB7 16-Bit Parallel Data Bus Digital Output Bit 7 10 10 10 DB6 16-Bit Parallel Data Bus Digital Output Bit 6 11 11 11 DB5 16-Bit Parallel Data Bus Digital Output Bit 5 12 12 12 DB4 16-Bit Parallel Data Bus Digital Output Bit 4 13 13 13 DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/ Configuration Register Input Bit 3 14 14 14 DB2/CR2 16-Bit Parallel Data Bus Digital Output Bit 2/ Configuration Register Input Bit 2 15 15 15 DB1/CR1 16-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit 1 16 16 16 DB0/CR0 16-Bit Parallel Data Bus Digital Output Bit 0/ Configuration Register Input Bit 0 17 17 17 EOC Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. CONVST Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. SHDN Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. 18 10 18 18 FUNCTION 16-Bit Parallel Data Bus Digital Output Bit 8 19 19 19 22, 28, 35, 43, 49 22, 28, 35, 43, 49 22, 28, 35, 43, 49 RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80µF total capacitance. See the Layout, Grounding, and Bypassing section. 23, 27, 33, 38, 44, 48 23, 27, 33, 38, 44, 48 23, 27, 33, 38, 44, 48 AGNDS Signal Ground. Connect all AGND and AGNDS inputs together on PCB. Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN MAX11044 (TQFN-EP) MAX11045 (TQFN-EP) MAX11046 (TQFN-EP) NAME FUNCTION 24, 30, 41, 47 24, 30, 41, 47 24, 30, 41, 47 AVDD 25, 31, 40, 46 25, 31, 40, 46 25, 31, 40, 46 AGND 32 29 26 CH0 Channel 0 Analog Input 34 32 29 CH1 Channel 1 Analog Input 37 34 32 CH2 Channel 2 Analog Input 39 37 34 CH3 Channel 3 Analog Input 36 36 36 REFIO — 39 37 CH4 — 42 39 CH5 Channel 5 Analog Input — — 42 CH6 Channel 6 Analog Input — — 45 CH7 Channel 7 Analog Input Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together. External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGND. Channel 4 Analog Input 52 52 52 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 53 53 54 CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. 54 54 54 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 55 55 55 DB15 56 56 56 DB14 26, 29, 42, 45 26, 45 — I.C. Internally Connected. Connect to AGND. — — — EP Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. Maxim Integrated 16-Bit Parallel Data Bus Digital Output Bit 15 16-Bit Parallel Data Bus Digital Output Bit 14 11 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN MAX11044 (TQFP-EP) MAX11045 (TQFP-EP) MAX11046 (TQFP-EP) NAME 1 1 1 DB14 16-Bit Parallel Data Bus Digital Output Bit 14 2 2 2 DB13 16-Bit Parallel Data Bus Digital Output Bit 13 3 3 3 DB12 16-Bit Parallel Data Bus Digital Output Bit 12 4 4 4 DB11 16-Bit Parallel Data Bus Digital Output Bit 11 5 5 5 DB10 16-Bit Parallel Data Bus Digital Output Bit 10 6 6 6 DB9 16-Bit Parallel Data Bus Digital Output Bit 9 7 7 7 DB8 8, 22, 59 8, 22, 59 8, 22, 59 DGND Digital Ground 9, 21, 60 9, 21, 60 9, 21, 60 DVDD Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input. 10 10 10 DB7 16-Bit Parallel Data Bus Digital Output Bit 7 11 11 11 DB6 16-Bit Parallel Data Bus Digital Output Bit 6 12 12 12 DB5 16-Bit Parallel Data Bus Digital Output Bit 5 13 13 13 DB4 16-Bit Parallel Data Bus Digital Output Bit 4 14 14 14 DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/ Configuration Register Input Bit 3 15 15 15 DB2/CR2 16-Bit Parallel Data Bus Digital Output Bit 2/ Configuration Register Input Bit 2 16 16 16 DB1/CR1 16-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit 1 17 17 17 DB0/CR0 16-Bit Parallel Data Bus Digital Output Bit 0/ Configuration Register Input Bit 0 18 18 18 EOC Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. CONVST Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. 19 12 FUNCTION 19 19 16-Bit Parallel Data Bus Digital Output Bit 8 20 20 20 SHDN 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 AGNDS 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input. 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 AGND Analog Ground. Connect all AGND inputs together. Signal Ground. Connect all AGND and AGNDS inputs together on PCB. Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN MAX11044 (TQFP-EP) MAX11045 (TQFP-EP) MAX11046 (TQFP-EP) NAME 26, 55 26, 55 26, 55 RDC_SENSE 27, 33, 40, 48, 54 27, 33, 40, 48, 54 27, 33, 40, 48, 54 RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80µF total capacitance. See the Layout, Grounding, and Bypassing section. 37 39 34 37 31 34 CH0 CH1 Channel 0 Analog Input Channel 1 Analog Input 42 39 37 CH2 Channel 2 Analog Input 44 42 39 CH3 Channel 3 Analog Input 41 41 41 REFIO — 44 42 CH4 Channel 4 Analog Input — 47 44 CH5 Channel 5 Analog Input — — 47 CH6 Channel 6 Analog Input — — 50 CH7 Channel 7 Analog Input 61 61 61 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 62 62 62 CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. 63 63 63 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 64 64 64 DB15 31, 34, 47, 50 31, 50 — I.C. Internally Connected. Connect to AGND. — — — EP Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. Maxim Integrated FUNCTION Reference Buffer Sense Feedback. Connect to RDC plane. External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGND. 16-Bit Parallel Data Bus Digital Output Bit 15 13 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN MAX11054 (TQFP-EP) MAX11055 (TQFP-EP) MAX11056 (TQFP-EP) NAME 1 1 1 DB12 14-Bit Parallel Data Bus Digital Output Bit 12 2 2 2 DB11 14-Bit Parallel Data Bus Digital Output Bit 11 3 3 3 DB10 14-Bit Parallel Data Bus Digital Output Bit 10 4 4 4 DB9 14-Bit Parallel Data Bus Digital Output Bit 9 5 5 5 DB8 14-Bit Parallel Data Bus Digital Output Bit 8 6 6 6 DB7 14-Bit Parallel Data Bus Digital Output Bit 7 7 7 7 DB6 8, 22, 59 8, 22, 59 8, 22, 59 DGND Digital Ground 9, 21, 60 9, 21, 60 9, 21, 60 DVDD Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input. 10 10 10 DB5 14-Bit Parallel Data Bus Digital Output Bit 5 11 11 11 DB4 14-Bit Parallel Data Bus Digital Output Bit 4 12 12 12 DB3 14-Bit Parallel Data Bus Digital Output Bit 3 13 13 13 DB2 14-Bit Parallel Data Bus Digital Output Bit 2 14 14 14 DB1/CR3 14-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit 3 15 15 15 DB0/CR2 14-Bit Parallel Data Bus Digital Output Bit 0/ Configuration Register Input Bit 2 16 16 16 CR1 Configuration Register Input Bit 1 17 17 17 CR0 Configuration Register Input Bit 0 18 18 18 EOC Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. CONVST Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. 19 14 FUNCTION 19 19 14-Bit Parallel Data Bus Digital Output Bit 6 20 20 20 SHDN 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 AGNDS 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input. 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 AGND Analog Ground. Connect all AGND inputs together. 26, 55 26, 55 26, 55 RDC_SENSE Signal Ground. Connect all AGND and AGNDS inputs together on PCB. Reference Buffer Sense Feedback. Connect to RDC plane. Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN NAME FUNCTION 27, 33, 40, 48, 54 RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80µF total capacitance. See the Layout, Grounding, and Bypassing section. 34 31 CH0 Channel 0 Analog Input 37 34 CH1 Channel 1 Analog Input 42 39 37 CH2 Channel 2 Analog Input 44 42 39 CH3 Channel 3 Analog Input 41 41 41 REFIO — 44 42 CH4 Channel 4 Analog Input — 47 44 CH5 Channel 5 Analog Input — — 47 CH6 Channel 6 Analog Input — — 50 CH7 Channel 7 Analog Input 61 61 61 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 62 62 62 CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. 63 63 63 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 64 64 64 DB13 31, 34, 47, 50 31, 50 — I.C. Internally Connected. Connect to AGND. — — — EP Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. MAX11054 (TQFP-EP) MAX11055 (TQFP-EP) MAX11056 (TQFP-EP) 27, 33, 40, 48, 54 27, 33, 40, 48, 54 37 39 Detailed Description The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 are fast, low-power ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 ideal for motor control and power monitoring. The MAX11044/MAX11045/MAX11046 and MAX11054/MAX11055/MAX11056 are available with ±5V input ranges that feature ±20mA overrange, faulttolerant inputs. The MAX11044/MAX11045/MAX11046 Maxim Integrated External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGND. 14-Bit Parallel Data Bus Digital Output Bit 13 and MAX11054/MAX11055/MAX11056 operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 20MHz, parallel data bus after a conversion time of 3µs following the end of a sample. The data bus is bidirectional and allows for easy programming of the configuration register. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 feature a reference buffer, which 15 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs is driven by an internal bandgap reference circuit (VREFIO = 4.096V). Drive REFIO with an external reference or bypass with 0.1µF capacitor to ground when using the internal reference. Analog Inputs Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Input Range and Protection The full-scale analog input voltage is a product of the reference voltage. For the MAX11044/MAX11045/ MAX11046 and MAX11054/MAX11055/MAX11056, the full-scale input is bipolar in the range of: ±(VREFIO x 5 ) 4.096 When in external reference mode, drive VREFIO with a 3.0V to 4.25V source, resulting in an input range of ±3.662V to ±5.188V, respectively. All analog inputs are fault-protected to up to ±20mA. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 include an input clamping circuit that activates when the input voltage at the analog input is above (VAVDD + 300mV) or below –(VAVDD + 300mV). The clamp circuit remains high impedance while the input signal is within the range of ±VAVDD and draws little or almost no current. However, when the input signal exceeds ±V AVDD , the clamps begin to turn on and shunt current to/from the AVDD supply. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed ±(VAVDD + 0.3V). To make use of the input clamps (see Figure 1), connect a resistor (RS) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the MAX11044/MAX11045/ MAX11046 and MAX11054/MAX11055/MAX11056 does not exceed ±20mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: PIN VOLTAGE INPUT SIGNAL AVDD DVDD DB15** CLAMP S/H 16-/14-BIT ADC SOURCE CH7† CLAMP S/H 16-/14-BIT ADC BIDIRECTIONAL DRIVERS CH0 8 x 16-/14-BIT REGISTERS RS AGNDS CONFIGURATION REGISTERS AGND INTERFACE AND CONTROL DB4 DB3/CR3 DB0/CR0 WR RD CS MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 INT REF 10kΩ BANDGAP REFERENCE SHDN EOC REF BUF EXT REF REFIO CONVST DGND RDC RDC_SENSE* *CONNECTED INTERNALLY ON THE TQFN PARTS TO RDC **MAX11044/MAX11045/MAX11046 †MAX11046/MAX11056 Figure 1. Required Setup for Clamp Circuit 16 Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs where VFAULT_MAX is the maximum voltage that the source produces during a fault condition. Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance R S = 1280Ω. While the input voltage is within the ±(VAVDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. Applications Information Digital Interface The bidirectional, parallel, digital interface, CR0–CR3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB0–DB15/DB13 output the 16-/14-bit conversion result. All bits are high impedance when RD = 1 or CS = 1. CR3 (Int/Ext Reference) CR3 selects the internal or external reference. The POR default = 0. 0 = internal reference, REFIO internally driven through a 10kΩ resistor, bypass with 0.1µF capacitor to AGND. 1 = external reference, drive REFIO with a high-quality reference. 20 CR1 (Reserved) CR1 must be set to 0. CR0 (CONVST Mode) CR0 selects the acquisition mode. The POR default = 0. 0 = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as the previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on CR3–CR0 of the bus and then raise WR once to save changes. CAUTION: When the configuration register is not being programmed, the host driving CR3–CR0 must relinquish the bus when the conversion results of the ADC are being read! Table 1. Configuration Register CR3 CR2 CR1 CR0 Int/Ext Reference Output Data Format Must be set to 0 CONVST Mode 30 MAX11044 fig02 30 CR2 (Output Data Format) CR2 selects the output data format. The POR default = 0. 0 = offset binary. 1 = two’s complement. RS = 1280Ω VAVDD = 5V MAX11044 fig03 VFAULT _ MAX - 7V RS = 20mA RS = 1280Ω VAVDD = 5V 20 AT CH_ INPUT ICLAMP (mA) ICLAMP (mA) AT CH_ INPUT 10 AT SOURCE 0 10 AT SOURCE 0 -10 -10 -20 -20 -30 -30 -50 -30 -10 10 30 SIGNAL VOLTAGE AT SOURCE AND PIN (V) Figure 2. Input Clamp Characteristics Maxim Integrated 50 -8 -6 -4 -2 0 2 4 6 8 SIGNAL VOLTAGE AT SOURCE AND PIN (V) Figure 3. Input Clamp Characteristics (Zoom In) 17 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Starting a Conversion Reading Conversion Results CONVST initiates conversions. The MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 provide two acquisition modes set through the configuration register. Allow a quiet time (tQ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. In default mode (CR0 = 0), drive CONVST low to place the MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1µs (tACQ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. In the second mode (CR0 = 1), the MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. CONVST needs to be low for at least 20ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056. The CS and RD are active-low, digital inputs that control the readout through the 16-/14-bit, parallel, 20MHz data bus (D0–D15/D13). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel’s result. When CS or RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout. CS (USER SUPPLIED) t5 t3 Reference Internal Reference The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a 0.1µF capacitor to AGND to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 10kΩ. Drive only high impedance circuits or buffer externally when using REFIO to drive external circuitry. External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 10µV in the bandwidth of up to 50kHz. CS (USER SUPPLIED) t6 t13 t12 t7 DB0–DB15/DB13 Sn Sn + 1 CONFIGURATION REGISTER Figure 4. Programming Configuration-Register Timing Requirements 18 t11 RD (USER SUPPLIED) WR (USER SUPPLIED) CR0–CR3 (USER SUPPLIED) t10 t9 t8 t4 Figure 5. Readout Timing Requirements Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs SAMPLE tCON tACQ CONVST t1 EOC tO tQ CS RD DB0–DB15/DB13 S0 S1 S6 S7 Figure 6. Conversion Timing Diagram (CR0 = 0) SAMPLE tCON tACQ CONVST t2 EOC tO tQ CS RD DB0–DB15/DB13 S0 S1 S6 S7 Figure 7. Conversion Timing Diagram (CR0 = 1) Maxim Integrated 19 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Reference Buffer The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 have a built-in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference mode. The reference buffer output feeds five RDC pins. The RDC pins should be all connected together on the PCB. The reference buffer is externally compensated and requires at least 10µF on the RDC node. For best performance, provide a total of at least 80µF on the RDC outputs. Transfer Functions Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values. VLSB = (10/4.096) x (VREF/65,536) VLSB = (10/4.096) x (VREF/65,536) 7FFF FULL-SCALE TRANSITION +FS = 32,767 x VLSB FFFF 0001 VIN + 32,768 VLSB OUTPUT CODE = 0000 FFFF FFFE 8001 7FFE 0001 0000 -FS 0 +32,766.5 x VLSB INPUT VOLTAGE (LSB) +FS -FS -32,767.5 x VLSB Figure 8. Two’s Complement Transfer Function for 16-Bit Devices 3FFF 1FFE +FS = 8191 x VLSB FULL-SCALE TRANSITION 3FFE -FS = -8192 x VLSB OUTPUT CODE = 0000 OUTPUT CODE (hex) OUTPUT CODE (hex) +FS VLSB = (10/4.096) x (VREF/16,384) FULL-SCALE TRANSITION +FS = 8191 x VLSB 0 -32,767.5 x VLSB +32,766.5 x VLSB INPUT VOLTAGE (LSB) Figure 9. Offset-Binary Transfer Function for 16-Bit Devices VLSB = (10/4.096) x (VREF/16,384) VIN + 8192 VLSB 3FFF 3FFE 2001 -FS = -8192 x VLSB VIN VLSB OUTPUT CODE = 2000 1FFF 1FFE 2001 0001 2000 0000 -FS 0 +FS -8191.5 x VLSB +8190.5 x VLSB INPUT VOLTAGE (LSB) Figure 8b. Two’s Complement Transfer Function for 14-Bit Devices 20 -FS = -32,768 x VLSB VIN OUTPUT CODE = VLSB 7FFF 8000 0001 FULL-SCALE TRANSITION 8000 8001 1FFF +FS = 32,767 x VLSB FFFE -FS = -32,768 x VLSB OUTPUT CODE (hex) OUTPUT CODE (hex) 7FFE -FS 0 -8191.5 x VLSB +8190.5 x VLSB INPUT VOLTAGE (LSB) +FS Figure 9b. Offset-Binary Transfer Function for 14-Bit Devices Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs VOLTAGE TRANSFORMER PHASE 1 OPT ADC OPT ADC CURRENT TRANSFORMER VN NEUTRAL ADC IN ADC LOAD 1 LOAD 2 MAX11046/ MAX11056 LOAD 3 I3 V3 I2 ADC ADC PHASE 2 V2 ADC ADC PHASE 3 Figure 10. Power-Grid Protection Maxim Integrated 21 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11044/ MAX11045/ MAX11046/ MAX11054/ MAX11055/ MAX11056 DSP-BASED DIGITAL PROCESSING ENGINE 16-/14-BIT ADC IGBT CURRENT DRIVERS 16-/14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC IPHASE1 IPHASE3 IPHASE2 3-PHASE ELECTRIC MOTOR POSITION ENCODER Figure 11. DSP Motor Control 22 Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Layout, Grounding, and Bypassing For best performance use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect DGND, AGND, and AGNDS pins on the MAX11044/MAX11045/MAX11046 and MAX11054/MAX11055/MAX11056 to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noisefree operation. To achieve the highest performance, connect all the RDC pins (22, 28, 35, 43, 49 for the TQFN package, or pins 27, 33, 40, 48, 54 for the TQFP package) to a local RDC plane on the PCB. In addition, on the TQFP package, the RDC_SENSE pins 26 and 55 should be directly connected to this RDC plane as well. Bypass the RDC outputs with a total of at least 80µF of capacitance. If two capacitors are used, place each as close as possible to pins 22 and 49 (TQFN) or pins 27 and 54 (TQFP). If four capacitors are used, place each as close as possible to pins 22, 28, 43, and 49 (TQFN) or pins 27, 33, 48, and 54 (TQFP). For example, two 47µF, 10V X5R capacitors in 1210 case size can be placed as close as possible to pins 22 and 49 (TQFN package) will provide excellent performance. Alternatively, four 22µF, 10V X5R capacitors in 1210 case size placed as close as possible to pins 22, 28, 43, and 49 (TQFN package) will also provide good performance. Ensure that each capacitor is connected directly into the AGND plane with an independent via. If Y5U or Z5U ceramics are used, be aware of the highvoltage coefficient these capacitors exhibit and select higher voltage rating capacitors to ensure that at least 80µF of capacitance is on the RDC plane when the plane is driven to 4.096V by the built-in reference buffer. For example, a 22µF X5R with a 10V rating is approximately 20µF at 4.096V, whereas, the same capacitor in Y5U ceramic is just 13µF. However, a Y5U 22µF capacitor with a 25V rating cap is approximately 20µF at 4.096V. Bypass AVDD and DVDD to the ground plane with 0.1µF ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10µF decoupling capacitor to AVDD and DVDD per PCB. Interconnect all of the AVDD inputs and DVDD inputs using two solid power planes. For best performance, bring the AVDD power plane in on the analog interface side of the MAX11044/ Maxim Integrated MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 and the DVDD power plane from the digital interface side of the device. For acquisition periods near minimum (1µs) use a 1nF C0G ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. Typical Application Circuits Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function. For example, -0.9 LSB guarantees no missing code while -1.1 LSB results in missing code. Offset Error The offset error is defined as the input voltage required to cause the MAX11044/MAX11045/MAX11046 digital output to be centered on code 0x8000 (offset binary) or 0x0000 (two’s complement) and the MAX11054/ MAX11055/MAX11056 digital output to be centered on code 0x0000 (offset binary) or 0x0000 (two’s complement). Ideally, this input voltage should be 0V with respect to AGNDS. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (10/4.096) x V REF x (65,534/65,536) for 16-bit, or (10/4.096) x VREF x (16,382/16,384) for 14-bit devices. For the MAX11044/MAX11045/MAX11046, top code tran23 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs sition is 0x7FFE to 0x7FFF in two’s complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two’s complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11054/MAX11055/MAX11056, top code transition is 0x1FFE to 0x1FFF in two’s complement mode and 0x3FFE to 0x3FFF in offset binary mode. The bottom code transition is 0x2000 and 0x2001 in two’s complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11044/MAX11045/MAX11046 and MAX11054/MAX11055/MAX11056, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (10/4.096) x V REF x (65,534/65,536) or (10/4.096) x V REF x (16,382/16,384), respectively from this measurement. Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is: expressed as: ⎡ ⎤ V22 + V32 + V42 + V52 ⎥ THD = 20 × log ⎢ ⎢ ⎥ V1 ⎢⎣ ⎥⎦ Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. where N = 16/14 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channel-to-channel isolation is measured by applying DC to channels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied to channel 0. A 10ksps FFT is taken for channel 0 and channel 1. Channel-to-channel isolation is expressed in dB as the power ratio of the two 60Hz magnitudes. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: ⎡ ⎤ SignalRMS SINAD(dB) = 10 × log ⎢ ⎥ ⎣ (Noise + Distortion)RMS ⎦ Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: ENOB = 24 SINAD − 1.76 6.02 where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency. Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Positive Full-Scale Error The error in the input voltage that causes the last code transition of FFFE to FFFF (hex) for 16-bit or 3FFE to 3FFF (hex) for 14-bit devices (in default offset binary mode) or 7FFE to 7FFF (hex) for 16-bit or 1FFE to 1FFF (hex) for 14bit devices (in two’s complement mode) from the ideal input voltage of 32,766.5 x (10/4.096) x (VREF/65,536) for 16-bit or 8190.5 x (10/4.096) x (VREF/16,384) for 14-bit devices after correction for offset error. Negative Full-Scale Error The error in the input voltage that causes the first code transition of 0000 to 0001 (hex) (in default offset binary mode) or 8000 to 8001 (hex) for 16-bit or 2000 to 2001 (hex) for 14-bit devices (in two’s complement mode) from the ideal input voltage of -32,767.5 x (10/4.096) x (V REF /65,536) for 16-bit or -8191.5 x (10/4.096) x (VREF/16,384) for 14-bit devices after correction for offset error. Chip Information PROCESS: BiCMOS RDC 54 22 RDC AGND 56 21 DGND AVDD 57 RDC CH1*/CH0†/I.C.‡ AVDD CH2*/CH1†/CH0‡ AGND AGNDS 20 SHDN 16 DB0/CR0 CS 62 15 DB1/CR1 RD 63 19 CONVST *EP + 18 EOC 17 DB0/CR0 *MAX11046 TQFP 10mm x 10mm CR1/DB1 DB9 10 11 12 13 14 15 16 CR3/DB3 DB10 9 CR2/DB2 DB11 8 DB4 DB12 7 DB5 6 DB6 5 DB7 4 DVDD 3 DGND 2 DB8 1 DB13 DB15 64 ‡MAX11044 †MAX11045 Maxim Integrated CH3*/CH2†/CH1‡ WR 61 CR2/DB2 TQFN 8mm x 8mm CR3/DB3 DB9 10 11 12 13 14 DB4 DB10 9 DB5 DB11 8 DB6 DB12 7 DB7 DB13 6 DVDD 5 DGND 4 DB8 3 RDC 21 DVDD 17 EOC RD 54 2 23 AGNDS 22 DGND CS 53 1 24 AVDD DVDD 60 18 CONVST + 25 AGND DGND 59 19 SHDN DB14 56 26 RDC_SENSE MAX11044 MAX11045 MAX11046 AGNDS 58 20 DVDD WR 52 DB15 55 27 RDC RDC_SENSE 55 23 AGNDS *EP REFIO 28 AGNDS 24 AVDD DVDD 51 CH4*/CH3†/CH2‡ 29 AVDD 25 AGND MAX11044 MAX11045 MAX11046 AGNDS AVDD 52 AVDD 47 DGND 50 CH5*/CH4†/CH3‡ 30 AGND 26 CH0*/I.C.†‡ AGND 46 RDC 49 AGND 27 AGNDS AGNDS 53 AGNDS 48 31 CH0*/I.C.†‡ AGND 51 DB14 AGNDS 44 32 AGNDS AGNDS 49 I.C.†‡/CH7* 50 28 RDC I.C.†‡/CH7* 45 AVDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RDC 43 CH6*/CH5†/I.C.‡ RDC CH1*/CH0†/I.C.‡ AVDD AGND CH2*/CH1†/CH0‡ AGNDS CH3*/CH2†/CH1‡ RDC REFIO CH4*/CH3†/CH2‡ AGNDS CH5*/CH4†/CH3‡ AGND AVDD TOP VIEW CH6*/CH5†/I.C.‡ Pin Configurations 25 MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs RDC CH1*/CH0†/I.C.‡ AVDD AGND CH2*/CH1†/CH0‡ AGNDS CH3*/CH2†/CH1‡ RDC REFIO CH4*/CH3†/CH2‡ AGNDS CH5*/CH4†/CH3‡ AGND AVDD CH6*/CH5†/I.C.‡ RDC Pin Configurations (continued) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AGNDS AGNDS 49 31 CH0*/I.C.†‡ I.C.†‡/CH7* 50 AGND 51 30 AGND AVDD 52 29 AVDD AGNDS 53 28 AGNDS 27 RDC RDC 54 26 RDC_SENSE RDC_SENSE 55 MAX11054 MAX11055 MAX11056 AGND 56 AVDD 57 AGNDS 58 25 AGND 24 AVDD 23 AGNDS DGND 59 22 DGND DVDD 60 21 DVDD WR 61 20 SHDN 19 CONVST CS 62 RD 63 *EP + 18 EOC 17 CR0 DB7 TQFP 10mm x 10mm ‡MAX11054 †MAX11055 CR1 DB8 10 11 12 13 14 15 16 CR2/DB0 DB9 9 DB2 DB10 8 CR3/DB1 DB11 7 DB3 6 DB4 5 DB5 4 DVDD 3 DGND 2 DB6 1 DB12 DB13 64 *MAX11056 Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 26 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 56 TQFN-EP T5688+3 21-0135 90-0047 64 TQFP-EP C64E+6 21-0084 90-0328 Maxim Integrated MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Revision History REVISION NUMBER REVISION DATE 0 10/09 Initial release 1 3/10 Added TQFP package to data sheet 1, 2, 8, 9, 19 2 5/10 Added 14-bit MAX11054/MAX11055/MAX11056 1–4, 7, 9–26 3 9/10 Style edits, specified part numbers in Typical Operating Characteristics, corrected pin names, clarified layout 4 10/10 Released the TQFP versions of MAX11044, MAX11045, and MAX11046. Revised the Electrical Characteristics, Typical Operating Characteristics, and the Input Range and Protection section. 5 1/11 Released MAX11054, MAX11055, MAX11056. Revised the Electrical Characteristics and Figures 8b and 9b. DESCRIPTION PAGES CHANGED — 1, 3–8, 13–18, 22 1–8, 15 1, 2, 4, 20 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 27 © 2011 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.