19-5106; Rev 2; 1/11 KIT ATION EVALU E L B AVAILA 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs The MAX11047/MAX11048/MAX11049 and MAX11057/ MAX11058/MAX11059 16-bit/14-bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 250ksps for each channel. The devices accept a 0 to +5V input. All inputs are overrange protected with internal ±20mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 20MHz, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. The devices operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX11047/MAX11048/MAX11049 are available in a 56-pin TQFN and 64-pin TQFP packages while the MAX11057/ MAX11058/MAX11059 are available in TQFP only. All devices operate over the extended -40°C to +85°C temperature range. Applications Automatic Test Equipment Power-Factor Monitoring and Correction Features o o o o o o o o o o o o o o o 16-Bit ADC (MAX11047/MAX11048/MAX11049) 14-Bit ADC (MAX11057/MAX11058/MAX11059) 8-Channel ADC (MAX11047/MAX11057) 6-Channel ADC (MAX11048/MAX11058) 4-Channel ADC (MAX11049/MAX11059) Single Analog and Digital Supply High-Impedance Inputs Up to 1GΩ On-Chip T/H Circuit for Each Channel Fast 3µs Conversion Time High Throughput: 250ksps for Each Channel 16-/14-Bit, High-Speed, Parallel Interface Internal Clocked Conversions 10ns Aperture Delay 100ps Channel-to-Channel T/H Matching Low Drift, Accurate 4.096V Internal Reference Providing an Input Range of 0 to 5V o External Reference Range of 3.0V to 4.25V, Allowing Full-Scale Input Ranges of +3.7V to +5.2V o 56-Pin TQFN (8mm x 8mm) and 64-Pin TQFP (10mm x 10mm) Packages o Evaluation Kit Available (MAX11046EVKIT+) Functional Diagram Power-Grid Protection Multiphase Motor Control AVDD CLAMP S/H 16-/14-BIT ADCs Ordering Information PART PIN-PACKAGE CHANNELS MAX11047ETN+ 56 TQFN-EP* 4 MAX11047ECB+ 64 TQFP-EP* 4 MAX11048ETN+ 56 TQFN-EP* 6 MAX11048ECB+ 64 TQFP-EP* 6 MAX11049ETN+ 56 TQFN-EP* 8 MAX11049ECB+ 64 TQFP-EP* 8 MAX11057ECB+ 64 TQFP-EP* 4 MAX11058ECB+ 64 TQFP-EP* 6 MAX11059ECB+ 64 TQFP-EP* CH7† S/H 16-/14-BIT ADCs AGNDS CONFIGURATION REGISTERS AGND INTERFACE AND CONTROL DB4 DB3/CR3 DB0/CR0 WRb RDb CSb BANDGAP REFERENCE REFIO 10kΩ CONVST SHDN EOCb MAX11047/MAX11048/MAX11049/ MAX11057/MAX11058/MAX11059 8 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. CLAMP BIDIRECTIONAL DRIVERS CH0 DVDD DB15** 8 x 16-/14-BIT REGISTERS Vibration and Waveform Analysis DGND INT REF REF BUF EXT REF RDC RDC_SENSE* *CONNECTED INTERNALLY ON THE TQFN PARTS **MAX11047/MAX11048/MAX11049 †MAX11049/MAX11059 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX11047–MAX11049/MAX11057–MAX11059 General Description MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND and DGND .....................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V CH0–CH7 to AGND ...............................................-2.5V to +7.5V REFIO, RDC to AGND ..................................-0.3V to the lower of (AVDD + 0.3V) and +6V EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of (DVDD + 0.3V) and +6V DB0–DB15 to AGND ....................................-0.3V to the lower of (DVDD + 0.3V) and +6V Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................±50mA Continuous Power Dissipation (TA = +70°C) 56-Pin TQFN (derated 47.6mW/°C above +70°C) ..3809.5mW 64-Pin TQFP (derate 43.5mW/°C above +70°C .........3478mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity N INL DNL No Missing Codes MAX11047/MAX11048/MAX11049 16 MAX11057/MAX11058/MAX11059 14 Bits MAX11047/MAX11048/MAX11049 -2 ±0.65 +2 MAX11057/MAX11058/MAX11059 -0.9 ±0.2 +0.9 MAX11047/MAX11048/MAX11049 > -1 ±0.7 < +1.2 MAX11057/MAX11058/MAX11059 -0.6 ±0.2 +0.7 MAX11047/MAX11048/MAX11049 16 MAX11057/MAX11058/MAX11059 14 Offset Temperature Coefficient LSB Bits ±0.001 Offset Error LSB ±0.012 ±0.8 Channel Offset Matching %FSR µV/°C ±0.01 %FSR Gain Error ±0.012 %FSR Positive Full-Scale Error ±0.017 %FSR ±0.01 %FSR Positive Full-Scale Error Matching Channel Gain-Error Matching Between all channels ±0.01 Gain Temperature Coefficient ±0.6 %FSR ppm/°C DYNAMIC PERFORMANCE Signal-to-Noise Ratio 2 SNR MAX11047/MAX11048/MAX11049, f IN = 10kHz, full-scale input 90.7 92.3 MAX11057/MAX11058/MAX11059, f IN = 10kHz, full-scale input 84.5 85.3 dB _______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Signal-to-Noise and Distortion Ratio Spurious-Free Dynamic Range Total Harmonic Distortion SYMBOL SINAD SFDR THD CONDITIONS MIN TYP MAX11047/MAX11048/MAX11049, f IN = 10kHz, full-scale input 90.5 92 MAX11057/MAX11058/MAX11059, f IN = 10kHz, full-scale input 84.5 85.2 98 108 95 108 MAX11047/MAX11048/ f IN = 10kHz, MAX11049 full-scale input MAX11057/MAX11058/ MAX11059 MAX11047/MAX11048/ f IN = 10kHz, MAX11049 full-scale input MAX11057/MAX11058/ MAX11059 UNITS dB dB -108 -98 -108 -95 -126 -100 dB 0 1.22 x VREFIO V -1 +1 µA +20 mA 250 ksps dB f IN = 60Hz, full scale and ground on adjacent channel (Note 2) Channel-to-Channel Crosstalk MAX ANALOG INPUTS (CH0–CH7) Input Voltage Range (Note 3) Input Leakage Current Input Capacitance 15 Input-Clamp Protection Current Each input simultaneously -20 pF TRACK AND HOLD Throughput Rate Per channel Acquisition Time tACQ 1 -3dB point Full-Power Bandwidth µs 4 -0.1dB point MHz > 0.2 Aperture Delay 10 ns Aperture-Delay Matching 100 ps Aperture Jitter 50 psRMS INTERNAL REFERENCE REFIO Voltage VREF 4.080 REFIO Temperature Coefficient 4.096 4.112 ±4 V ppm/°C EXTERNAL REFERENCE Input Current REF Voltage Input Range VREF -10 +10 3.00 4.25 REF Input Capacitance 15 µA V pF DIGITAL INPUTS (CR0–CR3, RD, WR, CS, CONVST) Input-Voltage High VIH VDVDD = 2.7V to 5.25V Input-Voltage Low VIL VDVDD = 2.7V to 5.25V Input Capacitance CIN Input Current I IN 2 V 0.8 V ±10 µA 10 VIN = 0 or VDVDD pF _______________________________________________________________________________________ 3 MAX11047–MAX11049/MAX11057–MAX11059 ELECTRICAL CHARACTERISTICS (continued) MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs ELECTRICAL CHARACTERISTICS (continued) VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS (DB0–DB15, EOC) Output-Voltage High VOH Output-Voltage Low VOL VDVDD 0.4 I SOURCE = 1.2mA V I SINK = 1mA 0.4 V Three-State Leakage Current DB0–DB15, VRD VIH or VCS VIH 10 µA Three-State Output Capacitance DB0–DB15, VRD VIH or VCS VIH 15 pF POWER SUPPLIES (MAX11047/MAX11057) Analog Supply Voltage AVDD 4.75 5.25 V Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current IAVDD Digital Supply Current IDVDD 25 mA VDVDD = 3.3V (Note 4) 5.5 mA Shutdown Current For DVDD 10 µA Shutdown Current For AVDD 10 µA Power-Supply Rejection PSR VAVDD = 4.9V to 5.1V (Note 5) MAX11047 ±1.2 MAX11057 ±0.3 LSB POWER SUPPLIES (MAX11048/MAX11058) Analog Supply Voltage AVDD 4.75 5.25 V Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current IAVDD Digital Supply Current IDVDD 32 mA VDVDD = 3.3V (Note 4) 6.5 mA Shutdown Current For DVDD 10 µA Shutdown Current For AVDD 10 µA Power-Supply Rejection PSR VAVDD = 4.9V to 5.1V (Note 5) MAX11048 ±1.2 MAX11058 ±0.3 LSB POWER SUPPLIES (MAX11049/MAX11059) Analog Supply Voltage AVDD 4.75 5.25 V Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current IAVDD Digital Supply Current IDVDD 39 mA VDVDD = 3.3V (Note 4) 7 mA Shutdown Current For DVDD 10 µA Shutdown Current For AVDD 10 µA Power-Supply Rejection PSR VAVDD = 4.9V to 5.1V (Note 5) MAX11049 ±1.2 MAX11059 ±0.3 LSB TIMING CHARACTERISTICS (Note 4) CONVST Rise to EOC Fall tCON Acquisition Time tACQ CS Rise to CONVST Rise 4 tQ Conversion time (Note 6) Sample quiet time (Note 6) 3 µs 1 µs 500 ns _______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33µF, CREFIO = 0.1µF, CAVDD = 4 x 0.1µF || 10µF, CDVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 65 140 ns CONVST Rise to EOC Rise t0 EOC Fall to CONVST Fall t1 CONVST mode B0 = 0 only (Note 7) 0 CONVST Low Time t2 CONVST mode B0 = 1 only 20 ns CS Fall to WR Fall t3 0 ns WR Low Time t4 20 ns CS Rise to WR Rise t5 0 ns Input Data Setup Time t6 10 ns Input Data Hold Time t7 0 ns CS Fall to RD Fall t8 0 ns RD Low Time t9 30 ns RD Rise to CS Rise t10 0 ns RD High Time t11 10 RD Fall to Data Valid t12 RD Rise to Data Hold Time t13 ns ns 35 (Note 7) 5 ns ns See the Definitions section at the end of the data sheet. Tested with alternating channels modulated at full scale and ground. See the Input Range and Protection section. CLOAD= 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. fCONV = 250ksps. All data is read out. Note 5: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage. Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON). Note 7: Guaranteed by design. Note 1: Note 2: Note 3: Note 4: Typical Operating Characteristics (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) DIFFERENTIAL NONLINEARITY (DNL) vs. CODE FOR MAX1104_ INTEGRAL NONLINEARITY (INL) vs. CODE FOR MAX1104_ 0.8 0.6 0.8 0.6 0.4 DNL (LSBs) INL (LSBs) 0.4 0.2 0 -0.2 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V -0.4 -0.6 -0.8 -1.0 MAX11047 toc02 1.0 MAX11047 toc01 1.0 0 65536 32768 49152 24576 40960 57344 OUTPUT CODE (DECIMAL) 16384 8192 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V 16384 32768 49152 65536 8192 24576 40960 57344 OUTPUT CODE (DECIMAL) _______________________________________________________________________________________ 5 MAX11047–MAX11049/MAX11057–MAX11059 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) VDVDD = 3.3V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V MIN DNL -1.5 4.85 4.95 5.05 5.15 MAX11049 STATIC MAX DNL MIN INL 5.25 MAX11048 STATIC -40 -15 10 35 22 20 MAX11047 STATIC 18 4.75 85 60 4.85 4.95 5.15 DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE DIGITAL SUPPLY CURRENT vs. TEMPERATURE 10 MAX11047 CONVERTING TA = +25°C fSAMPLE = 250ksps CDBxx = 15pF 6.0 4.8 8 VAVDD = 5.0V fSAMPLE = 250ksps 6 35 60 MAX11047 CONVERTING MAX11048 CONVERTING 2.4 2 MAX11049/MAX11048/ MAX11047 STATIC MAX11047 CONVERTING 1.2 85 MAX11049/MAX11048/ MAX11047 STATIC VDVDD = 3.3V fSAMPLE = 250ksps CDBxx = 15pF 0 0 10 MAX11048 CONVERTING 3.6 4 MAX11047 STATIC 18 -15 MAX11049 CONVERTING MAX11049 CONVERTING IDVDD (mA) MAX11048 STATIC 7.2 MAX11047 toc07 12 2.75 3.25 3.75 4.25 -40 5.25 4.75 -15 10 35 60 VDVDD (V) TEMPERATURE (°C) ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPY VOLTAGE INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE IAVDD 3 2 IDVDD 1 4 TA = +25°C 2 VRDC 4.09625 4.09620 IAVDD 3 4.09615 4.09610 4.09605 IDVDD 4.09600 1 VREFIO 4.09595 0 0 -15 10 35 TEMPERATURE (°C) 60 85 85 MAX11047 toc10 4.09630 MAX11047 toc09a TA = +25°C VREF (V) 4 5 SHUTDOWN CURRENT (µA) MAX11047 toc09 TEMPERATURE (°C) VAVDD = 5.0V VDVDD = 3.3V 5.25 MAX11047 toc08 ANALOG SUPPLY CURRENT vs. TEMPERATURE 22 6 5.05 VAVDD (V) MAX11048 CONVERTING -40 TA = +25°C fSAMPLE = 250ksps MAX11047 CONVERTING TEMPERATURE (°C) MAX11049 CONVERTING -40 26 VAVDD (V) 26 5 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps VRDC = 4.096V MIN DNL MAX11048 CONVERTING 28 24 -0.5 -1.0 IDVDD (mA) IAVDD (mA) 30 0 MAX11049 STATIC 30 MAX11049 CONVERTING 32 0.5 -1.5 4.75 34 IAVDD (mA) MIN INL -0.5 34 1.0 INL AND DNL (LSBs) 0.5 MAX INL MAX INL MAX11047 toc06 INL AND DNL (LSBs) 1.0 36 MAX11047 toc04 MAX DNL -1.0 1.5 MAX11047 toc03 1.5 0 ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE INL AND DNL vs. TEMPERATURE FOR MAX1104_ MAX11047 toc05 INL AND DNL vs. ANALOG SUPPLY VOLTAGE FOR MAX1104_ SHUTDOWN CURRENT (µA) MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs 4.09590 2.75 3.25 3.75 4.25 4.75 5.25 4.75 4.85 4.95 AVDD OR DVDD (V) _______________________________________________________________________________________ 5.05 VAVDD (V) 5.15 5.25 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs 4.108 0.006 UPPER TYPICAL LIMIT 0.010 MAX11047 toc12 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V 0.006 OFFSET ERROR MATCHING 4.100 4.096 4.092 ERRORS (%FS) OFFSET ERROR MATCHING ERRORS (%FS) VREFIO (V) 0.010 MAX11047 toc11 4.112 4.104 OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE 0.002 -0.002 0.002 -0.002 OFFSET ERROR OFFSET ERROR LOWER TYPICAL LIMIT 4.088 MAX11047 toc13 INTERNAL REFERENCE VOLTAGES vs. TEMPERATURE -0.006 -0.006 4.084 10 35 60 85 4.75 4.85 4.95 5.05 5.15 VAVDD (V) GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE 0.002 -0.002 GAIN ERROR -0.006 fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V 0.006 ERRORS (%FS) GAIN ERROR MATCHING 35 85 60 FFT PLOT FOR MAX1104_ GAIN ERROR MATCHING 0.002 -0.002 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V -20 -40 -60 -80 -100 GAIN ERROR -0.006 10 0 MAGNITUDE (dB) 0.006 MAX11047 toc14 fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V -15 TEMPERATURE (°C) TEMPERATURE (°C) 0.010 -40 5.25 MAX11047 toc15 -15 0.010 ERRORS (%FS) -0.010 -0.010 -40 MAX11047 toc16 4.080 -120 -0.010 -0.010 4.75 4.85 4.95 5.05 5.15 -15 10 35 60 85 0 25 50 75 100 125 TEMPERATURE (°C) FREQUENCY (kHz) TWO-TONE IMD PLOT FOR MAX1104_ SIGNAL-TO-NOISE RATIO (SNR) AND SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. TEMPERATURE FOR MAX1104_ TOTAL HARMONIC DISTORTION (THD) vs. TEMPERATURE FOR MAX1104_ -60 -80 -100 VAVDD = 5.0V fIN = 10kHz SINAD fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 91.5 8.4 9.2 10.0 10.8 FREQUENCY (kHz) 11.6 12.4 -109.0 -109.5 91.0 7.6 VAVDD = 5.0V fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -108.5 92.0 -120 -140 MAX11047 toc18 SNR 92.5 -108.0 THD (dB) -40 SNR AND SINAD (dB) -20 93.0 MAX11047 toc17 fIN1 = 9834Hz fIN2 = 10384Hz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.01dBFS MAX11047 toc19 VAVDD (V) 0 MAGNITUDE (dB) -140 -40 5.25 -110.0 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX11047–MAX11049/MAX11057–MAX11059 Typical Operating Characteristics (continued) (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) Typical Operating Characteristics (continued) (VAVDD = 5V, VDVDD = 3.3V, TA = +25°C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.) THD vs. ANALOG SUPPLY VOLTAGE FOR MAX1104_ -108.5 SNR 92.0 94 MAX11047 toc22 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS 93 92 SINAD (dB) -109.0 SINAD 91 90 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -109.5 91.5 89 -110.0 91.0 4.95 5.05 5.15 4.95 5.05 5.15 5.25 10.0 100.0 CROSSTALK vs. FREQUENCY OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO 2.5V FOR MAX1104_ fIN = 60Hz fSAMPLE = 250ksps TA = +25°C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS INACTIVE CHANNEL AT GND -100 -105 -110 -120 24000 20000 NUMBER OF OCCURENCES -90 -120 12000 10.0 100.0 0 0.1 1 FREQUENCY (kHz) 32768 32769 32770 32771 32772 32773 32774 OUTPUT CODE (DECIMAL) 100 10 FREQUENCY (kHz) CONVERSION TIME vs. ANALOG SUPPLY VOLTAGE CONVERSION TIME vs. TEMPERATURE TA = +25°C 2.99 3.00 MAX11047 toc26 3.00 2.98 VAVDD = 5.0V 2.99 CONVERSION TIME (µS) CONVERSION TIME (µS) 8000 4000 -140 1.0 VCHX = 2.500270V VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C 16000 -130 -115 MAX11047 toc25 THD vs. INPUT FREQUENCY FOR MAX1104_ -100 0.1 1.0 FREQUENCY (kHz) -110 2.97 2.96 2.95 2.98 2.97 2.96 2.95 2.94 2.94 2.93 2.93 2.92 2.92 4.75 4.85 4.95 5.05 VAVDD (V) 8 0.1 VAVDD (V) CROSSTALK (dB) -95 4.85 VAVDD (V) VAVDD = 5.0V fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS -90 88 4.75 5.25 MAX11047 toc24 -85 4.85 MAX11047 toc23 4.75 MAX11047 toc27 92.5 -108.0 MAX11047 toc20 fIN = 10kHz fSAMPLE = 250ksps TA = +25°C VRDC = 4.096V VIN = -0.025dB FROM FS THD (dB) SNR AND SINAD (dB) 93.0 SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. FREQUENCY FOR MAX1104_ MAX11047 toc21 SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE FOR MAX1104_ THD (dB) MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs 5.15 5.25 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs RDC 54 AGNDS 48 23 AGNDS 22 RDC AGND 56 21 DGND AVDD 57 16 DB0/CR0 CS 62 15 DB1/CR1 RD 63 RDC CH1*/CH0†/I.C.‡ AVDD CH2*/CH1†/CH0‡ AGND RDC CH1*/CH0†/I.C.‡ AVDD AGND CH2*/CH1†/CH0‡ AGNDS CH3*/CH2†/CH1‡ RDC REFIO CH4*/CH3†/CH2‡ AGNDS CH5*/CH4†/CH3‡ AGND AVDD DB1/CR1 DB9 10 11 12 13 14 15 16 DB3/CR3 DB10 9 DB2/CR2 DB11 8 DB4 DB12 7 DB5 6 DB6 5 DB7 4 DVDD 3 DGND 2 DB8 1 DB13 ‡MAX11047 †MAX11048 TQFP 10mm x 10mm CH6*/CH5†/I.C.‡ 18 EOC 17 DB0/CR0 *MAX11049 RDC AGNDS 19 CONVST *EP + DB15 64 DB2/CR2 DB3/CR3 TQFN 8mm x 8mm DB4 DB9 10 11 12 13 14 DB5 DB10 9 DB6 DB11 8 DB7 DB12 7 DVDD DB13 6 DGND 5 DB8 4 CH3*/CH2†/CH1‡ 20 SHDN WR 61 3 RDC 21 DVDD 17 EOC 2 23 AGNDS 22 DGND 18 CONVST 1 24 AVDD DVDD 60 RD 54 + 25 AGND DGND 59 CS 53 DB14 56 26 RDC_SENSE MAX11047 MAX11048 MAX11049 AGNDS 58 19 SHDN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AGNDS AGNDS 49 31 CH0*/I.C.†‡ I.C.†‡/CH7* 50 AGND 51 30 AGND AVDD 52 29 AVDD AGNDS 53 28 AGNDS 27 RDC RDC 54 26 RDC_SENSE RDC_SENSE 55 MAX11057 MAX11058 MAX11059 AGND 56 AVDD 57 AGNDS 58 25 AGND 24 AVDD 23 AGNDS DGND 59 22 DGND DVDD 60 21 DVDD WR 61 20 SHDN 19 CONVST CS 62 RD 63 *EP + 18 EOC 17 CR0 *MAX11059 TQFP 10mm x 10mm CR1 DB7 10 11 12 13 14 15 16 DB0/CR2 DB8 9 DB1/CR3 DB9 8 DB2 DB10 7 DB3 6 DB4 5 DB5 4 DVDD 3 DGND 2 DB11 ‡MAX11057 †MAX11058 1 DB12 DB13 64 DB6 DB15 55 27 RDC RDC_SENSE 55 20 DVDD *EP REFIO 28 AGNDS 24 AVDD WR 52 CH4*/CH3†/CH2‡ 29 AVDD AVDD 47 DVDD 51 AGNDS AVDD 52 AGNDS 53 MAX11047 MAX11048 MAX11049 CH5*/CH4†/CH3‡ 30 AGND 26 CH0*/I.C.†‡ 25 AGND RDC 49 AGND 27 AGNDS AGND 46 DGND 50 31 CH0*/I.C.†‡ AGND 51 DB14 AGNDS 44 32 AGNDS AGNDS 49 I.C.†‡/CH7* 50 28 RDC I.C.†‡/CH7* 45 AVDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RDC 43 CH6*/CH5†/I.C.‡ RDC CH1*/CH0†/I.C.‡ AVDD AGND CH2*/CH1†/CH0‡ AGNDS CH3*/CH2†/CH1‡ RDC REFIO CH4*/CH3†/CH2‡ AGNDS CH5*/CH4†/CH3‡ AGND AVDD CH6*/CH5†/I.C.‡ TOP VIEW _______________________________________________________________________________________ 9 MAX11047–MAX11049/MAX11057–MAX11059 Pin Configurations MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description PIN MAX11047 (TQFN-EP) MAX11048 (TQFN-EP) MAX11049 (TQFN-EP) NAME FUNCTION 1 1 1 DB13 16-Bit Parallel Data Bus Digital Output Bit 13 2 2 2 DB12 16-Bit Parallel Data Bus Digital Output Bit 12 3 3 3 DB11 16-Bit Parallel Data Bus Digital Output Bit 11 4 4 4 DB10 16-Bit Parallel Data Bus Digital Output Bit 10 5 5 5 DB9 16-Bit Parallel Data Bus Digital Output Bit 9 6 6 6 DB8 16-Bit Parallel Data Bus Digital Output Bit 8 7, 21, 50 7, 21, 50 7, 21, 50 DGND 8, 20, 51 8, 20, 51 8, 20, 51 DVDD 9 9 9 DB7 16-Bit Parallel Data Bus Digital Output Bit 7 10 10 10 DB6 16-Bit Parallel Data Bus Digital Output Bit 6 11 11 11 DB5 16-Bit Parallel Data Bus Digital Output Bit 5 12 12 12 DB4 16-Bit Parallel Data Bus Digital Output Bit 4 13 13 13 DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3 14 14 14 DB2/CR2 16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2 15 15 15 DB1/CR1 16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1 16 16 16 DB0/CR0 16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0 17 17 17 EOC Active-Low End of Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. 18 18 18 CONVST Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. 19 19 19 SHDN Shutdown Input. If SHDN is held high, the entire device enters and stays in a low-current state. Contents of the Configuration register are not lost when in the shutdown state. 22, 28, 35, 43, 49 22, 28, 35, 43, 49 22, 28, 35, 43, 49 RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80µF total capacitance. See the Layout, Grounding, and Bypassing section. 23, 27, 33, 38, 44, 48 23, 27, 33, 38, 44, 48 23, 27, 33, 38, 44, 48 AGNDS 24, 30, 41, 47 24, 30, 41, 47 24, 30, 41, 47 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input. 25, 31, 40, 46 25, 31, 40, 46 25, 31, 40, 46 AGND Analog Ground. Connect all AGND inputs together. 26, 29, 42, 45 26, 45 — I.C. Internally Connected. Connect to AGND 32 29 26 CH0 Channel 0 Analog Input 34 32 29 CH1 Channel 1 Analog Input 36 36 36 REFIO 10 Digital Ground Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input. Signal Ground. Connect all AGND and AGNDS inputs together on PWB. External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGND. ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs PIN MAX11047 (TQFN-EP) MAX11048 (TQFN-EP) MAX11049 (TQFN-EP) NAME FUNCTION 37 34 32 CH2 Channel 2 Analog Input 39 37 34 CH3 Channel 3 Analog Input — 39 37 CH4 Channel 4 Analog Input — 42 39 CH5 Channel 5 Analog Input — — 42 CH6 Channel 6 Analog Input — — 45 CH7 Channel 7 Analog Input 52 52 52 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 53 53 53 CS Active Low-Chip Select Input. Drive CS low when reading from or writing to the ADC. 54 54 54 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 55 55 55 DB15 16-Bit Parallel Data Bus Digital Output Bit 15 56 56 56 DB14 16-Bit Parallel Data Bus Digital Output Bit 14 — — — EP MAX11047 (TQFP-EP) MAX11048 (TQFP-EP) MAX11049 (TQFP-EP) NAME FUNCTION 1 1 1 DB14 16-Bit Parallel Data Bus Digital Output Bit 14 2 2 2 DB13 16-Bit Parallel Data Bus Digital Output Bit 13 3 3 3 DB12 16-Bit Parallel Data Bus Digital Output Bit 12 4 4 4 DB11 16-Bit Parallel Data Bus Digital Output Bit 11 5 5 5 DB10 16-Bit Parallel Data Bus Digital Output Bit 10 6 6 6 DB9 16-Bit Parallel Data Bus Digital Output Bit 9 7 7 7 DB8 8, 22, 59 8, 22, 59 8, 22, 59 DGND 9, 21, 60 9, 21, 60 9, 21, 60 DVDD 10 10 10 DB7 16-Bit Parallel Data Bus Digital Output Bit 7 11 11 11 DB6 16-Bit Parallel Data Bus Digital Output Bit 6 12 12 12 DB5 16-Bit Parallel Data Bus Digital Output Bit 5 13 13 13 DB4 16-Bit Parallel Data Bus Digital Output Bit 4 14 14 14 DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3 15 15 15 DB2/CR2 16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2 16 16 16 DB1/CR1 16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1 17 17 17 DB0/CR0 16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. PIN 16-Bit Parallel Data Bus Digital Output Bit 8 Digital Ground Digital Supply. Bypass to DGND with a 0.µF capacitor at each DVDD input. ______________________________________________________________________________________ 11 MAX11047–MAX11049/MAX11057–MAX11059 Pin Description (continued) MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN MAX11047 (TQFP-EP) MAX11048 (TQFP-EP) MAX11049 (TQFP-EP) NAME 18 18 18 EOC 19 19 19 CONVST 20 20 20 SHDN 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 AGNDS 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input. 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 AGND Analog Ground. Connect all AGND inputs together. 26, 55 26, 55 26, 55 27, 33, 40, 48, 54 27, 33, 40, 48, 54 27, 33, 40, 48, 54 RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80µF total capacitance. See the Layout, Grounding, and Bypassing section. 31, 34, 47, 50 31, 50 — I.C. Internally Connected. Connect to AGND. 37 34 31 CH0 Channel 0 Analog Input 39 37 34 CH1 Channel 1 Analog Input 41 41 41 REFIO 42 39 37 CH2 Channel 2 Analog Input 44 42 39 CH3 Channel 3 Analog Input — 44 42 CH4 Channel 4 Analog Input — 47 44 CH5 Channel 5 Analog Input — — 47 CH6 Channel 6 Analog Input — — 50 CH7 Channel 7 Analog Input 61 61 61 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 62 62 62 CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. 63 63 63 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 64 64 64 DB15 — — — EP 12 FUNCTION Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device enters and stays in a low-current state. Contents of the Configuration register are not lost when in the shutdown state. Signal Ground. Connect all AGND and AGNDS inputs together. RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane. External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGND. 16-Bit Parallel Data Bus Digital Out Bit 15 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs PIN MAX11057 (TQFP-EP) MAX11058 (TQFP-EP) MAX11059 (TQFP-EP) NAME FUNCTION 1 1 1 DB12 14-Bit Parallel Data Bus Digital Output Bit 12 2 2 2 DB11 14-Bit Parallel Data Bus Digital Output Bit 11 3 3 3 DB10 14-Bit Parallel Data Bus Digital Output Bit 10 4 4 4 DB9 14-Bit Parallel Data Bus Digital Output Bit 9 5 5 5 DB8 14-Bit Parallel Data Bus Digital Output Bit 8 6 6 6 DB7 14-Bit Parallel Data Bus Digital Output Bit 7 7 7 7 DB6 8, 22, 59 8, 22, 59 8, 22, 59 DGND 9, 21, 60 9, 21, 60 9, 21, 60 DVDD 10 10 10 DB5 14-Bit Parallel Data Bus Digital Output Bit 5 11 11 11 DB4 14-Bit Parallel Data Bus Digital Output Bit 4 12 12 12 DB3 14-Bit Parallel Data Bus Digital Output Bit 3 13 13 13 DB2 14-Bit Parallel Data Bus Digital Output Bit 2 14 14 14 DB1/CR3 15 15 15 DB0/CR2 16 16 16 CR1 Configuration Register Input Bit 1 17 17 17 CR0 Configuration Register Input Bit 0 18 18 18 EOC Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. 19 19 19 CONVST 20 20 20 SHDN 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 23, 28, 32, 38, 43, 49, 53, 58 AGNDS 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 24, 29, 35, 46, 52, 57 AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input. 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 25, 30, 36, 45, 51, 56 AGND Analog Ground. Connect all AGND inputs together. 26, 55 26, 55 26, 55 27, 33, 40,48, 54 27, 33, 40,48, 54 27, 33, 40,48, 54 RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80µF total capacitance. See the Layout, Grounding, and Bypassing section. 31, 34, 47, 50 31, 50 — I.C. Internally Connected. Connect to AGND. 37 34 31 CH0 Channel 0 Analog Input 39 37 34 CH1 Channel 1 Analog Input 14-Bit Parallel Data Bus Digital Output Bit 6 Digital Ground Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input. 14-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 3 14-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 2 Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device enters and stays in a low-current state. Contents of the Configuration register are not lost when in the shutdown state. Signal Ground. Connect all AGND and AGNDS inputs together. RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane. ______________________________________________________________________________________ 13 MAX11047–MAX11049/MAX11057–MAX11059 Pin Description (continued) MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Pin Description (continued) PIN MAX11057 (TQFP-EP) MAX11058 (TQFP-EP) MAX11059 (TQFP-EP) NAME FUNCTION 41 41 41 REFIO 42 39 37 CH2 Channel 2 Analog Input 44 42 39 CH3 Channel 3 Analog Input — 44 42 CH4 Channel 4 Analog Input — 47 44 CH5 Channel 5 Analog Input — — 47 CH6 Channel 6 Analog Input — — 50 CH7 Channel 7 Analog Input 61 61 61 WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. 62 62 62 CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. 63 63 63 RD Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 64 64 64 DB13 — — — EP External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to AGND. 14-Bit Parallel Data Bus Digital Out Bit 13 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. Detailed Description The MAX11047/MAX11048/MAX11049 and MAX11057/ MAX11058/MAX11059 are fast, low-power ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the devices ideal for motor control and power monitoring. The devices are available with a 0 to 5V input range that features ±20mA overrange, fault-tolerant inputs. The devices operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The devices perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 20MHz, parallel data bus after a conversion time of 3µs following the end of a sample. The 14 data bus is bidirectional and allows for easy programming of the configuration register. The devices feature a reference buffer, which is driven by an internal bandgap reference circuit (VREFIO = 4.096V). Drive REFIO with an external reference or bypass with a 0.1µF capacitor to ground when using the internal reference. Analog Inputs Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs 0 to + VREFIO x 5.0 4.096 In external reference mode, drive VREFIO with a 3.0V to 4.25V source, resulting in a full-scale input range of 3.662V to 5.188V, respectively. All analog inputs are fault-protected up to ±20mA. The devices include an input clamping circuit that activates when the input voltage at the analog input is above (VAVDD + 300mV) or below -300mV. The clamp circuit remains high impedance while the input signal is within the range of 0V to +VAVDD and draws little to no current. However, when the input signal exceeds the range of 0V to +V AVDD , the clamps begin to turn on. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of 0V to +VAVDD. To make use of the input clamps, connect a resistor (RS) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the devices does not exceed ±20mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: RS = VFAULT _ MAX − 7V 20mA where VFAULT_MAX is the maximum voltage that the source produces during a fault condition. PIN VOLTAGE AVDD DVDD DB15** CH0 CLAMP S/H 16-/14-BIT ADC SOURCE CH7† CLAMP S/H 16-/14-BIT ADC BIDIRECTIONAL DRIVERS RS 8 x 16-/14-BIT REGISTERS INPUT SIGNAL AGNDS CONFIGURATION REGISTERS AGND INTERFACE AND CONTROL DB4 DB3/CR3 DB0/CR0 WRb RDb CSb MAX11047/MAX11048/MAX11049/ MAX11057/MAX11058/MAX11059 INT REF 10kΩ BANDGAP REFERENCE *CONNECTED INTERNALLY ON THE TQFN PARTS **MAX11047/MAX11048/MAX11049 SHDN EOCb DGND RDC REF BUF EXT REF REFIO CONVST RDC_SENSE* †MAX11049/MAX11059 Figure 1. Required Setup for Clamp Circuit ______________________________________________________________________________________ 15 MAX11047–MAX11049/MAX11057–MAX11059 Input Range and Protection The full-scale analog input voltage is a product of the reference voltage. For the devices, the input is unipolar in the range of: 25 25 RS = 1170I VAVDD = 5.0V 20 15 AT CH_ INPUT 5 0 AT CH_ INPUT 10 ICLAMP (mA) 10 AT SOURCE -5 AT SOURCE 5 0 -5 -10 -10 -15 -15 -20 -20 -25 -25 -30 -20 -10 0 10 20 30 -4 40 -2 0 2 4 6 8 SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) Figure 3. Input Clamp Characteristics (Zoom In) Figure 2. Input Clamp Characteristics Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance R S = 1280Ω. While the input voltage is within the -300mV to +(VAVDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. Applications Information Digital Interface The bidirectional, parallel, digital interface, CR0–CR3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB0–DB15/13, output the 16-/14-bit conversion result. All bits are high impedance when RD = 1 or CS = 1. CR3 (Int/Ext Reference) CR3 selects the internal or external reference. The POR default = 0. 0 = internal reference, REFIO internally driven through a 10kΩ resistor, bypass with 0.1µF capacitor to AGND. 1 = external reference, drive REFIO with a high quality reference. CR2 (Output Data Format) CR2 selects the output data format. The POR default = 0. 0 = offset binary. 1 = two’s complement. 16 RS = 1170I VAVDD = 5.0V 20 15 ICLAMP (mA) MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs CR1 (Reserved) CR1 must be set to 0. CR0 (CONVST Mode) CR0 selects the acquisition mode. The POR default = 0. 0 = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on CR3–CR0 of the bus and then raise WR once to save changes. CAUTION: The host driving CR3–CR0 must relinquish the bus when the conversion results of the ADC are being read. Starting a Conversion CONVST initiates conversions. The devices provide two acquisition modes set through the configuration register. Allow a quiet time (tQ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. Table 1. Configuration Register CR3 CR2 CR1 CR0 Int/Ext Reference Output Data Format Must be set to 0 CONVST Mode ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Reading Conversion Results The CS and RD are active-low, digital inputs that control the readout through the 16-/14-bit, parallel, 20MHz data bus (D0–D15/13). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel’s result. When CS or RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout. Reference Internal Reference The devices feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a 0.1µF capacitor to AGND to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 10kΩ. Drive only high-impedance circuits or buffer externally when using REFIO to drive external circuitry. External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 10µV in the bandwidth of up to 50kHz. Reference Buffer The devices have a built- in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference modes. The internal reference buffer output feeds five RDC outputs. Connect all RDC outputs together. The reference buffer is externally compensated and requires at least 10µF on the RDC node for stability. For best performance, provide a total of at least 80µF on the RDC outputs. Transfer Functions Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values. Layout, Grounding, and Bypassing For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect DGND, AGND, and AGNDS pins on the devices to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noise-free operation. To achieve the highest performance, connect all the RDC pins 22, 28, 35, 43, and 49 for the TQFN package or pins 27, 33, 40, 48, and 54 for the TQFP package to a local RDC plane on the PCB. In addition, on the TQFP package, the RDC_SENSE pins 26 and 55 should be directly connected to this RDC plane as well. Bypass the RDC outputs with a total of at least 80µF of capacitance. For example, if two capacitors are used, place two 47µF, 10V X5R capacitors in 1210 case size as close as possible to pins 22 and 49 (TQFN), or pins 27 and 54 (TQFP). Alternatively, if four capacitors are used, place four 22µF, 10V X5R capacitors in 1210 case size as close as possible to pins 22, 28, 43, and 49 (TQFN), or pins 27, 33, 48, and 54 (TQFP). Ensure that each capacitor is connected directly into the GND plane with an independent via. In cases where Y5U or Z5U ceramics are used, select higher voltage rating capacitors to compensate for the high-voltage coefficient of these ceramic capacitors, thus ensuring that at least 80µF of capacitance is on the RDC plane when the plane is driven to 4.096V by the internal reference buffer. For example, at 4.096V, a 22µF X5R ceramic capacitor with a 10V rating diminishes to only 20µF, whereas the same capacitor in Y5U ceramic at 4.096V decreases to about 13µF. However, a 22µF Y5U ceramic capacitor with a 25V rating capacitor is approximately 20µF at 4.096V. ______________________________________________________________________________________ 17 MAX11047–MAX11049/MAX11057–MAX11059 In default mode (CR0 = 0), drive CONVST low to place the devices into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1µs (tACQ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the devices begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. In the second mode (CR0 = 1), the devices enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. Drive CONVST low for at least 20ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the devices. MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Bypass AVDD and DVDD to the ground plane with 0.1µF ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10µF decoupling capacitor to AVDD and DVDD per PCB. Interconnect all of the AVDD inputs and DVDD inputs using two solid power planes. For best performance, bring the AVDD power plane in on the analog interface side of the devices and the DVDD power plane from the digital interface side of the devices. For sampling periods near minimum (1µs) use a 1nF C0G ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the devices. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. CS (USER SUPPLIED) t5 t3 t4 WR (USER SUPPLIED) t7 t6 CONFIGURATION REGISTER CR0–CR3 (USER SUPPLIED) Figure 4. Programming Configuration-Register Timing Requirements CS (USER SUPPLIED) t10 t9 t8 t11 RD (USER SUPPLIED) t13 t12 DB0–DB15 Sn Sn + 1 Figure 5. Readout Timing Requirements 18 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047–MAX11049/MAX11057–MAX11059 SAMPLE tCON tACQ CONVST t1 EOC tO tQ CS RD DB0–DB15 S0 S1 S6 S7 Figure 6. Conversion Timing Diagram (CR0 = 0) SAMPLE tCON tACQ CONVST t2 EOC tO tQ CS RD DB0–DB15 S0 S1 S6 S7 Figure 7. Conversion Timing Diagram (CR0 = 1) ______________________________________________________________________________________ 19 7FFF VLSB = FS 65536 FULL-SCALE TRANSITION 1FFF OUTPUT CODE (hex) OUTPUT CODE (hex) VLSB = FS 16384 0001 0000 FFFF 0001 0000 3FFF FFFE 3FFE 8001 2001 8000 2000 0 FS/2 0 +FS FS/2 OUTPUT CODE = VIN x 65536 - 32768, 5 VREFIO x 4.096 FS = 5 x VREF 4.096 Figure 8a. Two’s Complement Transfer Function for 16-Bit Devices FFFF VLSB = FS 65536 +FS INPUT VOLTAGE (LSB) INPUT VOLTAGE (LSB) OUTPUT CODE = VIN x 16384 - 8192, 5 VREFIO x 4.096 FS = 5 x VREF 4.096 Figure 8b. Two’s Complement Transfer Function for 14-Bit Devices FULL-SCALE TRANSITION 3FFF VLSB = FS 16384 FULL-SCALE TRANSITION 3FFE OUTPUT CODE (hex) FFFE 8001 8000 7FFF 2001 2000 1FFF 7FFE 1FFE 0001 0001 0000 0000 0 FS/2 +FS INPUT VOLTAGE (LSB) OUTPUT CODE = 5 x VREF VIN x 65536 , FS = 4.096 5 4.096 VREFIO x Figure 9a. Offset-Binary Transfer Function for 16-Bit Devices 20 FULL-SCALE TRANSITION 1FFE 7FFE OUTPUT CODE (hex) MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs 0 FS/2 +FS INPUT VOLTAGE (LSB) OUTPUT CODE = 5 x VREF VIN x 16384 , FS = 4.096 5 4.096 VREFIO x Figure 9b. Offset-Binary Transfer Function for 14-Bit Devices ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application. VOLTAGE TRANSFORMER PHASE 1 OPT 2.5V ADC OPT CURRENT TRANSFORMER ADC 2.5V VN ADC IN NEUTRAL ADC LOAD 1 MAX11049 MAX11059 LOAD 2 LOAD 3 I3 V3 I2 ADC ADC PHASE 2 V2 ADC ADC PHASE 3 Figure 10. Power-Grid Protection ______________________________________________________________________________________ 21 MAX11047–MAX11049/MAX11057–MAX11059 Typical Application Circuits MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs DSP-BASED DIGITAL PROCESSING ENGINE MAX1104x MAX1105x 16-/14-BIT ADCs IGBT CURRENT DRIVERS 16-/14-BIT ADCs 16-/14-BIT ADCs 16-/14-BIT ADCs 16-/14-BIT ADCs IPHASE1 IPHASE3 IPHASE2 3-PHASE ELECTRIC MOTOR POSITION ENCODER Figure 11. DSP Motor Control 22 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function for an SAR ADC. For example, -0.9 LSB guarantees no missing code while -1.1 LSB results in missing code. Offset Error For the MAX11047/MAX11048/MAX11049, the offset error is defined at code transition 0x0000 to 0x0001 in offset binary encoding and 0x8000 to 0x8001 for two’s complement encoding. For the MAX11057/MAX11058/ MAX11059, the offset error is defined at code transition 0x0000 to 0x0001 in offset binary encoding and 0x2000 to 0x2001 for two’s complement encoding. The offset code transitions should occur with an analog input voltage of exactly 0.5 x (5/4.096) x VREF/65,536 above GND for 16-bit devices or 0.5 x (5/4.096) x VREF/16384 above GND for 14-bit devices. The offset error is defined as the deviation between the actual analog input voltage required to produce the offset code transition and the ideal analog input of 0.5 x (5/4.096) x VREF/65,536 above GND for 16-bit devices or 0.5 x (5/4.096) x VREF/16384 above GND for 14-bit devices, expressed in LSBs. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (5/4.096) x VREF x (65,534/65,536) for 16-bit or (5/4.096) x VREF x (16382/16384) for 14-bit devices. For the devices, top code transition is 0x7FFE to 0x7FFF in two’s complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two’s complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11057/MAX11058/MAX11059, top code transition is 0x1FFE to 0x1FFF in two’s complement mode and 0x3FFE to 0x3FFF in offset binary mode. The bottom code transition is 0x2000 and 0x2001 in two’s complement mode and 0x0000 to 0x0001 in offset binary mode. For the devices, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (5/4.096) x VREF x (65,534/65,536) or (5/4.096) x VREF x (16382/16384), respectively, from this measurement. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB where N = 16/14 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: ⎡ ⎤ Signal RMS SINAD(dB) = 10 × log ⎢ ⎥ ⎣ (Noise + Distortion) RMS ⎦ Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: ENOB = SINAD − 1. 76 6. 02 Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎡ V2 2 + V3 2 + V4 2 + V 5 2 THD = 20 × log ⎢ V1 ⎢ ⎣ ⎤ ⎥ ⎥ ⎦ where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics. ______________________________________________________________________________________ 23 MAX11047–MAX11049/MAX11057–MAX11059 Definitions MAX11047–MAX11049/MAX11057–MAX11059 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture Jitter (tAJ) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channelto-channel isolation is measured by applying DC to channels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied to channel 0. A 10ksps FFT is taken for channel 0 and channel 1. Channel-to-channel isolation is expressed in dB as the power ratio of the two 60Hz magnitudes. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. 24 Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 56 TQFN-EP T5688+2 21-0135 90-0046 64 TQFP-EP C64E+6 21-0084 90-0328 ______________________________________________________________________________________ 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs REVISION NUMBER REVISION DATE 0 12/09 Initial release 1 6/10 Released MAX11047, MAX11048, and MAX11049 in TQFP packages 1–20 2 1/11 Released MAX11057, MAX11058, and MAX11059. Updated Electrical Characteristics and Typical Operating Characteristics. 1–8 DESCRIPTION PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX11047–MAX11049/MAX11057–MAX11059 Revision History