FAIRCHILD FDMS2380

FDMS2380
Dual Integrated Solenoid Driver
Features
General Description
„ 5A, 60V Load Clamp
The FDMS2380 is an intelligent low side driver with built in
recirculation and demagnetization circuits designed
specifically for driving inductive loads. The inputs are
CMOS compatible. A separate diagnostic signal for each
channel provides the system with an indication of the
operation of the solenoid or the presence of a protection
fault condition. Built-in Over-voltage, Over-current, Overtemperature circuits protect the device from these
conditions. Additional diagnostic circuitry is included for
detecting Open Load, Under-voltage and output ground
fault conditions. The FDMS2380 contains two independent
intelligent low side solenoid drivers.
„ rDS(ON) = 30mΩ (Typ.) Excitation path
„ 6V to 26V Operation
„ CMOS Compatible
„ Soft Short Detection
„ Thermal Shutdown
„ Diagnostic Output
„ Integrated Clamps
„ Over-current Protection
„ Open Load Detection
„ Over-voltage Protection
Pin 1
Applications
„ Transmission Solenoid Driver
„ Inductive Load Management
Power QFN
Internal Logical Block Diagram (One of two Identical Channels)
VBATT
Volt Regulator
& Over / Under
Voltage Detect
Soft Short
&
Recirculation
PDMOS
Driver
& Clamp
Power
PDMOS
Recirculation
Device
Over Temp
Shutdown
INA
Control
Logic
INB
OUT
Open Load
Detect
Power
NDMOS
DIAG
Diagnostic Control
&
Pulse Generation
Over
Current
Shutdown
NDMOS
Driver
Excitation
Device
GND
©2007 Fairchild Semiconductor Corporation
FDMS2380 Rev. A
1
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FDMS2380 Dual Integrated Solenoid Driver
August 2007
FDMS2380 Dual Integrated Solenoid Driver
Pin Assignment
OUT2
GND2
1
2
OUT2
3
VBATT
4
OUT1
5
DIAG1
6
INB1
7
INA1
8
OUT1
9
OUT2
VBATT
OUT1
18
OUT2
17
INA2
16
INB2
15
DIAG2
14
OUT2
13
VBATT
12
OUT1
11
GND1
10
OUT1
TOP VIEW
Pin Description
QFN Pin
Pin Name
1, 3, 14, 18, pad OUT2
OUT2
Power Driver Output (Ch2)
Pin Description
2
GND2
Ground (Ch2)
4, 13, pad VBATT
VBATT
Battery Supply Voltage. Battery supply is common to both channels
5, 9, 10, 12, pad OUT1
OUT1
Power Driver Output (Ch1)
6
DIAG1
Diagnostic Flag (Ch1). Open drain output.
7
INB1
8
INA1
Input Control Signal A (Ch1)
11
GND1
Ground (Ch1)
15
DIAG2
16
INB2
Input Control Signal B (Ch2)
17
INA2
Input Control Signal A (Ch2)
Input Control Signal B (Ch1)
Diagnostic Flag (Ch2). Open drain output.
2
FDMS2380 Rev. A
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Symbol
Parameter
Ratings
Units
-4
A
IOUT(rev)
Maximum Reverse Output Current
VBATT(max)
Maximum DC Supply Voltage (Note 2)
60
V
IIN
Input Currents
10
mA
VIN(max)
Maximum Input Voltage
8
V
IDIAG
Diagnostic Output Current
10
mA
VDIAG(max)
Maximum Diagnostic Output Voltage
8
V
Total Power dissipation
PD
TJ, TSTG
7
W
Power dissipation VBATT pad
2.3
W
Power dissipation OUT pads: PD(OUT) = PD(OUT1) + PD(OUT2)
4.6
W
-40 to 160
oC
Operating and Storage Temperature
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case: OUT pad
3.5
oC/W
RθJC
Thermal Resistance Junction to Case: VBATT pad
4.0
oC/W
RθJA
Thermal Resistance Junction to Ambient: OUT pad (Note 1)
60
oC/W
RθJA
Thermal Resistance Junction to Ambient: VBATT pad (Note 1)
60
oC/W
Ordering Information
Part Number
Package
Packing
Method
Reel Size
Tape Width
Quantity
FDMS2380
18 pin QFN
Tape & Reel
330mm
24mm
2000
Notes:
1. RθJA is measured with 1.0 in2 copper on FR-4 board. RθJC is guaranteed by design while RθJA is determined by the user’s board design.
2. The FDMS2380 requires one or more high quality local bypass capacitors (i.e., low ESL, low ESR and located physically close to the VBATT/Ground terminals of
the device) to prevent fast transients on the VBATT line from affecting the operation of the device. More specifically, the bypass scheme must reduce transients
with an amplitude passing through VBATT(ov) to have a rise time of less than 2.2V/µs.
3
FDMS2380 Rev. A
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FDMS2380 Dual Integrated Solenoid Driver
Maximum Ratings TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
---
6.0
14.0
26.0
V
Off Characteristics
VBATT(Oper) Operating Supply Voltage
ISQ
Supply Quiescent Current
VBATT = 13V, VINA = VINB = 5V
-
9.3
15
mA
ILK
Output Leakage Current
VBATT = 18V, VINA = VINB = 1.5V
-
0.2
5
mA
On Characteristics
rDS(ON)
On Resistance - Excitation Path
VRecir(sat)
Saturation Voltage - Recirculation
Path
VBATT = 13V, VINA = VINB = 5V,
-
0.030
0.080
Ω
IOUT = 5A
-
0.050
0.100
Ω
-
1.4
1.8
V
TC = 150oC
VBATT = 13V, VINA = 5V,
VINB = 0V, IOUT = 10A
Switching Characteristics (Excitation Path)
td(ON)
Output Turn-On Delay Time
-
7.0
30
μs
td(OFF)
Output Turn-Off Delay Time
-
8.3
30
μs
tr
Rise Time
-
6.5
10
μs
tf
Fall Time
-
3.0
10
μs
VBATT = 14V, RLoad = 2.5Ω
Logic Input Characteristics
VIL
Input Low Level Voltage
---
-
-
1.5
V
VIH
Input High Level Voltage
---
3.5
-
-
V
VCL
Input Clamp Voltage
IIN
Input Current (each input)
IIN <=10mA
VINA = VINB = 5V
VINA = VINB = 1.5V
5.5
-
-
V
-
90
160
μA
20
60
-
μA
Protection and Diagnostics Characteristics (Note 1)
TJ(tsd)
Thermal Shut-down Junction
Temperature
---
160
172
185
oC
IOUT(trip)
Output Current Trip
---
15
20
30
A
VBATT(ov)
Over-voltage Threshold
---
27
29
32
V
VBATT(uv)
Under-voltage Threshold
---
-
5.1
5.5
V
IOUT(ol)
Open Load Detect Current
VINA = 5V, VINB = falling edge
300
450
800
mA
VOUT(SS)
Soft Short Detect Voltage
INA=0, INB=1, VBATT − VOUT
0.3
0.43
0.6
V
RSS
Soft Short Resistance
INA=0, INB=1, from VOUT to VBATT
50
75
140
Ω
TSS
Soft Short Active Time
INA=0, INB=1, time RSS is active
1
-
3
ms
VOUT(cl1)
NDMOS Over-voltage Clamp
Ref to GND; IOUT = 5A
60
73
85
V
VOUT(cl2)
Output Inductive Clamp Voltage
VOUT − VBATT; IOUT = 5A
27
30
33
V
VFB
Flyback Diagnostic Threshold
Voltage (VOUT − VBATT )
Threshold where DIAG goes low
during Fast turn-off Mode
22
23
33
V
td(DIAG)
Diagnostic Propagation Delay Time
Fast turn-off Mode; VDIAG = 1V
tDAIGFB(min) Minimum Diagnostic Flyback Time
---
tDIAG(prot)
Protection Diagnostic Pulse Width
Over-voltage, Under-voltage,
Over-current, Over-temperature
VDIAG(low)
Diagnostic Voltage Low
IDIAG <= 1mA,
Diagnostic output active
VDIAG(cl)
Diagnostic Output Clamp Voltage
IDIAG <= 10mA
-
3
10
μs
26
42
50
μs
2
7
10
μs
-
-
0.9
V
5.5
-
-
V
Notes:
1. Integrated protection functions, as described in this data sheet, are designed to prevent the destruction of the IC and these fault conditions are considered ‘outside’
the normal operating ranges. It is important to note that the protection functions integrated into this device are NOT designed for continuous repetitive operation.
4
FDMS2380 Rev. A
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FDMS2380 Dual Integrated Solenoid Driver
Electrical Characteristics TC = 25°C unless otherwise noted
solenoid characteristics (e.g., coil resistance or coil
inductance) must be checked to ensure the FDMS2380 is
not damaged by SCIS (self-clamped inductive switching)
related overstress.
STANDBY MODE, INA = INB = 0 In the Standby mode, INA
and INB are in the logic low state and there is no output
current flow through solenoid coil. Both the PDMOS and
NDMOS output power transistors are in their off state. This
is the condition either at the start of a cycle to activate the
solenoid or after a flyback signal has been generated.
SOFT SHORT TEST MODE, INA = 0 INB = 1 This test mode
is used for detecting an output ground fault. The Soft Short
mode is initiated any time INA=0 and INB=1 when in the
Standby mode. The input conditions need to be held for a
minimum of 2 ms to allow for the timing of the Soft Short
detection circuit. After this setup time the FDMS2380
switches in a resistance (RSS) of approximately 75 ohms
between VBATT and the output (OUT) pin. This resistance,
connected in parallel to the load, acts as an additional pullup impedance to the positive power supply. To minimize
power dissipation in the event of an output ground fault, the
output pull-up resistor, activated in the Soft Short mode, is
only switched on for a period of Tss by the FDMS2380.
Regardless if the INA and INB signals remain in the Soft
Short state for a longer period of time. Immediately prior to
the end of this period, the output voltage VOUT is compared
to the VBATT supply voltage and if the difference is greater
then VOUT(ss) the diagnostic pin DIAG is pulled low. The
diagnostic pin will stay activated until the Soft Short mode is
terminated by a change of the INA or INB inputs.
EXCITATION MODE, INA = INB = 1 In the Excitation mode,
INA and INB are in the logic high state and the NDMOS
power transistor is turned on to sink current through the coil
connected to the positive supply.
The output current rises in this condition until limited by
either the coil resistance or the FDMS2380 if the current
reaches the output current trip level IOUT(trip) in which case
the FDMS2380 will turn off the NDMOS and issue a
protection diagnostic signal.
RECIRCULATION MODE, INA = 1, INB = 0 The
Recirculation mode normally follows the Excitation mode. In
this mode the NDMOS is turned off and the PDMOS is on.
The current in the coil, connected to the output, is recirculated to the positive power supply pin through the low
impedance path of the recirculation diode and the PDMOS
transistor. In the Recirculation mode the coil current IOUT
slowly decays due to the impedance of the inductive load
and the forward voltage drop across the FDMS2380
recirculation path.
To minimize the power dissipation the Soft Short test mode
should not be restarted sooner than 10 ms after a previous
Soft Short test.
The FDMS2380 will also enter the Recirculation mode
during over-voltage, over-current, and over-temperature
conditions as a means to limit the power dissipation in the
device.
Self-Protection Functions
FAST TURN-OFF MODE, INA −> 0 The fast turn-off mode
is initiated whenever the INA pin transitions from a logic high
to low state with INB also in a logic low state. In this mode
the output voltage “flies back" to VBATT+VOUT(cl2) where it is
clamped by the FDMS2380 and the coil current is
recirculated through the device back to the VBATT supply.
The larger amplitude flyback voltage causes the coil current
to rapidly discharge shutting off the solenoid. This flyback
condition shall last as long as the output voltage is greater
then VBATT and less then VOUT(cl1). During this time, the
output diagnostic pin DIAG is driven low for the duration of
the flyback pulse. Any output flyback pulses which are less
then the period tDIAGFB(min) will have its corresponding
diagnostic pulse lengthened to a minimum of tDIAGFB(min) to
help identify the flyback condition from a possible protection
diagnostic fault.
Refer to figures 2 through 6 for self-protection waveforms.
All self-protection modes except over-voltage and undervoltage are reset when INA goes to logic 0. When a selfprotection condition is detected the FDMS2380 will issue a
protection fault on the diagnostic pin. This fault condition is
signaled by a 2 μs to 10 μs pulse tDIAG(prot) on the diagnostic
pin DIAG. If the INA pin is activated while the condition
setting the protection fault is still active additional protection
fault diagnostic pulses will be issued.
Current Trip (see figure 2) Anytime during Excitation mode,
if the current in the NDMOS rises above the IOUT(trip) level,
the FDMS2380 will turn off the NDMOS and enter into the
Recirculation mode and issue a 2 μs to 10 μs protection fault
pulse on the diagnostic pin DIAG. The device will remain in
this Recirculation mode as long as the INA pin remains high
and is terminated with the falling edge of INA.
If an under-voltage condition exists the flyback diagnostic
pulse will be blocked, however, a flyback diagnostic pulse is
generated if the flyback condition is still present at the end of
the under-voltage condition.
Thermal Shutdown (see figure 3) The FDMS2380 is
internally protected against over-temperature conditions by
a temperature sensing circuit. When the FDMS2380
junction temperature exceeds the protection limit, TJ(tsd),
thermal shutdown of the device will occur. Upon entering
thermal shutdown a 2 μs to 10 μs protection fault signal is
activated in the DIAG pin. In thermal shutdown, the NDMOS
is switched off and the FDMS2380 operates in recirculation
to discharge the energy in the load coil and minimize power
dissipation. The FDMS2380 will remain in this state until INA
is taken to logic 0. A protection fault signal will be issued
each time INA is brought to a logic high while the overtemperature conditions exists.
For inputs INA and INB in the logic low state the NDMOS
and PDMOS transistors will be off. Exceptions to this
condition are; during an alternator load dump event that
could drive the output to greater then VOUT(cl1) the NDMOS
will clamp the output voltage, and during a flyback event the
PDMOS will clamp the output to VOUT(cl2).
Using the curves from figures 7 through 12, the driving
parameters (e.g., maximum duty cycle, etc.) and/or the
5
FDMS2380 Rev. A
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FDMS2380 Dual Integrated Solenoid Driver
Normal operation (see figure 1)
Open Load Detect (see figure 5) While INA and INB are
high, if the load current fails to rise above the open load
current level, IOUT(ol), before INB transitions low an open
load diagnostic fault will be issued. The diagnostic pin will
be driven low on the falling edge of the INB signal and
remain low until INA is returned to a logic 0 condition. The
open load detect mechanism senses current flowing through
the NDMOS at the falling edge of the INB signal. If an open
load condition exists during the Excitation phase but is
corrected before the INB falling edge the open load
condition would not be detected and the open load
diagnostic fault would not be generated.
The FDMS2380 is designed with a fast responding overvoltage circuit that disables the output slope control circuit
which minimizes radiated EMI. However, voltage transitions
on the VBATT pin which exceed 30 volts above the battery
need to be limited to a rise time no faster then 2.2 V/μs
through the use of a power supply bypass capacitor.
The open load detection circuit does not alter the operation
of the FDMS2380 and the PDMOS and NDMOS output
transistors will be driven into the operational modes as
commanded by the INA and INB inputs.
Undervoltage (see figure 6) The FDMS2380 will operate
down to a minimum voltage of VBATT(uv). If the battery supply
drops below this minimum voltage the device is forced into
the Standby mode. If INA is high during this condition a 2 μs
to 10 μs protection fault pulse is issued on the diagnostic
DIAG pin. In addition, a diagnostic pulse will be generated
each time INA transitions from a low to a high logic level
while remaining in this under-voltage condition.
If during the detection of the open load condition a protection
fault condition also arises, the open load diagnostics will be
terminated and then after a 2 μs to 10 μs blanking period the
protection diagnostic will be generated.
The FDMS2380 will return to normal operation when VBATT
is 6 volts or greater.
Operational Truth Table
Conditions
INA
INB
NDMOS
PDMOS
Standby Mode:
L
L
OFF
OFF
Soft Short Test Mode
L
H
OFF
ON
Excitation Mode: (No protection faults)
H
H
ON
ON
Recirculation Mode
H
L
OFF
ON
Fast Turn-off Mode: VFB < VOUT < VOUT(cl1)
L
L
OFF
VOUT clamped
to VOUT(cl2)
Alternator Load Dump: VOUT > VOUT(cl1)
L
X
NDMOS in UIS
NA
operation
Thermal Shutdown: TJ > TJ(tsd)
H
X
OFF
ON
Current Trip: IOUT > IOUT(trip)
H
H
OFF
ON
Overvoltage: VBATT > VBATT(ov)
H
H
OFF
ON
Undervoltage: VBATT < VBATT(uv)
H
X
OFF
OFF
Open Load: IOUT < IOUT(ol) refer to Open Load waveforms
(Figure 5)
-
-
-
-
H = High, L = Low, X = Don’t Care
General operation INA and INB are standard logic inputs that control Standby, Excitation, Recirculation, Diagnostics, and
Fast turn-off modes in the FDMS2380.
6
FDMS2380 Rev. A
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FDMS2380 Dual Integrated Solenoid Driver
Diagnostic Functions
Overvoltage (see figure 4) While in the Excitation mode if
the VBATT pin rises above the over-voltage threshold,
VBATT(ov), the FDMS2380 is forced into the Recirculation
mode and a protection fault signal on the diagnostic pin
DIAG is generated. This condition is not reset by INA going
low but by the voltage of the VBATT pin returning below the
VBATT(ov) level. A protection fault pulse will be issued each
time the device is driven into the Excitation state while the
over-voltage condition exists.
INA
INB
DIAG
tDAIGFB
VBATT+VOUT(cl2)
VFB
OUT
Voltage
Recirculation
Fast Turn Off
IOUT
Load
Current
Excitation
Figure 1. Normal Operation
INA
INB
DIAG
2 to 10 μs protection fault signal
OUT
Voltage
Protection Recirculation
IOUT(Trip)
NDMOS turned off & PDMOS on -- forces device into
Recirculation mode to dissipate the inductive energy.
Operates in Recirculation mode for as long as INA is high
NDMOS can not turn back on until rising edge of INA
IOUT
Load
Current
Excitation
Figure 2. Current Trip
7
FDMS2380 Rev. A
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FDMS2380 Dual Integrated Solenoid Driver
Typical Characteristics TC = 25°C unless otherwise noted
FDMS2380 Dual Integrated Solenoid Driver
Typical Characteristics TC = 25°C unless otherwise noted
INA
INB
DIAG
protection fault signal
OUT
Voltage
PDMOS ONOFF
NDMOS ONOFF
Protection Recirculation
NDMOS turned off & PDMOS on -- forces device into
Recirculation mode to dissipate the inductive energy.
Operates in Recirculation mode for as long as INA is high
NDMOS can not turn back on until rising edge of INA
TJ(tsd)
TJ
Excitation
Figure 3. Thermal Shutdown
INA
INB
DIAG
protection fault signal
VBATT(ov)
Exits over-voltage protection condition
& resumes normal operation
VBATT
OUT
Voltage
Fast Turn Off
IOUT
Load
Current
Excitation
NDMOS turned off & PDMOS on
to force device into Recirculation
Figure 4. Over-Voltage
8
FDMS2380 Rev. A
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INA
INB
DIAG
latched low on falling edge of INB
reset on falling edge of INA
OUT
Voltage
Open load condition
IOUT < IOUT(ol)
IOUT
Fast Turn Off
Load Current
IOUT(ol)
Threshold
Recirculation
Excitation
Figure 5. Intermittent Open Load
INA
INB
DIAG
protection fault signal
INA low, DIAG pulse not issued
Exits Standby mode & resumes normal operation
VBATT
VBATT(uv)
Goes into Standby mode - PDMOS & NDMOS turned off
Figure 6. Under-Voltage
9
FDMS2380 Rev. A
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FDMS2380 Dual Integrated Solenoid Driver
Typical Characteristics TC = 25°C unless otherwise noted
ESCIS, SELF CLAMPED INDUCTIVE SWITCHING
ENERGY (mJ)
ESCIS, SELF CLAMPED INDUCTIVE SWITCHING
ENERGY (mJ)
TC = 25°C unless otherwise noted
160
Single Pulse
VBatt = 14V
140
TJ = 25oC
120
100
TJ = 150oC
80
60
40
0
2
4
6
8
10
220
200
Single Pulse
VBatt = 14V
180
TJ = 25oC
160
140
TJ = 150oC
120
100
80
60
40
0
10
15
Single Pulse
VBatt = 14V
12
9
TJ = 25oC
6
TJ = 150oC
3
2
4
6
8
12
9
6
TJ = 25oC
3
TJ = 150oC
0
0
10
30
40
50
Figure 10. Self Clamped Inductive Switching
Current vs Inductance
20
80
Single Pulse
VBatt = 14V
10
STARTING TJ =
IOUT = 5A
25oC
STARTING TJ = 150oC
1
1
20
L, INDUCTANCE (mH)
VOUT, OUTPUT CLAMP VOLTAGE (V)
ISCIS, SELF CLAMPED INDUCTIVE SWITCHING
Current (A)
50
Single Pulse
VBatt = 14V
10
Figure 9. Self Clamped Inductive Switching
Current vs Inductance
70
NDMOS Over-voltage Clamp
(ref to gnd)
60
50
40
Output Inductive Clamp Voltage
(VOUT - VBATT)
30
20
-40
10
0
40
80
120
160
TC , CASE TEMPERATURE (oC)
tCLP, TIME IN CLAMP (ms)
Figure 11. Self Clamped Inductive Switching
Current vs Time in Clamp
Figure 12. Output Clamp Voltage vs Case
Temperature
10
FDMS2380 Rev. A
40
15
L, INDUCTANCE (mH)
0.1
30
Figure 8. Self Clamped Inductive Switching
Energy vs Inductance
ISCIS, SELF CLAMPED INDUCTIVE SWITCHING
Current (A)
ISCIS, SELF CLAMPED INDUCTIVE SWITCHING
Current (A)
Figure 7. Self Clamped Inductive Switching
Energy vs Inductance
0
20
L, INDUCTANCE (mH)
L, INDUCTANCE (mH)
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FDMS2380 Dual Integrated Solenoid Driver
Typical Characteristics
1.4
15
VBATT = 13V
VINA = 5V
IOUT = 5A
IOUT, OUTPUT CURRENT (A)
NORMALIZED EXCITATION PATH
ON RESISTANCE
VBATT = 13V
VINA = VINB = 5V
1.2
1.0
12
VINB = 0V
9
6
TJ = 150oC
3
TJ = 25oC
0
0.8
-40
0
40
80
120
0.6
160
0.8
1.0
TC , CASE TEMPERATURE ( C)
Figure 13. Normalized Excitation Path On
Resistance vs Case Temperature
1.6
1.8
30
IOUT(trip), OUTPUT CURRENT TRIP (A)
VBATT = 13V
VRecir(SAT), RECIRCULATION PATH
SATURATION VOLTAGE (V)
1.4
Figure 14. Output Current vs Recirculation Path
Saturation Voltage
1.54
IOUT = 10A
1.52
VINA = 5V
VINB = 0V
1.50
1.48
1.46
-40
0
40
80
120
VINA = 5V
25
20
15
10
-40
160
0
TC , CASE TEMPERATURE (oC)
40
80
120
160
TC , CASE TEMPERATURE (oC)
Figure 15. Recirculation Path Saturation Voltage
vs Case Temperature
Figure 16. Output Current Trip vs Case
Temperature
700
120
VINA = 5V
VINB = Falling Edge
Single Channel
IIN, INPUT CURRENT (μA)
Iol, OPEN LOAD DETECT CURRENT (mA)
1.2
VRecir(SAT), RECIRCULATION PATH
SATURATION VOLTAGE (V)
o
600
500
400
300
-40
0
40
80
120
VINA = VINB = 5V
80
VINA = VINB = 1.5V
60
40
-40
160
TC , CASE TEMPERATURE (oC)
0
40
80
120
160
TC , CASE TEMPERATURE (oC)
Figure 17. Open Load Detect Current vs Case
Temperature
Figure 18. Input Current vs Case Temperature
11
FDMS2380 Rev. A
100
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FDMS2380 Dual Integrated Solenoid Driver
Typical Characteristics (Continued) TC = 25°C unless otherwise noted
12
VBATT = VOUT = 18V
VINA = VINB = 1.5V
Single Channel
ISQ, SUPPLY QUIESCENT CURRENT (mA)
ILK, OUTPUT LEAKAGE CURRENT (μA)
240
220
200
180
160
-40
VBATT = VOUT = 13V
VINA = VINB = 5V
9
6
3
VINA = VINB = 0V
0
0
40
80
120
160
-40
0
TC , CASE TEMPERATURE (oC)
40
80
120
160
TC , CASE TEMPERATURE (oC)
Figure 19. Output Leakage Current vs Case
Temperature
Figure 20. Supply Quiescent Current vs Case
Temperature
Typical Application Circuit
The following schematic of an FDMS2380 used in a basic application is just one of several possible variations for this device.
It shows two external and independent controllers, one for each channel, and two solenoids being controlled by the
FDMS2380. Furthermore, it shows the external local VBATT bypass capacitor, the details of which are discussed in the
Maximum Ratings section. The FDMS2380 ground pins GND1 and GND2 are fully isolated; therefore, they are normally
connected together on the PCB.
When designing the PCB for the FDMS2380 the user needs to provide as low a thermal impedance as is possible for both
the VBATT and OUT[1,2] paddles on the bottom of the package. The power density in the dual integrated solenoid driver can
be quite large and care should be taken to optimize the thermal impedance of the system to maximize the power handling
capability of the device while minimizing the maximum operating temperature.
L1
&
2
, 1 t1
10 u
9, d O
5 , Pa
10K
Controller I
DIAG1
6
OUT1
&
8
, 1 t2
4
u
1
3, d O
1 , Pa
V batt
OUT2
FDMS2380
DISD
8
7
GND1
GND2
11
2
12
+5V
L2
INA1
INB1
FDMS2380 Rev. A
V batt
15
17
16
10K
DIAG2
INA2
ControllerII
+5V
V batt
4,13 & Pad Vbatt
V batt
INB2
www.fairchildsemi.com
FDMS2380 Dual Integrated Solenoid Driver
Typical Characteristics (Continued) TC = 25°C unless otherwise noted
Aug-2006, Rev. B
User Direction of Feed
Tape Dimensions:
P0
T
D0
E1
F
K0
Wc
W
E2
B0
Tc
A0
P1
D1
Dimensions are in millimeter
Pkg. Type
A0
B0
W
D0
D1
E1
E2
F
P1
P0
K0
T
Wc
Tc
18 pin
QFN
8.35
+/-0.10
12.35
+/-0.10
24.0
+/-0.3
1.50
+0.10/-0.0
1.50
min
1.75
+/-0.10
22.25
min
11.50
+/-0.10
16.0
+/-0.1
4.0
+/-0.1
2.40
+/-0.10
0.30
+/-0.05
21.3
+/-0.1
0.10
max
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and
lateral movement requirements.
10 deg maximum component rotation
Component Rotation (Side Sectional View)
Package Orientation
Reel Dimensions:
W1 Measured at Hub
B Min
Dim C
Dim A
max
Dim D
min
Dim N
DETAIL AA
See detail AA
W3
13” Diameter Option
W2 max Measured at Hub
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
24 mm
13” Dia
13.00
330
0.079
2.0
0.512 · 0.0008
13 ·0.20
0.819
20.8
4.00
100
0.960 + 0.078/-0
24.4 + 2/-0
1.12
28.4
0.941 – 1.079
23.9 – 27.4
13
FDMS2380 Rev. A
www.fairchildsemi.com
FDMS2380 Dual Integrated Solenoid Driver
Tape and Reel Specifications
FDMS2380 Dual Integrated Solenoid Driver
Physical Dimensions
14
FDMS2380 Rev. A
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Advance Information
Formative or In Design
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Definition
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Rev. I31
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