19-4595; Rev 1; 7/09 Multiprotocol, Pin-Selectable Data Interface Chipset Features ♦ Supports V.28 (RS-232), V.10 (RS-423), V.11 (RS-449/V.36, RS-530, RS-530A, X.21) and V.35 Protocols The MAX13171E along with the MAX13173E/ MAX13175E, form a complete pin-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that support the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry the control signals. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network. The MAX13175E contains six pin-selectable, multiprotocol cable termination networks. The MAX13171E/MAX13173E have an internal charge pump and low-dropout transmitter output stages that allow V.10-, V.11-, V.28-, and V.35-compliant operation from a single supply. The MAX13171E/MAX13173E feature a no-cable mode that reduces supply current and disables all transmitter and receiver outputs (high impedance). Short-circuit current limiting and thermal shutdown circuitry protects the receiver and transmitter outputs against excessive power dissipation. The MAX13171E/ MAX13173E have extended ESD protection for all the transmitter outputs and receivers inputs. The MAX13171E/MAX13173E/MAX13175E operate over the +3.135V to +5.5V supply range and are available in 5mm x 7mm, 38-pin TQFN packages. These devices operate over the -40°C to +85°C extended temperature range. ♦ Pin-Selectable Cable Termination Using the MAX13175E ♦ Pin-Selectable DCE/DTE Configurations ♦ 20/40Mbps (max) Data Rate in RS-449, RS-530, RS-530A, X.21, and V.35 ♦ True Fail-Safe Receivers while Maintaining V.11 and V.35 Compatibility ♦ Operates Over a Wide +3.135V to +5.5V VCC Supply Range ♦ Flexible VL Logic Reference Input Allows Interfacing Down to 1.62V ♦ Extended ESD Protection for All the Transmitter Outputs and Receivers Inputs to GND ♦ Small, 5mm x 7mm, 38-Pin TQFN Package Ordering Information Applications Data Networking PCI Cards Telecommunication Equipment CSU and DSU Data Routers TEMP RANGE PINPACKAGE MAX13171EETU+ -40°C to +85°C 38 TQFN-EP* MAX13173EETU+ -40°C to +85°C 38 TQFN-EP* PART MAX13175EETU+ -40°C to +85°C 38 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Data Switches Typical Operating Circuit T4 LL CTS DSR R4 R3 R2 DCD R1 MAX13173E T3 DTR RTS T2 T1 RXD RXC R3 R2 TXC R1 MAX13171E T3 SCTE TXD T2 T1 MAX13175E 18 13 5 10 8 22 6 23 20 19 4 1 7 16 3 9 17 12 15 11 24 14 2 TXD A (103) TXD B SCTE A (113) SCTE B TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B SG (102) SHIELD (101) RTS A (105) RTS B DTR A (108) DTR B DCD A (107) DCD B DSR A (109) DSR B CTS A (106) CTS B LL A (141) DB-25 CONNECTOR ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX13171E/MAX13173E/MAX13175E General Description MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset ABSOLUTE MAXIMUM RATINGS Transmitter Outputs T_OUT_, T_OUT_/R_IN_ (no-cable, V.28, V.10 modes) ...............................-15V to +15V Short-Circuit Duration to GND..................................Continuous Receiver Inputs R_IN_, T_OUT_/R_IN ............................................-15V to +15V R_INA to R_INB, T3OUTA/R3INA to T3OUTB/R3INB ................................................-15V to +15V Continuous Power Dissipation (TA = +70°C) 38-Pin TQFN (derate 35.7mW/°C above +70°C) ........2857mW Junction-to-Case Thermal Resistance (θJC) (Note 1) 38-Pin TQFN ....................................................................1°C/W Junction-to-Ambient Thermal Resistance (θJA) (Note 1) 38-Pin TQFN ..................................................................28°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C (All voltages to GND, unless otherwise noted.) Supply Voltages VCC ........................................................................ -0.3V to +6V VL ........................................................................... -0.3V to +6V VEE ..................................................................... +0.3V to -7.1V VDD .................................................................... -0.3V to +7.1V VDD to VCC ............................................................-0.3V to +6V Logic-Input Voltages M0, M1, M2, DCE/DTE, LATCH, INVERT, T_IN ..... -0.3V to +6V Termination Network Inputs R_A, R_B, R_C.......................................................-15V to +15V R_A to R_B (only for high-Z state) .....................................±14V R_A to R_B...........................................................................±6V R_A to R_C (only for high-Z state) .....................................±14V R_A to R_C...........................................................................±3V R_B to R_C (only for high-Z state) .......................................±3V Logic-Output Voltages R_OUT ........................................................-0.3V to (VL + 0.3V) Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAX13171E ELECTRICAL CHARACTERISTICS (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF (Figure 15), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER VCC Operating Range SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 3.135 5.5 V VL Operating Range VL 1.62 VCC V VL Supply Current IL VCC Supply Current (DCE Mode) (Digital Inputs = GND or VCC) (Transmitter Outputs Static) ICC All inputs connected to GND, all receiver outputs low, VL = +5.5V 550 800 µA RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11), no load 15 28 mA RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11), full load 150 200 mA mA V.35 mode, no load 21 38 V.35 mode, full load 150 210 mA V.28 mode, no load 15 30 mA V.28 mode, full load Internal Power Dissipation (DCE Mode)(Static) 2 PD 28 42 mA No-cable mode 0.01 10 µA RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11), full load 100 V.35 mode, full load 500 V.28 mode, full load 70 _______________________________________________________________________________________ mW Multiprotocol, Pin-Selectable Data Interface Chipset (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF (Figure 15), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN V.28, V.35 modes, no load (Note 3) Positive Charge-Pump Output Voltage Negative Charge-Pump Output Voltage VDD VEE Thermal Shutdown Protection MAX 5.93 7.1 V.28 mode, full load (Note 3) 5.6 5.86 V.35 mode, full load (Note 3) 4.6 5.1 RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11) (Note 3) 4.9 5.26 5.7 VCC V.28, V.35 modes, no load (Note 3) -5.89 V.28 mode, full load (Note 3) -5.74 -5.4 V.35 mode, full load, Note 3 -4.46 -3.8 -4.47 -4.16 RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11) (Note 3) -4.84 UNITS V No-cable mode No-cable mode V 0 Time until all VDD and VEE specifications meet Charge-Pump Enable Time TYP THSD <1 ms +145 °C LOGIC INPUTS (M0, M1, M2, DCE/DTE, T1IN, T2IN, T3IN) Input High Voltage VIH Input Low Voltage VIL Logic-Input Current IIN Pullup Resistor RPUIN 0.66 x VL V 0.33 x VL T1IN, T2IN, T3IN -1 M0, M1, M2, DCE/DTE to VL 50 100 V +1 µA 170 kΩ LOGIC OUTPUTS (R1OUT, R2OUT, R3OUT) Output High Voltage VOH ISOURCE = 4mA 0.66 x VL Output Low Voltage VOL ISINK = 4mA Output Pullup Resistor RPUY No-cable mode (to VL) Open-Circuit Differential Output Voltage VODO Open circuit, R = 1.95kΩ, Figure 1 -VCC Loaded Differential Output Voltage VODL R = 50Ω, Figure 1 0.5 x VODO R = 50Ω, Figure 1 I2I V 0.33 x VL 71.4 V kΩ V.11 TRANSMITTER +VCC V V Change in Magnitude of Output Differential Voltage |∆VOD| R = 50Ω, Figure 1 0.2 V Common-Mode Output Voltage VOC R = 50Ω, Figure 1 3.0 V Change in Magnitude of Common-Mode Output Voltage |∆VOC| R = 50Ω, Figure 1 (Note 3) 0.2 V 150 mA Short-Circuit Current ISC VOUT = GND Rise Time tr Figures 2, 6 4.5 ns Fall Time tf Figures 2, 6 6.5 ns _______________________________________________________________________________________ 3 MAX13171E/MAX13173E/MAX13175E MAX13171E ELECTRICAL CHARACTERISTICS (continued) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF (Figure 15), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER SYMBOL Transmitter Input to Output Propagation Delay (Figures 2, 6) tPHL, tPLH Data Skew |tPHL-tPLH| Channel-to-Channel Skew tSKEW TYP MAX Figures 2, 6 CONDITIONS MIN 22 28 VL ≥ +3V, Figures 2, 6 20 25 UNITS ns Figures 2, 6 (Note 3) 2 ns Figures 2, 6 (Notes 3, 4) 3 ns -50 mV V.11 RECEIVER Differential Threshold Voltage Input Hysteresis Receiver Input Current VTH -7V ≤ VCM ≤ +7V ∆VTH -7V ≤ VCM ≤ +7V -200 15 IIN -10V ≤ VA,B ≤ +10V -0.66 Receiver Input Resistance RIN -10V ≤ VA,B ≤ +10V 15 Rise or Fall Time tr, tf Figures 2, 7 Receiver Input to Output Delay tPHL, tPLH Figures 2, 7 Data Skew |tPHL-tPLH| Channel-to-Channel Skew tSKEWR mV +0.66 30 mA kΩ 3 ns 2.5 ns Figures 2, 7 (Note 3) 3 ns Figures 2, 7 (Notes 3, 4) 3 ns V.35 TRANSMITTER Differential Output Voltage VOD Full load, -4V < VCM < +4V, Figure 3 ±0.44 ±0.55 ±0.66 V Output High Current IOH VA,B = 0V -13 -11 -9 mA Output Low Current IOL VA,B = 0V 9 11 13 mA ±0.05 ±5 µA Output Leakage Current Rise or Fall Time Transmitter Input to Output Delay Data Skew Channel-to-Channel Skew IZ tr, tf tPLH, tPHL |tPLH - tPHL| tSKEWR -0.25V ≤ VOUT ≤ +0.25V, power off or no-cable mode Figures 3, 6 5 Figures 3, 6 19 ns 35 ns Figures 3, 6 (Note 3) 3 ns Figures 3, 6 (Notes 3, 4) 3 ns -50 mV V.35 RECEIVER Differential Threshold Voltage Input Hysteresis VTH -2V ≤ VCM ≤ +2V ∆VTH -2V ≤ VCM ≤ +2V -200 15 Receiver Input Current IIN -10V ≤ VA,B ≤ +10V -0.66 Receiver Input Resistance RIN -10V ≤ VA,B ≤ +10V 15 Rise or Fall Time mV +0.66 30 mA kΩ tr, tf Figures 3, 7 Receiver Input to Output Delay tPHL, tPLH Figures 3, 7 25 ns Data Skew |tPHL- tPLH| Figures 3, 7 (Note 3) 3 ns Figures 3, 7 (Notes 3, 4) 3 ns Channel-to-Channel Skew tSKEWR 3 ns V.28 TRANSMITTER Output-Voltage Swing Short-Circuit Current 4 |VOD| Open circuit RL = 3kΩ 7.1 5 6 IOH _______________________________________________________________________________________ 85 V mA Multiprotocol, Pin-Selectable Data Interface Chipset (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF (Figure 15), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER Output Leakage Current Output Slew Rate Transmitter Input to Output Delay SYMBOL IZ CONDITIONS MIN -0.25V ≤ VOUT ≤ +0.25V, power off or no-cable mode SRR/F RL = 3kΩ, CL = 2500pF (swing in ±3V), Figures 4, 10 tPHL, tPLH RL = 3kΩ, CL = 2500pF, Figures 4, 10 TYP MAX UNITS ±0.05 ±5 µA 30 V/µs 2 µs 2 V 4 1 V.28 RECEIVER Input Threshold Low VIL Input Threshold High VIH 1.2 VHYST 0.25 Input Hysteresis 0.8 Input Resistance RIN -15V ≤ VIN ≤ +15V Rise or Fall Time tr, tf Figures 5, 11 tPHL, tPLH Figures 5, 11 Receiver Input to Output Delay 3 1.2 5 V V 7 3 kΩ ns 150 ns ESD PROTECTION T_OUT, T3OUT_/R1IN_, R_IN to GND Human Body Model ±15 Air Gap Discharge IEC 61000-4-2 ±12 Contact Discharge IEC 61000-4-2 ±8 kV MAX13173E ELECTRICAL CHARACTERISTICS (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF (Figure 15), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER VCC Operating Range SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 3.135 5.5 V VL Operating Range VL 1.62 VCC V VL Supply Current IL VCC Supply Current ICC Internal Power Dissipation Positive Charge-Pump Output Voltage PD VDD All inputs connected to GND, all receiver outputs low, VL = +5.5V 680 1100 µA RS-530A, no load 11 21 mA RS-530, X.21, V.36/RS-449, DCE mode, INVERT = low, full load, transmitter outputs static, digital inputs = GND or VL 41 210 mA V.28 mode, no load 21 38 mA V.28 mode, full load 42 65 mA No-cable mode 0.01 10 µA RS-530, X.21, V.36/RS-449; DCE mode, INVERT = low, full load 120 V.28 mode, no load (Note 3) 5.9 V.28 mode with full load (Note 3) 5.6 RS-530 mode, full load (Note 3) 4.84 mW 7.1 5.79 5.15 RS-530A mode, full load 5.15 No-cable mode VCC 5.5 V _______________________________________________________________________________________ 5 MAX13171E/MAX13173E/MAX13175E MAX13171E ELECTRICAL CHARACTERISTICS (continued) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset MAX13173E ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF (Figure 15), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER Negative Charge-Pump Output Voltage SYMBOL VEE CONDITIONS MIN V.28 mode with full load (Note 3) -5.55 -5.3 -4.44 -4.17 RS-530 mode, full load (Note 3) -4.71 UNITS V -4.44 No-cable mode 0 THSD Time until all VDD and VEE specifications meet Charge-Pump Enable Time MAX -5.83 RS-530A mode, full load Thermal Shutdown Protection TYP V.28 mode, no load (Note 3) +145 °C <1 ms LOGIC INPUTS (M0, M1, M2, DCE/DTE, INVERT, T1IN, T2IN, T3IN, T4IN, T5IN/R5OUT) Input High Voltage VIH Input Low Voltage VIL Logic-Input Current Pullup Resistor IIN RPUIN 0.66 x VL V 0.33 x VL T1IN, T2IN, T3IN, T4IN -1 M0, M1, M2, DCE/DTE, INVERT to VL 50 100 V +1 µA 170 kΩ LOGIC OUTPUTS (R1OUT, R2OUT, R3OUT, R4OUT, T5IN/R5OUT) Output High Voltage VOH ISOURCE = 4mA Output Low Voltage VOL ISINK = 4mA 0.66 x VL Output Pullup Resistor RPUY No-cable mode (to VL) VODO Open circuit, R = 1.95kΩ, Figure 1 -VCC R = 50Ω, Figure 1 0.5 x VODO R = 50Ω, Figure 1 |2| V 0.33 x VL 71.4 V kΩ V.11 TRANSMITTER (T1, T2, T3) Open-Circuit Differential Output Voltage +VCC V Loaded Differential Output Voltage VODL Change in Magnitude of Output Differential Voltage |∆VOD| R = 50Ω, Figure 1 0.2 V Common-Mode Output Voltage VOC R = 50Ω, Figure 1 3.0 V Change in Magnitude of Common-Mode Output Voltage |∆VOC| R = 50Ω, Figure 1 (Note 3) 0.2 V VOUT = GND 150 mA ±0.05 ±5 µA Short-Circuit Current ISC V IZ -0.25V ≤ VOUT ≤ +0.25V, power-off or nocable mode Rise Time tr Figures 2, 6 4 10 ns Fall Time tf Figures 2, 6 6 10 ns Figures 2, 6 20 28 ns Output Leakage Current Transmitter Input to Output Prop Delay tPHL, tPLH Data Skew |tPHL- tPLH| Channel-to-Channel Skew 6 tSKEW Figures 2, 6, VL ≥ +3V 25 ns Figures 2, 6 (Note 3) 2 ns Figures 2, 6 (Notes 3, 4) 3 ns _______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF (Figure 15), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -50 mV V.11 RECEIVER (R1, R2, R3) Differential Threshold Voltage VTH -7V ≤ VCM ≤ +7V Input Hysteresis ∆VTH -7V ≤ VCM ≤ +7V -200 15 Receiver Input Current IIN -10V ≤ VA,B ≤ +10V -0.66 Receiver Input Resistance RIN -10V ≤ VA,B ≤ +10V 15 Rise or Fall Time mV +0.66 30 mA kΩ tr, tf Figures 2, 7 Receiver Input to Output Delay tPHL, tPLH Figures 2, 7 27 ns Data Skew |tPHL- tPLH| Figures 2, 7 (Note 3) 3 ns Figures 2, 7 (Notes 3, 4) 3 ns Channel-to-Channel Skew tSKEWR 3 ns V.10 TRANSMITTER (T2, T4, T5) Open-Circuit Output Voltage Swing VO Output-Voltage Swing VT Short-Circuit Current ISC Output Leakage Current IZ Rise or Fall Time Transmitter Input to Output Delay RL = 3.9kΩ (out high) 4 6 RL = 3.9kΩ (out low) -6 -4 RL = 450Ω (out high) 3.6 RL = 450Ω (out low) -3.6 RL = 450Ω 0.9 x |VO| VO = GND -55 -0.25V ≤ VOUT ≤ +0.25V, power-off or no-cable mode ±0.05 V V +55 mA +5 µA tr, tf RL = 450Ω, CL = 100pF, Figure 8 2 µs tPLH, tPHL RL = 450Ω, CL = 100pF, Figure 8 1 µs V.10 RECEIVER (R2, R4, R5) Input Threshold Voltage VTH Input Hysteresis ∆VTH 50 25 Receiver Input Current IIN -10V ≤ VA ≤ +10V -0.66 Receiver Input Resistance RIN -10V ≤ VA ≤ +10V 15 Rise or Fall Time Receiver Input to Output Delay Data Skew 250 mV +0.66 mA 30 kΩ ns tr, tf Figures 5, 9 3 tPLH Figure 9 55 tPHL Figure 9 109 Figures 5, 9 (Note 3) 60 |tPHL - tPLH| mV ns ns V.28 TRANSMITTER (All CHANNELS) Output-Voltage Swing Short-Circuit Current Output Leakage Current |VOD| Open circuit RL = 3kΩ 7.1 5 6 IOH IZ -0.25V ≤ VOUT ≤ +0.25V, power-off or no-cable mode ±0.05 V 90 mA ±5 µA _______________________________________________________________________________________ 7 MAX13171E/MAX13173E/MAX13175E MAX13173E ELECTRICAL CHARACTERISTICS (continued) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset MAX13173E ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF, Figure 15, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER Output Slew Rate Transmitter Input to Output Delay SYMBOL CONDITIONS SRR/F RL = 3kΩ, CL = 2500pF (swing in ±3V) Figures 4, 10 tPHL, tPLH RL = 3kΩ, CL = 2500pF, Figures 4, 10 MIN TYP 4 1 MAX UNITS 30 V/µs 2 µs 2 V V.28 RECEIVER (All CHANNELS) Input Threshold Low VIL Input Threshold High VIH 1.2 VHYST 0.25 Input Hysteresis 0.8 Input Resistance RIN -15V ≤ VIN ≤ +15V Rise or Fall Time tr, tf Figures 5, 11 tPHL, tPLH Figures 5, 11 Receiver Input to Output Delay 3 1.2 5 V V 7 3 kΩ ns 150 ns ESD PROTECTION T_OUT, T_OUT/R_IN_, R_IN Human Body Model ±15 Air Gap Discharge IEC 61000-4-2 Contact Discharge ±15 kV ±5 MAX13175E ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF, Figure 15, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER VCC Operating Range VL Operating Range SYMBOL MAX UNITS VCC CONDITIONS 3.135 MIN TYP 5.5 V VL 1.62 VCC V VDD Operating Range VDD 4.5 7.1 V VEE Operating Range VEE -7.1 -4 V VL POR Rising Threshold VCC POR Rising Threshold VDD Supply Current VCC Supply Current 0.7 1.06 1.46 V 1 1.88 2.75 V IDD All inputs connected to GND or VL, except no-cable mode 0.05 0.25 mA ICC All inputs connected to GND or VL, except no-cable mode 2.15 5.9 mA 1.29 2.6 mA +1 µA ICC_NOCAB VEE = 0V, M[x] = 1111 (Note 5) VL Supply Current IL All inputs connected to GND or VL -1 VEE Supply Current IEE All inputs connected to GND or VL -3.5 -1 mA TERMINATOR INPUTS Differential-Mode Impedance V.35 Mode -2V ≤ VCM ≤ +2V, all channels, Figure 12 90 104 110 Ω Common-Mode Impedance V.35 Mode -2V ≤ VCM ≤ +2V, all channels, Figure 13 135 153 165 Ω 8 _______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset (VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1µF, C3 = C4 = C5 = 4.7µF, Figure 15, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS -7V ≤ VCM ≤ +7V, all channels, except nocable mode, Figure 12 Differential-Mode Impedance V.11 Mode MIN TYP MAX 100 104 110 UNITS Ω -7V ≤ VCM ≤ +7V, no cable, VEE = 0V, VAB < 2V, Figure 12 115 Differential Path Enable Time 50 µs Differential Path Disable Time 300 µs Common-Mode Path Enable Time 12 µs Common-Mode Path Disable Time 2 µs High-Impedance Leakage Current IZ -15V ≤ VR_A ≤ +15V -50 +50 µA LOGIC INPUTS (M0, M1, M2, LATCH, DCE/DTE) Input High Voltage VIH Input Low Voltage VIL Logic Input Current IIN 0.66 x VL V 0.33 x VL VIN = GND or VL -1 +1 V µA ESD PROTECTION Human Body Model ±15 R_A, R_B to GND Air Gap Discharge IEC 61000-4-2 ±10 Contact Discharge IEC 61000-4-2 ±6 All Other Pins Human Body Model ±2 kV kV Note 2: All devices are 100% production tested at TA = +85°C for the MAX13171E/MAX13173E and TA = +25°C for the MAX13175E. Specifications over temperature are guaranteed by design. Note 3: Guaranteed by design, not production tested. Note 4: Output-to-output skews are evaluated as difference of propagation delays between different channels in the same condition and for the same polarity (LH or HL). Note 5: M[x] is the input bus DTE/DCE, M2, M1, M0. _______________________________________________________________________________________ 9 MAX13171E/MAX13173E/MAX13175E MAX13175E ELECTRICAL CHARACTERISTICS (continued) MAX13171E Typical Operating Characteristics (VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) V.28 SUPPLY CURRENT vs. DATA RATE 150 100 MAX13171E toc02 30 0 0.1 10 200 150 100 0 0 10,000 1000 250 50 10 0 50 100 150 250 200 0.1 10 10,000 1000 DATA RATE (kbps) DATA RATE (kbps) DATA RATE (kbps) V.11 DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE V.28 OUTPUT VOLTAGE vs. TEMPERATURE V.35 OUTPUT VOLTAGE vs. TEMPERATURE DC OUTPUT DCE MODE, R = 50Ω -1 2 DC OUTPUT DCE MODE, RL = 3kΩ -2 400 MAX13171E toc06 VOUT+ 4 0 600 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1 0 6 MAX13171E toc05 VOUT+ 2 8 MAX13171E toc04 3 VOH 200 DC OUTPUT DCE MODE, VCM = 0V, FULL LOAD 0 -200 -4 -2 VOUT- VOUT- -3 -600 -8 -40 -15 10 35 60 85 VOL -400 -6 -40 -15 10 35 60 -40 85 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) V.35 LOADED DIFFERENTIAL OUTPUT VOLTAGE vs. COMMON-MODE VOLTAGE V.11/V.35 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE V.28 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE DC OUTPUT 550 |VOD| 545 540 535 530 DC OUTPUT DTE MODE R1INA 300 INPUT CURRENT (µA) 555 400 200 100 0 R2INA, R3INA -100 -200 -2 0 2 COMMON-MODE VOLTAGE (V) 4 2.0 DC OUTPUT DTE MODE 1.5 1.0 0.5 0 -0.5 -1.0 -300 -1.5 -400 -2.0 -2.5 -500 -4 2.5 MAX13171E toc09 500 MAX13171E toc07 560 INPUT CURRENT (mA) DIFFERENTIAL OUTPUT VOLTAGE (V) 40 20 50 10 50 DCE MODE, FULLY LOADED, ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE 300 SUPPLY CURRENT (mA) 200 60 350 MAX13171E toc08 SUPPLY CURRENT (mA) 250 DCE MODE, ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE, RL = 3kΩ, CL = 2500pF 70 SUPPLY CURRENT (mA) DCE MODE, R = 50Ω, ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE 300 80 MAX13171E toc01 350 V.35 SUPPLY CURRENT vs. DATA RATE MAX13171E toc03 RS-530 SUPPLY CURRENT vs. DATA RATE DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset -10 -8 -6 -4 -2 0 2 4 INPUT VOLTAGE (V) 6 8 10 -10 -8 -6 -4 -2 0 2 4 INPUT VOLTAGE (V) ______________________________________________________________________________________ 6 8 10 Multiprotocol, Pin-Selectable Data Interface Chipset V.28 LOOPBACK OPERATION (250kbps) V.11 LOOPBACK OPERATION (40Mbps) MAX13171E toc11 MAX13171E toc10 RL = 3kΩ, CL = 2500pF R = 50Ω T_IN 2V/div T_IN 2V/div T_OUT_/R_IN_ 2V/div T_OUT_/R_IN_ 5V/div R_OUT 2V/div R_OUT 2V/div 10ns/div 1µs/div V.35 LOOPBACK OPERATION (40Mbps) V.28 SLEW RATE vs. LOAD CAPACITANCE MAX13171E toc12 MAX13171E toc13 35 RL = 3kΩ FULL LOAD 30 SLEW RATE (V/µs) T_IN 2V/div T_OUT_/R_IN_ 0.5V/div 25 20 SRF 15 SRR 10 R_OUT 2V/div 5 0 0 1µs/div 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) 14 12 10 8 6 tPHL 15 10 5 4 25 MAX13171E toc16 20 30 PROPAGATION DELAY (ns) tPLH tPLH MAX13171E toc15 PROPAGATION DELAY (ns) 16 25 PROPAGATION DELAY (ns) tPHL 18 MAX13171E toc14 20 V.35 TRANSMITTER PROPAGATION DELAY vs. TEMPERATURE V.11 TRANSMITTER PROPAGATION DELAY vs. TEMPERATURE V.11/V.35 RECEIVER PROPAGATION DELAY vs. TEMPERATURE tPHL 20 tPLH 15 10 5 2 0 0 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) ______________________________________________________________________________________ 11 MAX13171E/MAX13173E/MAX13175E MAX13171E Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) MAX13173E Typical Operating Characteristics (VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) 150 FULL LOAD, R = 50Ω 60 50 NO LOAD 40 30 DCE MODE, INVERT = 1 ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE 20 50 NO LOAD, R = 1.95kΩ 10 0 1 1000 -1 0 -3 50 100 150 200 MAX13171E toc20 VOUT+ 2 RL = 450Ω -2 VOUT- 6 -4 2 DC OUTPUT DCE MODE, RL = 3kΩ 0 -2 VOUT- -8 -15 -40 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) V.11 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE V.28 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE DC OUTPUT DCE MODE 200 R2INA 0 -100 -200 85 2 1 0 -1 -2 R1INA -300 DC OUTPUT 3 INPUT CURRENT (mA) 300 R3INA 4 MAX13171E toc22 500 INPUT CURRENT (µV) VOUT+ 4 -6 -8 100 60 -4 RL = 3.9kΩ -6 400 35 8 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4 10 TEMPERATURE (°C) V.28 OUTPUT VOLTAGE vs. TEMPERATURE RL = 3.9kΩ 0 -15 -40 250 DATA RATE (kbps) 8 DC OUTPUT DCE MODE VOUT- -2 -4 100,000 V.10 OUTPUT VOLTAGE vs. TEMPERATURE 6 DC OUTPUT DCE MODE, INVERT = 1, R = 50Ω 0 MAX13171E toc21 10 DATA RATE (kbps) -3 -400 -500 -4 -10 -8 -6 -4 -2 0 2 4 INPUT VOLTAGE (V) 12 2 0 0 VOUT+ 3 MAX13171E toc23 100 FULL LOAD, RL = 50Ω, CL = 2500pF 70 4 DIFFERENTIAL OUTPUT VOLTAGE (V) 80 SUPPLY CURRENT (mA) DCE MODE, INVERT = 1 3 TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE IN V.11 MODE MAX13171E toc18 90 MAX13171E toc17 250 200 V.11 DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE V.28 SUPPLY CURRENT vs. DATA RATE MAX13171E toc19 R-530 SUPPLY CURRENT vs. DATA RATE SUPPLY CURRENT (mA) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset 6 8 10 -15 -10 -5 0 5 INPUT VOLTAGE (V) ______________________________________________________________________________________ 10 15 85 Multiprotocol, Pin-Selectable Data Interface Chipset V.28 SLEW RATE vs. LOAD CAPACITANCE V.10 TRANSMITTER RISE/FALL TIME vs. LOAD CAPACITANCE 1.8 1.6 RISE/FALL TIME (µs) 25 20 SRF 15 SRR 10 FULL LOAD T_IN 2V/div FALL 1.4 1.2 T_OUT_/R_IN_ 2V/div RISE 1.0 0.8 0.6 R_OUT 2V/div 0.4 5 0.2 0 0 0 1000 2000 4000 3000 5000 0 LOAD CAPACITANCE (pF) 1000 2000 3000 4000 5000 10ns/div LOAD CAPACITANCE (pF) V.28 LOOPBACK OPERATION (250kbps) V.10 LOOPBACK OPERATION (100kbps) MAX13171E toc27 MAX13171E toc28 RL = 3kΩ, CL = 2500pF T_IN 2V/div T_IN 2V/div RL = 3.9kΩ T_OUT_/R_IN_ 5V/div T_OUT_/R_IN_ 5V/div RL = 450Ω R_OUT 2V/div R_OUT 2V/div 1µs/div 4µs/div V.11 RECEIVER PROPAGATION DELAY vs. TEMPERATURE V.11 TRANSMITTER PROPAGATION DELAY vs. TEMPERATURE tPLH 15 10 5 20 MAX13171E toc30 tPHL 20 25 PROPAGATION DELAY (ns) MAX13171E toc29 25 PROPAGATION DELAY (ns) SLEW RATE (V/µs) 30 MAX13171E toc26 MAX13171E toc25 RL = 3kΩ V.11 LOOPBACK OPERATION (40Mbps) 2.0 MAX13171E toc24 35 tPHL tPLH 15 10 5 0 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) ______________________________________________________________________________________ 13 MAX13171E/MAX13173E/MAX13175E MAX13173E Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) MAX13175E Typical Operating Characteristics (VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) 107 VCM = 0V VCM = +7V 106 105 104 103 110 107 106 105 104 109 108 107 106 105 104 103 103 102 102 101 101 101 100 100 VCM = -7V 102 -40 -15 10 35 60 85 -5 -3 -1 1 3 5 100 7 3.0 3.5 4.0 4.5 5.0 5.5 TEMPERATURE (NC) VCM (V) VCC (V) V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. SUPPLY VOLTAGE (VEE) V.35 COMMON-MODE IMPEDANCE vs. TEMPERATURE V.35 COMMON-MODE IMPEDANCE vs. COMMON-MODE VOLTAGE (VCM) IMPEDANCE (I) 107 160 106 105 104 103 102 150 VCM = -2V 145 -7 -5 -6 VEE (V) -4 135 175 170 165 160 155 150 145 140 101 180 VCM = +2V 155 MAX13175E toc36 108 185 IMPEDANCE (I) 109 MAX13175E toc35 165 MAX13175E toc34 110 100 -7 V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. SUPPLY VOLTAGE (VCC) MAX13175E toc33 108 IMPEDANCE (I) IMPEDANCE (I) 108 109 IMPEDANCE (I) 109 14 110 MAX13175E toc31 110 V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. COMMON-MODE VOLTAGE (VCM) MAX13175E toc32 V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. TEMPERATURE IMPEDANCE (I) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset 140 -40 -15 10 35 TEMPERATURE (NC) 60 85 135 -2 -1 0 VCM (V) ______________________________________________________________________________________ 1 2 Multiprotocol, Pin-Selectable Data Interface Chipset VCM = -2V 150 VCM = -2V 145 140 140 3.5 4.0 4.5 5.5 5.0 135 MAX13175E toc39 700 600 500 400 ICC 300 IEE 200 -7 -5 -6 0 -4 -40 VEE (V) VCC (V) 80 60 40 35 60 85 V.11 OR V.35 DIFFERENTIAL IMPEDANCE PHASE vs. FREQUENCY 15 10 5 PHASE (DEGREES) 100 10 TEMPERATURE (NC) V.11 OR V.35 DIFFERENTIAL IMPEDANCE MAGNITUDE vs. FREQUENCY 120 -15 M AX13175E toc41 3.0 800 100 M AX13175E toc40 135 VCM = +2V 155 HI-Z MODE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (FA) 150 145 160 IMPEDANCE (I) VCM = +2V IM PEDANCE (I ) IMPEDANCE (I) 160 155 165 MAX13175E toc37 165 V.35 COMMON-MODE IMPEDANCE vs. SUPPLY VOLTAGE (VEE) MAX13175E toc38 V.35 COMMON-MODE IMPEDANCE vs. SUPPLY VOLTAGE 0 -5 -10 -15 -20 -25 20 -30 -35 0 0.1 1 10 FREQUENCY (MHz) 100 0.1 1 10 100 FREQUENCY (MHz) ______________________________________________________________________________________ 15 MAX13171E/MAX13173E/MAX13175E MAX13175E Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +1.8V, TA = +25°C, unless otherwise noted.) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E Pin Description PIN NAME 1, 2, 6, 30, 31 N.C. No Connection. Not internally connected. 3, 16 VCC Device Supply Voltage. Bypass VCC with a 4.7µF capacitor to ground as close as possible to pin 3. 4 T1IN Transmitter 1 Logic Input 5 T2IN Transmitter 2 Logic Input 7 T3IN Transmitter 3 Logic Input 8 R1OUT 9 R2OUT Receiver 2 Logic Output with Internal Pullup to VL 10 R3OUT Receiver 3 Logic Output with Internal Pullup to VL 11 M0 Mode-Select 0 Input with Internal Pullup to VL 12 VL Logic-Supply Reference Input. VL determines the voltage level of the logic interface. Bypass VL with a 0.1µF capacitor to ground as close as possible to the device. 13 M1 Mode-Select 1 Input with Internal Pullup to VL 14 M2 Mode-Select 2 Input with Internal Pullup to VL 15 DCE/DTE 17 R3INB 18 R3INA 19, 24, 29, 35 GND 20 R2INB Receiver 2 Noninverting Input 21 R2INA Receiver 2 Inverting Input 22 T3OUTB/R1INB 23 T3OUTA/R1INA 25 T2OUTB Transmitter 2 Noninverting Output 26 T2OUTA Transmitter 2 Inverting Output 27 T1OUTB Transmitter 1 Noninverting Output 28 T1OUTA Transmitter 1 Inverting Output 32 VEE Charge-Pump Negative Supply Output. Connect a 4.7µF ceramic capacitor from VEE to ground as close as possible to the device. 33 C2- VEE Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-. 34 C2+ VEE Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-. 36 C1- VDD Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-. 37 C1+ VDD Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-. 38 VDD Charge-Pump Positive-Supply Output. Connect a 4.7µF ceramic capacitor from VDD to ground as close as possible to the device. — EP Exposed Pad. Internally connected to VEE. Connect to a large VEE plane to maximize thermal performance. Not intended as an electrical connection point. Do not share the same plane as the MAX13173E. 16 FUNCTION Receiver 1 Logic Output with Internal Pullup to VL DCE/DTE Mode-Select Input with Internal Pullup to VL Receiver 3 Noninverting Input Receiver 3 Inverting Input Ground Transmitter 3 Noninverting Output/Receiver 1 Noninverting Input Transmitter 3 Inverting Output/Receiver 1 Inverting Input ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset PIN NAME FUNCTION 1 T1IN Transmitter 1 Logic Input 2 VCC Device Supply Voltage. Bypass VCC with a 4.7µF capacitor to ground as close as possible to the device. 3 T2IN Transmitter 2 Logic Input 4 T3IN Transmitter 3 Logic Input 5 VL 6 R1OUT Receiver 1 Logic Output with Internal Pullup to VL 7 R2OUT Receiver 2 Logic Output with Internal Pullup to VL 8 R3OUT Receiver 3 Logic Output with Internal Pullup to VL 9 R5OUT/T5IN Receiver 5 Logic Output/Transmitter 5 Logic Input Logic-Supply Reference Input. VL determines the voltage level of the logic interface. Bypass VL with a 0.1µF capacitor to ground, as close as possible to the device. 10 T4IN 11 R4OUT 12 M0 Mode-Select 0 Input with Internal Pullup to VL 13 M1 Mode-Select 1 Input with Internal Pullup to VL 14 M2 Mode-Select 2 Input with Internal Pullup to VL 15 DCE/DTE 16 INVERT 17 Transmitter 4 Logic Input Receiver 4 Logic Output DCE/DTE Mode-Select Input with Internal Pullup to VL T4/R4 and T5/R5 Select Input with Internal Pullup to VL. INVERT reverses the action of DCE/DTE for channels 4 and 5. T4OUTA/R4INA Transmitter 4 Inverting Output/Receiver 4 Inverting Input 18, 25, 31, 35 GND 19 R3INB Receiver 3 Noninverting Input Ground 20 R3INA Receiver 3 Inverting Input 21 R2INB Receiver 2 Noninverting Input 22 R2INA Receiver 2 Inverting Input 23 T3OUTB/R1INB Transmitter 3 Noninverting Output/Receiver 1 Noninverting Input 24 T3OUTA/R1INA Transmitter 3 Inverting Output/Receiver 1 Inverting Input 26 T2OUTB Transmitter 2 Noninverting Output 27 T2OUTA Transmitter 2 Inverting Output 28 T1OUTB Transmitter 1 Noninverting Output 29 T1OUTA Transmitter 1 Inverting Output 30 T5OUTA/R5INA Transmitter 5 Inverting Output/Receiver 5 Inverting Input 32 VEE Charge-Pump Negative-Supply Output. Connect a 4.7µF ceramic capacitor from VEE to ground as close as possible to the device. 33 C2- VEE Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-. 34 C2+ VEE Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1µF ceramic capacitor between C2+ and C2-. 36 C1- VDD Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-. ______________________________________________________________________________________ 17 MAX13171E/MAX13173E/MAX13175E MAX13173E Pin Description Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E MAX13173E Pin Description (continued) PIN NAME FUNCTION 37 C1+ VDD Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1µF ceramic capacitor between C1+ and C1-. 38 VDD Charge-Pump Positive-Supply Output. Connect a 4.7µF ceramic capacitor from VDD to ground as close as possible to the device. — EP Exposed Pad. Internally connected to VEE. Connect to a large VEE plane to maximize thermal performance, not intended as an electrical connection point. Does not share the same plane as the MAX13171E. MAX13175E Pin Description 18 PIN NAME FUNCTION 1, 38 R1B Load 1, Node B 2, 3 R1A Load 1, Node A 4, 5 R2A Load 2, Node A 6, 7 R2B Lode 2, Node B 8 R2C Lode 2, Center Tap 9, 10 R3A Load 3, Node A 11, 12 R3B Lode 3, Node B 13, 18 GND Ground 14 R3C 15 VL Logic-Supply Reference Input. VL determines the voltage level of the logic interface. 16 VEE Negative Supply Voltage. Bypass VEE to GND with a 0.1µF capacitor. Connect to VEE from the MAX13173E. 17 VDD Positive Supply Voltage. Bypass VDD to GND with a 0.1µF capacitor. Connect to VDD from the MAX13173E. 19 VCC Supply Voltage. Bypass VCC to GND with a 0.1µF capacitor as close as possible to the device. 20, 21 R4B Load 4, Node B 22, 23 R4A Load 4, Node A 24, 25 R5B Load 5, Node B 26, 27 R5A Load 5, Node A 28, 29 R6A Load 6, Node A 30, 31 R6B Load 6, Node B 32 DCE/DTE Lode 3, Center Tap DCE/DTE Mode-Select Input Latch Signal Input. When LATCH is low, the input latches are transparent. When LATCH is high, the data at the mode-select inputs are latched. 33 LATCH 34 M2 Mode-Select Input 2 35 M1 Mode-Select Input 1 36 M0 Mode-Select Input 0 37 R1C Load 1, Center Tap — EP Exposed Pad. Internally connected to VEE. Connect to a large VEE plane to maximize thermal performance, not intended as an electrical connection point. If VEE is powered from the MAX13173E’s VEE, planes can be shared. ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset A 100pF T R B B A VOD R 100Ω A 15pF VOC R 100pF B Figure 1. V.11 DC Test Circuit Figure 2. V.11 AC Test Circuit 50Ω T B 50Ω 125Ω VCM 125Ω B VOD R A 50Ω A 50Ω 15pF Figure 3. V.35 Transmitter/Receiver Test Circuit T A T VO CL Figure 4. V.10/V.28 Transmitter Test Circuit A R RL 15pF Figure 5. V.10/V.28 Receiver Test Circuit ______________________________________________________________________________________ 19 MAX13171E/MAX13173E/MAX13175E Test Circuits MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset Timing Diagrams VL TIN_ f = 1MHz: tr, tf ≤ 1ns VL/2 0V VL/2 tPHL tPLH V0 B-A 90% 90% 10% 50% -V0 50% tF tR Figure 6. V.11 Transmitter Propagation Delays +1V f = 1MHz: tr, tf ≤ 1ns 0 B-A INPUT 0 -1V tPLH tPHL V0H 90% VL/2 R V0L 90% OUTPUT 10% VL/2 10% tF tR Figure 7. V.11 Receiver Propagation Delays VL tR, tF ≤ 10ns VL/2 TIN_ 0V VL/2 tPHL V0H tPLH 90% 90% 0 0 A 10% 10% -V0L tR tF Figure 8. V.10 Transmitter Propagation Delay VIH A VIL tR, tF ≤ 10ns 0 tPLH tPHL V0H R V0L 0 90% VL/2 10% tF 90% 10% VL/2 tR Figure 9. V.10 Receiver Propagation Delay 20 ______________________________________________________________________________________ 10% Multiprotocol, Pin-Selectable Data Interface Chipset VL tR, tF ≤ 10ns VL/2 TIN_ 0V VL/2 tPHL V0H tPLH 3V 3V 0 0 A -3V -3V -V0L SRF = 6/tF tF tR SRR = 6/tR Figure 10. V.28 Transmitter Propagation Delay (2.0V) VIH A (0.8V) VIL tR, tF ≤ 10ns 1.3V 1.3V tPLH tPHL V0H R V0L 90% VL/2 90% 10% 10% VL/2 tR tF Figure 11. V.28 Receiver Propagation Delay A A I R1 = 52Ω R1 = 52Ω AMMETER S1 ON S1 ON R3 = 127Ω R3 = 127Ω S2 OFF AMMETER VDM = ±2V S2 ON R2 = 52Ω I R2 = 52Ω VCM = ±2V B VCM = ±7V OR ±2V V RDM = DM I Figure 12. V.11 or V.35 Differential Impedance Measurement V RCM = CM I B Figure 13. V.35 Common-Mode Impedance Measurement ______________________________________________________________________________________ 21 MAX13171E/MAX13173E/MAX13175E Timing Diagrams (continued) MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset VCC VL R1C R2C R3C VDD VEE EP MAX13175E LATCH VEE DCE/DTE M2 M1 M0 GND R1A R1B R2A R2B R3A R3B R4A R4B R5A R5B R6A R6B Figure 14. MAX13175E Block Diagram Detailed Description The MAX13171E/MAX13173E/MAX13175E form a complete pin-selectable DTE or DCE interface port that supports the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry serial-interface control signaling. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network, or by a discrete termination network. The MAX13171E/MAX13173E feature a low supply current, no-cable mode, true fail-safe operation, and thermal-shutdown circuitry. Thermal shutdown protects the drivers against excessive power dissipation. When activated, the thermal-shutdown circuitry places the driver and receiver outputs into a highimpedance state. The MAX13171E is a three-driver/three-receiver, multiprotocol transceiver that operates from a single +3.135V to +5.5V supply. The MAX13173E is a five-driver/five-receiver multiprotocol transceiver that operates from a single +3.135V to +5.5V supply. The MAX13175E contains six pin-selectable multiprotocol cable termination networks (Figure 14). Each network is capable of terminating V.11 (RS-422, RS-530, RS-530A, RS-449, V.36 and X.21) with a 100Ω differential load, V.35 with a T-network load, or V.28 (RS-232) and V.10 (RS-423) with an open-circuit load for use with transceivers having on-chip termination. The terminations and protocols are pin selectable. The MAX13175E replaces discrete resistor termination networks and 22 expensive relays required for multiprotocol termination, saving space and cost. Dual Charge-Pump Voltage Converter The MAX13171E/MAX13173E have internal-regulated dual charge pumps that provide positive and negative output voltages from a single supply. The charge pump operates in discontinuous mode. If the output voltage is less than the regulated voltage, the charge pump is enabled. If the output voltage exceeds the regulated voltage, the charge pump is disabled. Each charge pump requires flying capacitors (C1, C2), and reservoir capacitors (C3, C5), to generate the VDD and VEE supplies. Figure 15 shows the charge-pump connections. MAX13171E MAX13173E C3 4.7µF VDD C2+ C1+ C2- C1- VEE C2 1µF C1 1µF +3.135V TO +5.5V C5 4.7µF VCC GND C4 4.7µF Figure 15. Charge Pump ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset Mode Selection The mode-select inputs M0, M1, and M2 determine which interface protocol is selected (Table 1 for the MAX13171E, Table 2 for the MAX13173E). The state of the DCE/DTE input determines whether the transceivers are configured as a DTE serial port or a DCE serial port. The INVERT input on the MAX13173E changes the DCE/DTE functionality regarding T4/T5 and R4/R5 only. M0, M1, M2, INVERT, and DCE/DTE are internally pulled up to VL to ensure logic-high if left unconnected. If the M0, M1, and M2 mode inputs are all unconnected, the MAX13171E/MAX13173E enter no-cable mode. The MAX13175E mode select inputs and DCE/DTE input do not have an internal pullup to VL. They are pulled logic-high if their mode-select inputs are tied to the MAX13171E/MAX13173E’s mode select inputs. Termination Modes The termination networks in the MAX13175E can be set to one of three modes, V.11, V.35, or high impedance. Table 1. MAX13171E Mode Selection MAX13171E MODE NAME M2 M1 M0 DCE/ DTE T1 T2 T3 R1 R2 R3 Not Used (Default V.11) RS-530A 0 0 0 0 V.11 V.11 Z V.11 V.11 V.11 0 0 1 0 V.11 V.11 Z V.11 V.11 V.11 RS-530 0 1 0 0 V.11 V.11 Z V.11 V.11 V.11 X.21 0 1 1 0 V.11 V.11 Z V.11 V.11 V.11 V.35 1 0 0 0 V.35 V.35 Z V.35 V.35 V.35 RS-449/V.36 1 0 1 0 V.11 V.11 Z V.11 V.11 V.11 V.28/RS-232 1 1 0 0 V.28 V.28 Z V.28 V.28 V.28 No Cable 1 1 1 0 Z Z Z Z Z Z Not Used (Default V.11) 0 0 0 1 V.11 V.11 V.11 Z V.11 V.11 RS-530A 0 0 1 1 V.11 V.11 V.11 Z V.11 V.11 RS-530 0 1 0 1 V.11 V.11 V.11 Z V.11 V.11 X.21 0 1 1 1 V.11 V.11 V.11 Z V.11 V.11 V.35 1 0 0 1 V.35 V.35 V.35 Z V.35 V.35 RS-449/V.36 1 0 1 1 V.11 V.11 V.11 Z V.11 V.11 V.28/RS-232 1 1 0 1 V.28 V.28 V.28 Z V.28 V.28 No Cable 1 1 1 1 Z Z Z Z Z Z ______________________________________________________________________________________ 23 MAX13171E/MAX13173E/MAX13175E Fail-Safe The MAX13171E/MAX13173E guarantee a logic-high receiver output when the receiver inputs are shorted, or when they are connected to a terminated transmission line with all drivers disabled by setting the receiver threshold between -50mV and -200mV in the V.11 and V.35 modes. If the differential receiver input voltage (B A) is ≥ -50mV, R_OUT is logic-high. If (B - A) is ≤ -200mV, R_OUT is logic-low. In the case of a terminated bus with all transmitters disabled, the receiver’s differential input voltage is pulled to zero by the termination. This results in a logic-high with a 50mV minimum noise margin. The V.10 receiver threshold is set between 50mV and 250mV. If the V.10 receiver input voltage is less than or equal to 50mV, R_OUT is logic-high. The V.28 receiver threshold is set between 0.8V and 2.0V. If the receiver input voltage is less than or equal to 0.8V, R_OUT is logic-high. In the case of a terminated bus with transmitters disabled, the receiver’s input voltage is pulled to GND by the termination. MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset Table 2. MAX13173E Mode Selection PROTOCOL M2 M1 M0 DCE/ DTE INVERT T1 T2 T3 R1 R2 R3 T4 R4 T5 R5 Not Used (Default V.11) 0 0 0 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10 Z V.10 RS-530A 0 0 1 0 0 V.11 V.10 Z V.11 V.10 V.11 Z V.10 Z V.10 RS-530 0 1 0 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10 Z V.10 X.21 0 1 1 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10 Z V.10 V.35 1 0 0 0 0 V.28 V.28 Z V.28 V.28 V.28 Z V.28 Z V.28 RS-449/V.36 1 0 1 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10 Z V.10 V.28/RS-232 1 1 0 0 0 V.28 V.28 Z V.28 V.28 V.28 Z V.28 Z V.28 No Cable 1 1 1 0 0 Z Z Z Z Z Z Z Z Z Z Not Used (Default V.11) 0 0 0 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z V.10 Z RS-530A 0 0 1 0 1 V.11 V.10 Z V.11 V.10 V.11 V.10 Z V.10 Z RS-530 0 1 0 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z V.10 Z X.21 0 1 1 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z V.10 Z V.35 1 0 0 0 1 V.28 V.28 Z V.28 V.28 V.28 V.28 Z V.28 Z RS-449/V.36 1 0 1 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z V.10 Z V.28/RS-232 1 1 0 0 1 V.28 V.28 Z V.28 V.28 V.28 V.28 Z V.28 Z No Cable 1 1 1 0 1 Z Z Z Z Z Z Z Z Z Z Not Used (Default V.11) 0 0 0 1 0 V.11 V.11 V.11 Z V.11 V.11 V.10 Z V.10 Z RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable Not Used (Default V.11) RS-530A 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 V.11 V.11 V.11 V.28 V.11 V.28 Z V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.28 V.11 V.28 Z Z Z Z Z Z Z Z V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.28 V.11 V.28 Z V.10 V.10 V.10 V.28 V.10 V.28 Z Z Z Z Z Z Z Z V.10 V.10 V.10 V.28 V.10 V.28 Z Z Z Z Z Z Z V.10 0 0 0 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10 Z V.10 0 0 1 1 1 V.11 V.10 V.11 Z V.10 V.11 Z V.10 Z V.10 RS-530 0 1 0 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10 Z V.10 X.21 0 1 1 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10 Z V.10 V.35 1 0 0 1 1 V.28 V.28 V.28 Z V.28 V.28 Z V.28 Z V.28 RS-449/V.36 1 0 1 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10 Z V.10 V.28/RS-232 1 1 0 1 1 V.28 V.28 V.28 Z V.28 V.28 Z V.28 Z V.28 No Cable 1 1 1 1 1 Z Z Z Z Z Z Z Z Z Z 24 ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset The state of the MAX13175E’s mode-select inputs, M0, M1, M2, and DCE/DTE determines the mode of each of the six termination networks. Table 3 shows a cross-reference of termination mode and select input state for each of the six termination networks within the MAX13175E. A A A MAX13175E MAX13175E R1 52Ω R1 52Ω S1 CLOSED S1 CLOSED MAX13175E R1 52Ω S1 OPEN C C S2 OPEN S2 CLOSED R3 127Ω R2 52Ω C S2 OPEN R3 127Ω R2 52Ω R2 52Ω B B R3 127Ω B (a) V.11 (b) V.35 (c) Z Figure 16. Termination Modes Table 3. MAX13175E Termination Mode Selection PROTOCOL V.10/RS-423 RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable V.10/RS-423 RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable DCE/DTE M2 M1 M0 R1 R2 R3 R4 R5 R6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z Z Z Z V.35 Z Z V.11 Z Z Z Z V.35 Z Z V.11 Z Z Z Z V.35 Z Z V.11 Z Z Z Z V.35 Z Z V.11 Z Z Z Z Z Z Z V.11 Z Z Z Z V.35 Z Z V.11 Z V.11 V.11 V.11 V.35 V.11 Z V.11 Z Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.35 V.11 Z V.11 Z V.11 V.11 V.11 V.35 V.11 Z V.11 Z V.11 V.11 V.11 V.35 V.11 Z V.11 Z V.11 V.11 V.11 V.35 V.11 Z V.11 ______________________________________________________________________________________ 25 MAX13171E/MAX13173E/MAX13175E As shown in Figure 16, in V.11 mode, switch S1 is closed and switch S2 is open, presenting 104Ω across terminals A and B. In V.35 mode, switches S1 and S2 are both closed, presenting a T-network with 104Ω differential impedance and 153Ω common-mode impedance. In high-impedance mode, switches S1 and S2 are both open, presenting a high impedance across terminals A and B suitable for V.28 and V.10 modes. MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset No-Cable Mode The MAX13171E/MAX13173E enter no-cable mode when the mode-select inputs are left unconnected or connected high (M0 = M1 = M2 = 1). The receiver outputs enter a high-impedance state in no-cable mode, allowing these output lines to be shared with other receiver outputs (the receiver outputs have an internal pullup resistor to pull the outputs high if not driven). Also, in no-cable mode, the transmitter outputs enter a high-impedance state, so these output lines can be shared with other devices. The MAX13175E enters no-cable mode when the mode select inputs, M0, M1, and M2 are connected high. In no-cable mode, all six termination networks are placed in V.11 mode, with S1 closed and S2 open. VL Logic Supply The MAX13171E/MAX13173E/MAX13175E include a VL logic supply that allows user-defined interface logicvoltage levels referenced to VL. VL can go down to +1.62V and up to VCC. All logic inputs and outputs are referred to VL. Data Rate The MAX13171E/MAX13173E/MAX13175E support a maximum data rate of 40Mbps in RS-449/V.36, RS-530, RS-530A, X.21, V.35 if only one of the MAX13171E high-speed transceivers is operated at the maximum data rate. If two high-speed transceivers operate simultaneously, the maximum data rate is 20Mbps. Applications Information Capacitor Selection The capacitors used for the charge pumps, as well as for supply bypassing, must have a low equivalent series resistance (ESR), low inductance (ESL), and low temperature coefficient. Multilayer ceramic capacitors with an X7R dielectric offer the best combination of performance, size, and cost. The flying capacitors (C1, C2) should have a value of 1µF, while the bypass capacitor (C4) and reservoir capacitors (C3, C5) should have a 26 minimum value of 4.7µF (Figure 15). To reduce the ripple present on the transmitter outputs, capacitors C3, C4, and C5 can be increased. The values of C1 and C2 should not be increased. Cable Mode-Select Application A cable-selectable multiprotocol interface is shown in Figure 17. The mode control lines M0, M1, and DCE/DTE are wired to the DB-25 connector. To select the serial interface mode, the appropriate combination of M0, M1, and DCE/DTE are grounded within the cable wiring. The control lines that are not grounded are pulled high by the internal pullups on the MAX13171E/MAX13173E. The serial interface protocol of the MAX13171E/ MAX13173E/MAX13175E is selected based on the cable that is connected to the DB-25 interface. V.10 (RS-423) Interface (MAX13173E Only) The V.10 interface (Figure 18) is an unbalanced singleended interface capable of driving a 450Ω load. The V.10 driver generates a minimum VO voltage of ±4V across A’ and C’ when unloaded, and a minimum voltage of 0.9 x V O when loaded with 450Ω. The V.10 receiver has a single-ended input and does not reject common-mode differences between C and C’. The V.10 receiver-input trip threshold is defined between +50mV and +250mV with input impedance characteristic shown in Figure 19. The MAX13173E V.10 mode receiver has a threshold between +50mV and +250mV. To ensure that the receiver has proper fail-safe operation, see the FailSafe section. To aid in rejecting system noise, the MAX13173E V.10 receiver has a typical hysteresis of 25mV. Switch S3 in Figures 20a and 20b is open in V.10 mode to disable the V.28 5kΩ termination at the receiver input. Switch S4 is closed and switch S5 is open to internally ground the receiver B input. ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E 100pF VCC 100pF 100pF VCC C4 4.7µF VL 0.1µF 0.1µF VDD MAX13175E DTE_TXD/DCE_RXD T1IN DTE_SCTE/DCE_RXC T2IN T3IN DTE_TXC/DCE_TXC R1OUT DTE_RXC/DCE_SCTE R2OUT DTE_RXD/DCE_TXD R3OUT VL T1 T2 NC VL DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B DCE RXD A RXD B RXC A RXC B T3 R1 R2 R3 T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB 15 12 17 9 3 16 7 MAX13171E M0 M1 M2 0.1µF R6A R6B 0.1µF T1OUTA T1OUTB T2OUTA T2OUTB R5A R5B VEE R4A R4B C5 4.7µF M0 LATCH VEE R2A R2B R3A R3B C3 4.7µF CHARGE PUMP R1A R1B VDD 0.1µF DCE/DTE M2 M1 C2 1µF C1 1µF 1 TXC A TXC B TXC A TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B SG SHIELD DCE/DTE DB-25 CONNECTOR C4 4.7µF VCC C2 1µF C1 1µF VDD C3 4.7µF CHARGE PUMP 25 VEE C5 4.7µF T1OUTA DTE_RTS/DCE_CTS T1IN DTE_DTR/DCE_DSR T2IN T3IN DTE_DCD/DCE_DCD R1OUT DTE_DSR/DCE_DTR R2OUT DTE_CTS/DCE_RTS R3OUT T4IN T1 T2 4 19 20 23 RTS A RTS B CTS A CTS B DTR A DTR B DSR A DSR B T3 R1 R2 R3 T4 R4OUT R5OUT/T5IN T1OUTB T2OUTA T2OUTB DCE/DTE 21 M1 18 M0 T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B DCD A DCD B DTR A DTR B RTS A RTS B T4OUTA/R4INA R4 T5OUTA/R5INA T5 R5 VL 0.1µF NC MAX13173E M0 M1 M2 DCE/DTE INVERT Figure 17. Cable-Selectable Multiprotocol DCE/DTE Port with DB-25 Connector ______________________________________________________________________________________ 27 MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset UNBALANCED INTERCONNECTING CABLE GENERATOR LOAD CABLE TERMINATION A A′ C C′ RECEIVER Figure 18. Typical V.10/V.28 Interface IZ -10V +3.25mA -3V VZ +10V +3V -3.25mA Figure 19. Receiver Input Impedance Curve A′ A′ A R8 5kΩ A MAX13171E MAX13173E R5 55kΩ R8 5kΩ R6 11kΩ MAX13173E R5 55kΩ RECEIVER S3 R6 11kΩ RECEIVER S3 + 1.4V R7 11kΩ B′ R4 55kΩ B S1 S2 C′ GND Figure 20a. V.10 Internal Resistance Network for Receivers 1, 2, and 3 28 C′ GND Figure 20b. V.10 Internal Resistance Network for Receivers 4 and 5 ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset tem noise, the MAX13171E/MAX13173E V.11 receivers have a typical hysteresis of 15mV. Switch S3 in Figure 23 is open in V.11 mode to disable the V.28 5kΩ termination at the inverting receiver input. Because the control signals are slow (60kbps), 100Ω termination resistance is generally not required for the MAX13173E. For high-speed data transmission, the V.11 specification recommends terminating the cable at the receiver with a 100Ω resistor. This resistor, although not required, prevents reflections from corrupting transmitted data. In Figure 23, the MAX13175E is used to terminate the V.11 receiver. Internal to the MAX13175E, S1 is closed and S2 is open to present a 100Ω minimum differential resistance. The MAX13171E’s internal V.28 termination is disabled by opening S3. BALANCED INTERCONNECTING CABLE GENERATOR IZ LOAD CABLE TERMINATION RECEIVER -3V -10V A′ A +3V 100Ω MIN B B′ C C′ VZ +10V -3.25mA Figure 22. Receiver Input Impedance Figure 21. Typical V.11 Interface A′ A MAX13171E R5 55kΩ R1 52Ω R8 5kΩ MAX13175E S2 R6 11kΩ RECEIVER S3 S1 R3 127Ω + 1.4V R2 52Ω B′ +3.25mA R7 R4 11kΩ 55kΩ B S1 S2 C′ GND Figure 23. V.11 Termination and Internal Resistance Networks ______________________________________________________________________________________ 29 MAX13171E/MAX13173E/MAX13175E V.11 (RS-422) Interface As shown in Figure 21, the V.11 protocol is a fully balanced differential interface. The V.11 driver generates a minimum of ±2V between nodes A and B when a 100Ω (min) resistance is present at the load. The V.11 receiver is sensitive to differential signals of ±200mV at receiver inputs A’ and B’. The V.11 receiver input must comply with the impedance curve of Figure 22 and reject common-mode signals developed across the cable (referenced from C to C’ in Figure 21) of up to ±7V. The MAX13171E/MAX13173E V.11 mode receivers have a differential threshold between -50mV and -200mV to ensure that the receiver has fail-safe operation (see the Fail-Safe section.) To aid in rejecting sys- MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset V.28 (RS-232) Interface The V.28 interface is an unbalanced single-ended interface (Figure 18). The V.28 driver generates a minimum of ±5V across the 3kΩ load impedance between A’ and C’. The V.28 receiver has a single-ended input. The MAX13171E/MAX13173E V.28 mode receivers have a threshold between +0.8V and +2.0V. To aid in rejecting system noise, the MAX13171E/MAX13173E V.28 receivers have a typical hysteresis of 250mV. Switch S3 in Figures 24a and 24b is closed in V.28 mode to enable the 5kΩ V.28 termination at the receiver inputs. V.35 Interface Figure 25 shows a fully-balanced, differential standard V.35 interface. The generator and the load must both present a 100Ω ±10Ω differential impedance and a 150Ω ±15Ω common-mode impedance as shown by the resistive T-networks in Figure 26. The V.35 driver generates a current output (±11mA, typ) that develops an output voltage of ±550mV across the generator and A′ A load termination networks. The V.35 receiver is sensitive to ±200mV differential signals at receiver inputs A’ and B’. The V.35 receiver rejects common-mode signals developed across the cable (referenced from C to C’) of up to ±4V, allowing for error-free reception in noisy environments. In Figure 26, the MAX13175E is used to implement the resistive T-network that is needed to properly terminate the V.35 driver and receiver. Internal to the MAX13175E, S1 and S2 are closed to connect the Tnetwork resistors to the circuit. The V.28 termination resistor (internal to the MAX13171E) is disabled by opening S3 to avoid interference with the T-network impedance. The V.35 specification allows for ±4V of ground difference between the V.35 generator and V.35 load. The MAX13174E maintains correct termination impedance over this condition. A′ R8 5kΩ A MAX13171E MAX13173E R5 55kΩ R8 5kΩ R6 11kΩ MAX13173E R5 55kΩ RECEIVER S3 R6 11kΩ RECEIVER S3 + 1.4V R7 11kΩ B′ R4 55kΩ B S1 S2 C′ GND Figure 24a. V.28 Termination and Internal Resistance Network for Receiver 1, 2, and 3 30 C′ GND Figure 24b. V.28 Internal Resistance Network for Receiver 4 and 5 ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset 50Ω LOAD CABLE TERMINATION A′ A MAX13171E/MAX13173E/MAX13175E BALANCED INTERCONNECTING CABLE GENERATOR 125Ω RECEIVER 50Ω 125Ω 50Ω 50Ω B B′ C C′ GND GND Figure 25. Typical V.35 Interface A A′ MAX13171E R5 55kΩ R1 52Ω R8 5kΩ MAX13175E RECEIVER S3 S1 S2 R6 11kΩ R3 127Ω + 1.4V R7 11kΩ R2 52Ω B′ R4 55kΩ B S1 S2 C′ GND Figure 26. V.35 Termination and Internal Resistance Networks DTE/DCE Mode Applications The MAX13171E/MAX13173E can be hardwired for either DTE or DCE mode in one of two ways: a dedicated DTE or DCE port with an appropriate gender connector, or a port with a connector that can be configured for DTE or DCE operation by rerouting the signals to the MAX13171E and MAX13173E, using a dedicated DTE cable or dedicated DCE cable. The interface mode is selected by logic outputs from the controller or from jumpers to either VL or GND on the mode select inputs. A dedicated DCE port using a DB-25 female connector is shown in Figure 28. Figure 29 illustrates a dedicated DTE port using a DB-25 male connector. Figure 27 shows an application circuit with one common DB-25 connector that can be configured for either DTE or DCE mode. The configuration requires separate cables for proper signal routing in DTE or DCE operation. Figure 27 illustrates a DCE or DTE controller-selectable interface. The DCE/DTE and INVERT inputs switch the port’s mode of operation (Tables 1, 2). ______________________________________________________________________________________ 31 MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset 100pF VCC 100pF 100pF VCC C4 4.7µF VL 0.1µF 0.1µF VDD MAX13175E DTE_TXD/DCE_RXD T1IN DTE_SCTE/DCE_RXC T2IN T3IN DTE_TXC/DCE_TXC R1OUT DTE_RXC/DCE_SCTE R2OUT DTE_RXD/DCE_TXD R3OUT VL T1 T2 R6A R6B M0 LATCH T1OUTA T1OUTB T2OUTA T2OUTB DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B DCE RXD A RXD B RXC A RXC B T3OUTA/R1INA T3OUTB/R1INB 15 12 TXC A TXC B R2INA R2INB R3INA R3INB 17 9 T3 R1 R2 R3 3 16 7 MAX13171E M0 M1 M2 DCE/DTE 0.1µF R5A R5B 0.1µF R4A R4B C5 4.7µF VEE M1 VEE R2A R2B R3A R3B C3 4.7µF CHARGE PUMP R1A R1B VDD 0.1µF DCE/DTE M2 C2 1µF C1 1µF 1 TXC A TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B SG SHIELD DB-25 CONNECTOR C4 4.7µF VCC C2 1µF C1 1µF VDD C3 4.7µF CHARGE PUMP VEE C5 4.7µF T1OUTA DTE_RTS/DCE_CTS T1IN DTE_DTR/DCE_DSR T2IN T3IN DTE_DCD/DCE_DCD R1OUT DTE_DSR/DCE_DTR R2OUT DTE_CTS/DCE_RTS R3OUT DTE_LL/DCE_LL T4IN R4OUT R5OUT/T5IN T1 T2 T1OUTB T2OUTA T2OUTB 4 19 20 23 RTS A RTS B CTS A CTS B DTR A DTR B DSR A DSR B T3 R1 R2 R3 T4 T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B T4OUTA/R4INA R4 T5OUTA/R5INA T5 R5 VL 0.1µF MAX13173E M0 M1 M2 DCE/DTE INVERT DCE/DTE M2 M1 M0 INVERT Figure 27. Controller-Selectable Multiprotocol DCE/DTE Port with DB-25 Connector 32 ______________________________________________________________________________________ DCD A DCD B DTR A DTR B RTS A RTS B Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E 100pF VCC 100pF 100pF VCC C4 4.7µF VL 0.1µF 0.1µF VDD MAX13175E RXD T1IN RXC T2IN T3IN TXC R1OUT SCTE R2OUT TXD R3OUT VL 0.1µF NC C4 4.7µF T1 T2 R6A R6B R5A R5B 0.1µF T1OUTA T1OUTB T2OUTA T2OUTB R4A R4B C5 4.7µF VEE VL M0 LATCH VEE R2A R2B R3A R3B C3 4.7µF CHARGE PUMP R1A R1B VDD 0.1µF DCE/DTE M2 M1 C2 1µF C1 1µF DCE 3 RXD A (104) 16 RXD B 17 RXC A (115) 9 RXC B T3 R1 R2 R3 T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB 15 12 24 11 2 14 7 MAX13171E M0 M1 M2 DCE/DTE 1 VCC VDD CHARGE PUMP VEE C5 4.7µF T1OUTA T1IN T2IN T3IN DCD R1OUT DTR R2OUT RTS R3OUT LL SHIELD (101) C2 1µF C3 4.7µF DSR SCTE A (113) SCTE B TXD A (103) TXD B SG DB-25 FEMALE CONNECTOR C1 1µF CTS TXC A (114) TXC B T4IN R4OUT R5OUT/T5IN T1 T2 T1OUTB T2OUTA T2OUTB 4 19 20 23 CTS A CTS B DSR A DSR B T3 R1 R2 R3 T4 R2INA R2INB R3INA R3INB 8 DCD A (109) 10 DCD B 20 DTR A (108) 23 DTR B 4 RTS A (105) 19 RTS B T4OUTA/R4INA 18 T3OUTA/R1INA T3OUTB/R1INB LL A (141) R4 T5OUTA/R5INA T5 R5 VL 0.1µF NC MAX13173E M0 M1 M2 DCE/DTE INVERT M2 M1 M0 INVERT Figure 28. Controller-Selectable DCE Port with DB-25 Connector ______________________________________________________________________________________ 33 MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset 100pF VCC 100pF 100pF VCC C4 4.7µF VL 0.1µF 0.1µF VDD MAX13175E TXD T1IN SCTE T2IN T3IN TXC R1OUT RXC R2OUT RXD R3OUT VL T1 T2 M0 DTE 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B T3 R1 R2 R3 T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB 15 12 17 9 3 14 7 MAX13171E M0 M1 M2 DCE/DTE 0.1µF R6A R6B 0.1µF T1OUTA T1OUTB T2OUTA T2OUTB R5A R5B VEE R4A R4B C5 4.7µF LATCH M1 VEE R2A R2B R3A R3B C3 4.7µF CHARGE PUMP R1A R1B VDD 0.1µF DCE/DTE M2 C2 1µF C1 1µF 1 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B SG SHIELD (101) DB-25 MALE CONNECTOR C4 4.7µF VCC C2 1µF C1 1µF VDD C3 4.7µF CHARGE PUMP VEE C5 4.7µF T1OUTA RTS T1IN DTR T2IN T3IN DCD R1OUT DSR R2OUT CTS R3OUT LL T4IN R4OUT R5OUT/T5IN T1 T2 T1OUTB T2OUTA T2OUTB 4 19 20 23 RTS A (105) RTS B DTR A (108) DTR B T3 R1 R2 R3 T4 R2INA R2INB R3INA R3INB 8 DCD A (109) 10 DCD B 6 DSR A (107) 22 DSR B 5 CTS A (106) 13 CTS B T4OUTA/R4INA 18 T3OUTA/R1INA T3OUTB/R1INB LL A (141) R4 T5OUTA/R5INA T5 R5 VL 0.1µF MAX13173E M0 M1 M2 DCE/DTE INVERT M2 M1 M0 INVERT Figure 29. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector 34 ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset extra protection against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, the MAX13171E/MAX13173E/MAX13175E keep working without latchup or damage. ESD protection can be tested in various ways. The Electrical Characteristics table shows the various limits for each device and they are characterized for protection to the following methods: • Human Body Model • Contact Method specified in IEC 61000-4-2 ESD Protection ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX13171E/MAX13173E have • Air-Gap Discharge Method specified in IEC 61000-4-2 DTE SERIAL CONTROLLER MAX13171E DCE MAX13175E MAX13175E TXD T1 TXD SCTE T2 SCTE T3 TXC R3 RXC R2 RXD R1 104Ω 104Ω MAX13171E SERIAL CONTROLLER R3 TXD R2 SCTE R1 104Ω 104Ω 104Ω TXC T1 TXC RXC T2 RXC RXD T3 RXD MAX13173E MAX13173E RTS T1 RTS R3 RTS DTR T2 DTR R2 DTR T3 R1 DCD R1 DCD T3 DCD DSR R2 DSR T2 DSR CTS R3 CTS T1 CTS LL D4 T4 LL R4 LL T4 Figure 30. DCE-to-DTE X.21 Interface ______________________________________________________________________________________ 35 MAX13171E/MAX13173E/MAX13175E Complete Multiprotocol X.21 Interface A complete DTE-to-DCE interface operating in X.21 mode is shown in Figure 30. The MAX13171E is used to generate the clock and data signals, and the MAX13173E generates the control signals and local loopback (LL). The MAX13175E is used to terminate the clock and data signals to support the V.11 protocol for cable termination. The control signals do not need external termination. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 31a shows the Human Body Model, and Figure 31b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. RC 1MΩ CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX13171E/MAX13173E/MAX13175E help equipment designs to meet IEC 61000-4-2, without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2 because series resistance is lower in the IEC 61000-4-2 model. Figure 31c shows the IEC 61000-4-2 model, and Figure 31d shows the current waveform for the IEC 61000-4-2 ESD Contact Discharge test. RD 1500Ω RC 50MΩ TO 100MΩ DISCHARGE RESISTANCE CHARGE-CURRENT LIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR Figure 31a. Human Body ESD Test Model IP 100% 90% Ir HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 31c. ICE 61000-4-2 ESD Test Model I 100% 90% PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) IPEAK MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset AMPS 36.8% 10% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM Figure 31b. Human Body Current Waveform 36 tr = 0.7ns TO 1ns t 30ns 60ns Figure 31d. IEC 61000-4-2 ESD Generator Current Waveform ______________________________________________________________________________________ Multiprotocol, Pin-Selectable Data Interface Chipset N.C. N.C. GND T1OUTA T1OUTB T2OUTA T2OUTB GND T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB TOP VIEW 31 30 29 28 27 26 25 24 23 22 21 20 VEE 32 19 GND C2- 33 18 R3INA C2+ 34 17 R3INB MAX13171E GND 35 16 VCC 15 DCE/DTE C1- 36 C1+ 37 + VCC T1IN T2IN N.C. 7 8 9 10 11 12 VL 6 M0 5 R3OUT 4 R2OUT 3 R1OUT 2 T3IN 1 N.C. 13 M1 N.C. VDD 38 14 M2 *EP TQFN GND T5OUTA/R5INA T1OUTA T1OUTB T2OUTA T2OUTB GND T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA *CONNECT EXPOSED PAD TO VEE. 31 30 29 28 27 26 25 24 23 22 21 20 VEE 32 19 R3INB C2- 33 18 GND C2+ 34 17 T4OUTA/R4INA MAX13173E GND 35 16 INVERT C1- 36 15 DCE/DTE C1+ 37 + 2 3 4 5 6 7 8 9 10 11 12 VCC T2IN T3IN VL R1OUT R2OUT R3OUT R5OUT/T5IN T4IN R4OUT M0 13 M1 1 T1IN VDD 38 14 M2 *EP TQFN *CONNECT EXPOSED PAD TO VEE. ______________________________________________________________________________________ 37 MAX13171E/MAX13173E/MAX13175E Pin Configurations Pin Configurations (continued) R6B R6B R6A R6A R5A R5A R5B R5B R4A R4A R4B R4B TOP VIEW 31 30 29 28 27 26 25 24 23 22 21 20 DCE/DTE 32 19 VCC LATCH 33 18 GND M2 34 17 VDD MAX13175E M1 35 16 VEE M0 36 15 VL R1C 37 + 1 2 3 4 5 6 7 8 9 10 11 12 R1A R2A R2A R2B R2B R2C R3A R3A R3B R3B 13 GND R1A R1B 38 14 R3C *EP R1B MAX13171E/MAX13173E/MAX13175E Multiprotocol, Pin-Selectable Data Interface Chipset TQFN *CONNECT EXPOSED PAD TO VEE Package Information Chip Information PROCESS: BiCMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 38 TQFN-EP T3857-1 21-0172 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.