AD ADM2209EARU

a
EMI-/EMC-Compliant ⴞ15 kV ESD Protected,
Dual RS-232 Port with Standby
ADM2209E
FEATURES
Two Complete Serial Ports, Six Drivers and Ten Receivers
Operates with 3 V or 5 V Logic
Low Power CMOS: <5 mA Operation
Low Standby Current: 100 ␮A
460 kbit/s Data Rate Guaranteed Laplink® -Compatible
0.1 ␮F Charge Pump Capacitors
Single +12 V Power Supply
+3.3 V/+5 V Standby Supply
One Receiver on Each Port Active in Standby
Complies with 89/336/EEC EMC Directive
ESD Protection to IEC1000-4-2 (801.2)
ⴞ8 kV: Contact Discharge
ⴞ15 kV: Air-Gap Discharge
ⴞ15 kV: Human Body Model
Electrical Fast Transient (EFT) Immunity (IEC1000-4-4)
Low EMI Emissions (EN55022)
Eliminates Costly TransZorbs®
Conforms to EIA/TIA-232-E Specifications
Fail-Safe Receiver Outputs
APPLICATIONS
Personal Computers
Printers
Peripherals
Modems
FUNCTIONAL BLOCK DIAGRAM
0.1mF
CMOS
INPUTS
CMOS
OUTPUTS
The ADM2209E is suitable for operation in harsh electrical
environments and is compliant with the EU directive on EMC
(89/336/EEC). Both the level of emissions and immunity are in
compliance. EM immunity includes ESD protection in excess of
± 15 kV on all I-O lines (1000-4-2), Electrical Fast Transient
protection (1000-4-4) and Radiated Immunity (1000-4-3). EM
emissions include radiated and conducted emissions as required
by Information Technology Equipment EN55022, CISPR22.
The ADM2209E conforms to the EIA-232E and CCITT V.28
specifications and operates at data rates up to 460 kbps.
3.3V/5V
0.1mF
V–
0.1mF
+
GND
CHARGE PUMP
VOLTAGE INVERTER
C+
+
0.1mF
C–
T1INA
T1
T1OUTA
T2INA
T2
T2OUTA
T3INA
T3
T3OUTA
R1OUTA
R1
R1INA
R2OUTA
R2
R2INA
R3OUTA
R3
R3INA
R4OUTA
R4
R4INA
R5OUTA
R5
R5INA
EIA/TIA-232
OUTPUTS
EIA/TIA-232
INPUTS
ADM2209E
CMOS
INPUTS
GENERAL DESCRIPTION
The ADM2209E is a complete, dual RS-232 port on a single
chip, containing six drivers and ten receivers and fully meeting
EIA-232 and V.28 specifications. The device features an onboard dc-to-dc converter to generate a –12 V power rail, eliminating the need for a negative power supply.
STBY
VDD
+12V
CMOS
OUTPUTS
T1INB
T1
T1OUTB
T2INB
T2
T2OUTB
T3INB
T3
T3OUTB
R1OUTB
R1
R1INB
R2OUTB
R2
R2INB
R3OUTB
R3
R3INB
R4OUTB
R4
R4INB
R5OUTB
R5
R5INB
EIA/TIA-232
OUTPUTS
EIA/TIA-232
INPUTS
In standby mode, one receiver on each port (R5) remains active
to allow monitoring of peripheral devices while the rest of the
system is in power-saving mode. This feature allows the
ADM2209E to wake up the system when a peripheral device
begins communication.
The ADM2209E is available in a 38-lead TSSOP package.
Laplink is a registered trademark of Traveling Software, Inc.
TransZorb is a registered trademark of General Semiconductor Industries, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
(VDD = 10.8 V to 13.2 V, VSTBY = 3.3 V ⴞ 5% or 5 V ⴞ 10%, C1 = C2 = 0.1 ␮F. All
MIN to TMAX unless otherwise noted.)
ADM2209E–SPECIFICATIONS specifications T
Typ1 Max
Parameter
Min
Units
OPERATING CONDITIONS
Operating Voltage Range, VDD
Standby Voltage Range, VSTBY
VDD Power Supply Current2
+10.8 +12 +13.2 V
+3.15
+5.5 V
5
mA
Test Conditions/Comments
No Load, All Driver Inputs at 0.8 V or 2 V,
All Receiver Inputs at +15 V or –15 V
No Load, All Tx IN at VSTBY or Open
100 200
µA
10
µA
V
V
Transmitter Input at GND
TRANSMITTER (DRIVER) EIA-232 OUTPUTS
Output Voltage Swing
± 5.0 ± 9.0
±5
± 15 ± 30
Output Short-Circuit Current, IOS
Output Resistance
300
V
mA
Ω
All Transmitter Outputs Loaded with 3 kΩ to GND
VO = 0 V, VIN = 0.8 V3
VDD = 0 V, VSTBY = 0 V, VIN = ± 2 V
RECEIVER EIA-232 INPUTS
Input Voltage Range
Input Low Threshold, VTL
Input High Threshold, VTH
Input Hysteresis
Input Resistance, RIN
+15
1.45
1.7 2.4
0.25
5
7
V
V
V
V
kΩ
VIN = ± 15 V
0.2 0.4
0.05 ± 5
V
V
µA
IOH = –40 µA
IOL = +1.6 mA
VDD = 0 V
460
460
kbps
kbps
920
kbps
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 470 pF
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF,
TA = 0°C to +85°C, 5 V ± 10% Only
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 470 pF,
VSTBY = 5 V ± 5%, V DD = 12 V ± 5%
RL = 3 kΩ, CL = 1000 pF (Figures 1 and 2)
RL = 3 kΩ, CL = 1000 pF (Figures 1 and 2)
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 470 pF
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF,
VSTBY = 5 V ± 10% Only. Measured from +3 V
to –3 V or Vice Versa
VSTBY Supply Current
TRANSMITTER (DRIVER) CMOS INPUTS
Input Pull-Up Current
High Level Input Voltage, VINH
Low Level Input Voltage, VINL
25
2.1
0.4
–15
0.4
3
4
RECEIVER OUTPUTS
High Level Output Voltage, VOH
Low Level Output Voltage, VOL
Output Leakage Current (Except R5A, R5B)
DRIVER SWITCHING CHARACTERISTICS5
Maximum Data Rate
Propagation Delay, High to Low, TPHL
Propagation Delay, Low to High, TPLH
Transition Region Slew Rate
Transition Region Slew Rate (5 V)
2.4
6
4
RECEIVER SWITCHING CHARACTERISTICS
Maximum Data Rate
920
460
Propagation Delay, R1–R4
Propagation Delay, R5
Output Rise Time, tr
Output Fall Time, tf
ESD AND EMC
ESD Protection (I-O Pins)
ESD Protection (All Other Pins)
EFT Protection (I-O Pins)
EMI Immunity
1
1
16
16
µs
µs
V/µs
V/µs
0.4
1
30
30
kbps
kbps
µs
µs
ns
ns
CL = 150 pF, VSTBY = 5 V ± 5% Only
CL = 150 pF
CL = 150 pF
CL = 150 pF
Figures 3 and 4
kV
kV
kV
kV
kV
V/m
Human Body Model
IEC1000-4-2 Air Discharge
IEC1000-4-2 Contact Discharge
Human Body Model, MIL-STD-883B
IEC1000-4-4
IEC1000-4-3
0.75
2
± 15
± 15
±8
± 2.5
±2
10
NOTES
1
All typicals are given for V DD = +12 V, VSTBY = 5 V, TA = +25°C.
2
Current into device pins is defined as positive. Current out-of-device pins is defined as negative. All voltages are referred to ground unless otherwise specified. For
current, minimum and maximum values are specified as an absolute value and the sign is used to indicate direction. For voltage logic levels, the more positive value is
designated as maximum. For example, if –6 V is a maximum, the typical value (–6.8 V) is more negative.
3
Only one driver output shorted at a time.
4
If receiver inputs are unconnected, receiver output is a logic high.
5
Refer to typical curves. Driver output slew rate is measured from the +3.0 V to the –3.0 V level on the output waveform. Slew rate is determined by load capacitance.
Specifications subject to change without notice.
–2–
REV. 0
ADM2209E
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
(TA = +25°C unless otherwise noted)
VSTBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V
Input Voltages
Driver Inputs TnINA/B . . . . . . . . . –0.3 V to (VSTBY, +0.3 V)
Receiver Inputs Rn INA/B . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Output Voltages
Driver Outputs Tn OUTA/B . . . . . . . . . . . . . . . . . . . . . ± 15 V
Receiver Outputs RnOUTA/B . . . . –0.3 V to (VSTBY, +0.3 V)
Short Circuit Duration
Tn OUTA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Power Dissipation
RU-38 TSSOP (Derate 12 mW/°C Above +70°C) . . . 1488 mW
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
ESD Rating (MIL-STD-883B) (I-O Pins) . . . . . . . . . . ±15 kV
ESD Rating (MIL-STD-883B) (Except I-O) . . . . . . . . ± 2.5 kV
ESD Rating (IEC1000-4-2 Air) (I-O Pins) . . . . . . . . . ±15 kV
ESD Rating (IEC1000-4-2 Contact) (I-O Pins) . . . . . . ± 8 kV
EFT Rating (IEC1000-4-4) (I-O Pins) . . . . . . . . . . . . . ± 2 kV
*This is a stress rating only; functional operation of the device at these or any other
conditions above those indicated in the operation sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
REV. 0
–3–
Model
Temperature Range
ADM2209EARU –40°C to +85°C
Package Option
RU-38
PIN CONFIGURATION
R5OUTA 1
38
R5INA
R4OUTA 2
37
R4INA
R3OUTA 3
36
R3INA
R2OUTA 4
35
R2INA
R1OUTA 5
34
R1INA
T3INA 6
33
T3OUTA
T2INA 7
32
T2OUTA
T1INA 8
31
T1OUTA
STBY
30
V–
9
ADM2209E
VDD 10
TOP VIEW 29 C–
C+ 11 (Not to Scale) 28 GND
T1INB 12
27
T1OUTB
T2INB 13
26
T2OUTB
T3INB 14
25
T3OUTB
R1OUTB 15
24
R1INB
R2OUTB 16
23
R2INB
R3OUTB 17
22
R3INB
R4OUTB 18
21
R4INB
R5OUTB 19
20
R5INB
ADM2209E
PIN FUNCTION DESCRIPTION
Pin Number
Mnemonic
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
R5OUTA
R4OUTA
R3OUTA
R2OUTA
R1OUTA
T3INA
T2INA
T1INA
STBY
VDD
C+
T1INB
T2INB
T3INB
R1OUTB
R2OUTB
R3OUTB
R4OUTB
R5OUTB
R5INB
R4INB
R3INB
R2INB
R1INB
T3OUTB
T2OUTB
T1OUTB
GND
C–
V–
T1OUTA
T2OUTA
T3OUTA
R1INA
R2INA
R3INA
R4INA
R5INA
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Driver Input (3.3 V/5 V TTL/CMOS Logic Levels)
Driver Input (3.3 V/5 V TTL/CMOS Logic Levels)
Driver Input (3.3 V/5 V TTL/CMOS Logic Levels)
3.3 V/5 V Standby Power Supply for Receiver R5 in Ports A and B
Positive Power Supply, Nominally +12 V
Positive Terminal of C1 (If C1 is polarized capacitor.)
Driver Input (3.3 V/5 V TTL/CMOS Logic Levels)
Driver Input (3.3 V/5 V TTL/CMOS Logic Levels)
Driver Input (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Output (3.3 V/5 V TTL/CMOS Logic Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Driver Output (EIA-232 Signal Levels)
Driver Output (EIA-232 Signal Levels)
Driver Output (EIA-232 Signal Levels)
Ground Pin. Must Be Connected to 0 V
Negative Terminal of C1 (If C1 is polarized capacitor.)
Inverter Output (–12 V Nominal)–Terminal of C2 (If C2 is polarized capacitor.)
Driver Output (EIA-232 Signal Levels)
Driver Output (EIA-232 Signal Levels)
Driver Output (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
Receiver Input (EIA-232 Signal Levels)
–4–
REV. 0
ADM2209E
Test Circuits
VIN
+3V
1.5V
1.5V
–3V
t PHL
t PLH
VOH
PULSE
GENERATOR
VIN
80%
80%
VOUT
T
CL
1.5V
1.5V
VOUT
RL
20%
20%
VOL
tf
Figure 1. Test Circuit for Driver Propagation Delay and
Transition Time
tr
Figure 4. Receiver Propagation Delay and Transition Time
Waveforms
5ns
VIN
1.5V
1.5V
0V
t PHL
3V
t PLH
DRIVER
INPUT
VOH
90%
0V
+3V
+3V
VOUT
0V
10%
200ns
200ns
0V
–3V
–3V
+10V
VOL
tf
RECEIVER
INPUT
tr
+3V
–10V
Figure 2. Driver Propagation Delay and Transition Time
Waveforms
PULSE
GENERATOR
VIN
VOUT
R
–3V
Figure 5. Input Waveforms Used in AC Performance Tests
CL
Figure 3. Test Circuit for Receiver Propagation Delay and
Transition Time
REV. 0
5ns
3V
–5–
ADM2209E
Typical Performance Curves (VSTBY = +5 V)
–4
–6
Tx OUT LOW – Volts
VOLTS–
–6
–8
–10
–8
–10
–12
–12
–14
0
20
30
LOAD CURRENT – mA
10
40
–14
10.5
50
12.5
11.5
13.5
VDD
Figure 6. V– vs. Load Current
Figure 10. Transmitter Output Voltage Low vs. V DD
15
12
Tx OUT HIGH/LOW – Volts
Tx OUT HIGH – Volts
TxHI
10
8
Tx OUTPUT VOLTAGE HIGH (V)
6
4
–20
5
0
–5
0
0
200
400
600
800
1000
LOAD CAPACITANCE – pF
1200
Figure 11. Transmitter Output Voltage High/Low vs.
Load Capacitance
12
–6
10
–8
8
IDD – mA
–4
–10
–12
–14
TxLO
–10
–15
–10
–5
–15
LOAD CURRENT – mA
Figure 7. Transmitter Output Voltage High vs. Load
Current
Tx OUT LOW – Volts
10
IDD
6
4
2
0
5
10
15
LOAD CURRENT – mA
20
0
Figure 8. Transmitter Output Voltage Low vs. Load Current
200
400
600
800
1000
LOAD CAPACITANCE – pF
1200
Figure 12. IDD vs. Load Capacitance VSTBY = 5 V
Tx OUT HIGH – Volts
14
12
10
8
10.5
11.5
12.5
13.5
VDD
Figure 9. Transmitter Output Voltage High vs. V DD
–6–
REV. 0
ADM2209E
Typical Performance Curves (VSTBY = +3.3 V)
–3
–6
Tx OUT LOW – Volts
VOLTS–
–5
–7
–9
CHARGE PUMP VOLTAGE V – (V)
–8
–10
–12
–11
–13
0
10
20
30
LOAD CURRENT – mA
40
–14
10
50
Figure 13. V– vs. Load Current
11
12
VDD
13
14
Figure 17. Transmitter Output Voltage Low vs. V DD
13
15
11
10
Tx OUT – Volts
Tx OUT HIGH – Volts
TxHI
9
7
Tx OUTPUT VOLTAGE HIGH (V)
5
5
0
–5
TxLO
–10
3
1
–15
–15
–5
–10
LOAD CURRENT – mA
0
0
Figure 14. Transmitter Output Voltage High vs. Load
Current
200
400
600
800
1000
LOAD CAPACITANCE – pF
1200
Figure 18. Transmitter Output Voltage vs. Load Capacitance @ 460 kBPS
–2
10
8
–6
IDD – mA
Tx OUT LOW – Volts
–4
Tx OUTPUT VOLTAGE LOW (V)
–8
IDD – mA
6
4
–10
2
–12
0
5
10
LOAD CURRENT – mA
0
15
Figure 15. Transmitter Output Voltage Low vs. Load
Current
Tx OUT HIGH – Volts
12
10
11.5
12.5
13.5
VDD
Figure 16. Transmitter Output Voltage High vs. V DD
REV. 0
1000
400
600
800
LOAD CAPACITANCE – pF
1200
Figure 19. IDD vs. Load Capacitance
14
8
10.5
200
–7–
ADM2209E
GENERAL DESCRIPTION
The inverted output V– goes to GND. All transmitter outputs
are disabled and receivers R1 through R4 on each port are threestated. The remaining receiver on each port (R5) remains fully
active.
The ADM2209E is a rugged dual-port RS-232 line driver/receiver that operates from a single, +12 V supply, thus removing
the need for a –12 V power supply. It contains ten receivers and
six drivers, and provides a one-chip solution for both serial ports
in desktop or portable personal computers.
The standby current ISTBY remains less than 200 µA in this
mode.
Features include low power consumption, high transmission
rates and compatibility with the EU directive on electromagnetic
compatibility. EM compatibility includes protection against
radiated and conducted interference including high levels of
electrostatic discharge.
VDD (12V)
INTERNAL
SHUTDOWN SIGNAL
All RS-232 inputs and outputs contain protection against
electrostatic discharges up to ± 15 kV and electrical fast transients up to ± 2 kV. This ensures compliance to IE1000-4-2 and
IEC1000-4-4 requirements.
Figure 21. Standby Detection Circuit
This device is ideally suited for operation in electrically harsh
environments or where RS-232 cables are frequently being
plugged/unplugged. They are also immune to high RF field
strengths without special shielding precautions. Emissions are
also controlled to within very strict limits.
Charge Pump Capacitors And Supply Decoupling
For proper operation of the charge pump, the capacitors should
have an equivalent series resistance (ESR) less than 1 Ω. As the
charge pump draws current pulses from VDD, the VDD decoupling capacitor should also have low ESR. The V– decoupling
capacitor and reservoir capacitor should also have low ESR
because they determine how effectively ESD pulses are clamped
to VDD or V– by the on-chip clamp diodes. Tantalum or monolithic ceramic capacitors are suitable for these components. If
using tantalum capacitors, do not forget to observe polarity.
A novel feature of this device is that one receiver (R5) in each
port can be kept active by a low-current, +3 V/+5 V power
supply, while the rest of the system is powered down. This allows the system to be awakened when peripheral devices begin
to communicate with it.
Transmitter (Driver) Section
CIRCUIT DESCRIPTION
The drivers convert 5 V logic input levels into EIA-232 output
levels. With VDD = +12 V and driving an EIA-232 load, the
output voltage swing is typically ± 9 V.
The internal circuitry consists of four main sections. These are:
1. A charge pump dc-to-dc converter
2. Logic (3 V/5 V)-to-EIA-232 transmitters
3. EIA-232-to-logic receivers
4. Transient protection circuit on all I-O lines
Unused inputs may be left unconnected, as an internal 400 kΩ
pull-up resistor pulls them high, forcing the outputs into a low
state. The input pull-up resistors typically source 10 µA when
grounded, so unused inputs should either be connected to VSTBY
or left unconnected in order to minimize power consumption.
Charge Pump DC-DC Converter
The dc-dc converter generates a negative supply voltage from
the +12 V supply, thus removing the need for a separate –12 V
rail. It consists of an on-chip 200 kHz oscillator, switching matrix and two external capacitors, as shown in Figure 20.
VDD
+12V
Receiver Section
The receivers are inverting level shifters that accept EIA-232
input levels and translate them into 5 V logic output levels. The
inputs have internal 5 kΩ pull-down resistors to ground and are
also protected against overvoltages of up to ± 30 V. The guaranteed switching thresholds are 0.4 V minimum and 2.4 V maximum. Unconnected inputs are pulled to 0 V by the internal
5 kΩ pull-down resistor. This, therefore, results in a Logic 1
output level for unconnected inputs or for inputs connected to
GND.
S3
S1
S2
GND
VSTBY (5V)
C1
+
+
S4
GND
C2
C2–
INTERNAL
OSCILLATOR
The receivers have Schmitt trigger input with a hysteresis level
of 0.25 V. This ensures error-free reception for both noisy inputs and for inputs with slow transition times.
Figure 20. Charge Pump DC-DC Converter
When S1 and S2 are closed, S3 and S4 are open, and C1 charges
to +12 V. S1 and S2 are then opened, while S3 and S4 are
closed to connect C1 across C2, dumping charge into C2. Since
the positive terminal of C2 is at ground, a negative voltage will
be built up on its negative terminal with each cycle of the oscillator. This voltage depends on the current drawn from C2. If
the current is small, the voltage will be close to –12 V, but will
fall as the current drawn increases.
HIGH BAUD RATE
The ADM2209E features high slew rates permitting data transmission at rates well in excess of the EIA-232-E specifications.
RS-232 levels are maintained at data rates up to 920 kb/s. This
allows for high speed data links between two terminals and,
indeed, is suitable for the new generation modem standards.
Standby Operation
ESD/EFT TRANSIENT PROTECTION SCHEME
The ADM2209E automatically enters a standby or shutdown
mode when the VDD power supply is removed. An on-chip comparator circuit generates an internal shutdown signal. This signal disables the internal oscillator and hence the charge pump.
The ADM2209E uses protective clamping structures on all inputs and outputs, which clamps the voltage to a safe level and
dissipates the energy present in ESD (Electrostatic) and EFT
–8–
REV. 0
ADM2209E
(Electrical Fast Transient) discharges. A simplified schematic of
the protection structure is shown in Figures 22a and 22b. Each
input and output contains two back-to-back high speed clamping
diodes. During normal operation with maximum RS-232 signal
levels, the diodes have no effect as one or the other is reversebiased, depending on the polarity of the signal. If, however, the
voltage exceeds about ± 50 V, reverse breakdown occurs and the
voltage is clamped at this level. The diodes are large p-n junctions
designed to handle the instantaneous current surge which can
exceed several amperes.
The transmitter outputs and receiver inputs have a similar protection structure. The receiver inputs can also dissipate some of
the energy through the internal 5 kΩ resistor to GND as well as
through the protection diodes.
It is possible that the ESD discharge could induce latch-up in the
device under test. This test is therefore more representative of a
real-world I-O discharge where the equipment is operating normally with power applied. For maximum peace of mind, however,
both tests should be performed, to ensure maximum protection
both during handling and later, during field service.
The protection structure achieves ESD protection up to ±15 kV
and EFT protection up to ± 2 kV on all RS-232 I-O lines. The
methods used to test the protection scheme are discussed later.
RECEIVER
INPUT
product connected to the I-O port. Traditional ESD test methods such as the MIL-STD-883B method 3015.7 do not fully
test a product’s susceptibility to this type of discharge. This test
was intended to test a product’s susceptibility to ESD damage
during handling. Each pin is tested with respect to all other
pins. There are some important differences between the traditional test and the IEC test:
(a) The IEC test is much more stringent in terms of discharge
energy. The peak current injected is over four times greater.
(b) The current rise time is significantly faster in the IEC test.
(c) The IEC test is carried out while power is applied to the device.
RIN
R1
HIGH
VOLTAGE
GENERATOR
Rx
D1
R2
DEVICE
UNDER TEST
C1
D2
ESD TEST METHOD
Figure 22a. Receiver Input Protection Scheme
R2
C1
H. BODY MIL-STD-883B
1.5kV
100pF
IEC1000-4-2
330V
150pF
Figure 23. ESD Test Standards
TRANSMITTER
OUTPUT
Tx
D1
100
D2
90
IPEAK – %
Figure 22b. Transmitter Output Protection Scheme
ESD TESTING (IEC1000-4-2)
IEC1000-4-2 (previously 801-2) specifies compliance testing
using two coupling methods, contact discharge and air-gap
discharge. Contact discharge calls for a direct connection to the
unit being tested. Air-gap discharge uses a higher test voltage
but does not make direct contact with the unit under test. With
air discharge, the discharge gun is moved towards the unit under test developing an arc across the air gap, hence the term airdischarge. This method is influenced by humidity, temperature,
barometric pressure, distance and rate of closure of the discharge
gun. The contact-discharge method, while less realistic, is more
repeatable and is gaining acceptance in preference to the air-gap
method.
36.8
10
TIME t
Figure 24. Human Body Model ESD Current Waveform
100
IPEAK – %
90
Although very little energy is contained within an ESD pulse,
the extremely fast rise time coupled with high voltages can cause
failures in unprotected semiconductors. Catastrophic destruction can occur immediately as a result of arcing or heating. Even
if catastrophic failure does not occur immediately, the device
may suffer from parametric degradation, which may result in
degraded performance. The cumulative effects of continuous
exposure can eventually lead to complete failure.
10
0.1 TO 1ns
TIME t
30ns
I-O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I-O cable can result in a static discharge that can damage or completely destroy the interface
REV. 0
tDL
tRL
60ns
Figure 25. IEC1000-4-2 ESD Current Waveform
–9–
ADM2209E
Table VI.
The ADM2209E is tested using both of the above-mentioned
test methods. All pins are tested with respect to all other pins as
per the MIL-STD-883B specification. In addition, all I-O pins
are tested as per the IEC test specification. The products were
tested under the following conditions:
(a) Power-On—Normal Operation
(b) Power-Off
Level
V Peak (kV)
PSU
V Peak (kV)
I-O
There are four levels of compliance defined by IEC1000-4-2.
The ADM2209E meets the most stringent compliance level for
both contact and air-gap discharge. This means that the products
are able to withstand contact discharges in excess of 8 kV and airgap discharges in excess of 15 kV.
1
2
3
4
0.5
1
2
4
0.25
0.5
1
2
A simplified circuit diagram of the actual EFT generator is
illustrated in Figure 27.
Table IV. IEC1000-4-2 Compliance Levels
Contact Discharge
kV
2
4
6
8
Level
1
2
3
4
Air Discharge
kV
2
4
8
15
Table V. ADM2209E ESD Test Results
ESD Test Method
I-O Pins
Other Pins
MIL-STD-883B
IEC1000-4-2
Contact
Air
± 15 kV
± 2.5 kV
± 8 kV
± 15 kV
FAST TRANSIENT BURST TESTING (IEC1000-4-4)
IEC1000-4-4 (previously 801-4) covers electrical fast-transient/
burst (EFT) immunity. Electrical fast transients occur as a
result of arcing contacts in switches and relays. The tests simulate the interference generated when, for example, a power relay
disconnects an inductive load. A spark is generated due to the
well-known back EMF effect. In fact the spark consists of a burst
of sparks as the relay contacts separate. The voltage appearing
on the line, therefore, consists of a burst of extremely fast transient impulses. A similar effect occurs when switching on fluorescent lights.
The fast transient burst test defined in IEC1000-4-4 simulates
this arcing and its waveform is illustrated in Figure 26. It consists of a burst of 2.5 kHz to 5 kHz transients repeating at
300 ms intervals. It is specified for both power and data lines.
V
t
300ms
V
15ms
5ns
50ns
HIGH
VOLTAGE
SOURCE
RC
CC
RM
L
CD
50V
OUTPUT
ZS
Figure 27. IEC1000-4-4 Fast Transient Generator
The transients are coupled onto the signal lines using an EFT
coupling clamp. The clamp is 1 meter long and it completely
surrounds the cable, providing maximum coupling capacitance
(50 pF to 200 pF typ) between the clamp and the cable. High
energy transients are capacitively coupled onto the signal lines.
Fast rise times (5 ns) as specified by the standard result in very
effective coupling. This test is very severe since high voltages
are coupled onto the signal lines. The repetitive transients can
often cause problems where single pulses do not. Destructive
latch-up may be induced due to the high energy content of the
transients. Note that this stress is applied while the interface
products are powered up and transmitting data. The EFT test
applies hundreds of pulses with higher energy than ESD. Worst
case transient current on an I-O line can be as high as 40 A.
Test results are classified according to the following:
1. Normal performance within specification limits.
2. Temporary degradation or loss of performance which is selfrecoverable.
3. Temporary degradation or loss of function or performance
which requires operator intervention or system reset.
4. Degradation or loss of function which is not recoverable due
to damage.
The ADM2209E has been tested under worst case conditions
using unshielded cables and meets Classification 2. Data transmission during the transient condition is corrupted, but it may
be resumed immediately following the EFT event without user
intervention.
IEC1000-4-3 RADIATED IMMUNITY
IEC1000-4-3 (previously IEC801-3) describes the measurement method and defines the levels of immunity to radiated
electromagnetic fields. It was originally intended to simulate the
electromagnetic fields generated by portable radio transceivers
or any other device that generates continuous wave radiated
electromagnetic energy. Its scope has since been broadened to
include spurious EM energy which can be radiated from fluorescent lights, thyristor drives, inductive loads, etc.
t
0.2/0.4ms
Figure 26. IEC1000-4-4 Fast Transient Waveform
–10–
REV. 0
ADM2209E
Testing for immunity involves irradiating the device with an EM
field. There are various methods of achieving this, including use
of an echoic chamber, stripline cell, TEM cell, GTEM cell. A
stripline cell consists of two parallel plates with an electric field
developed between them. The device under test is placed within
the cell and exposed to the electric field. There are three severity
levels having field strengths ranging from 1 V to 10 V/m. Results
are classified in a fashion similar to those for IEC1000-4-4.
1. Normal operation.
signal lines to minimize crosstalk, without the complication of
multilayer PCBs.
Note that the two receivers kept active by the standby supply
(R5INA and R5INB) should be connected to the Ring In (RI)
line, so that the system can be awakened when a peripheral
device begins to communicate.
FAIL-SAFE RECEIVER OUTPUTS
The ADM2209E has fail-safe receiver outputs that assume a
high output level if the receiver input is zero or open-circuit.
2. Temporary degradation or loss of function that is selfrecoverable when the interfering signal is removed.
LAPLINK COMPATIBILITY
3. Temporary degradation or loss of function that requires
operator intervention or system reset when the interfering
signal is removed.
The ADM2209E can operate up to 460 kbps data rate under
maximum driver load conditions of CL = 1000 pF and
RL = 3 kΩ at minimum power supply voltages.
4. Degradation or loss of function that is not recoverable due to
damage.
The ADM2209E easily meets Classification 1 at the most stringent (Level 3) requirement. In fact, field strengths up to 30 V/m
showed no performance degradation and error-free data transmission continued even during irradiation.
Table VII. Test Severity Levels (IEC1000-4-3)
Level
1
2
3
Field Strength
V/m
SUPER I/O
CHIP
DCD
R1
DCD
DSR
R2
DSR
RxD
R3
RxD
RTS
T1
RTS
TxD
T2
TxD
CTS
R4
CTS
DTR
T3
DTR
RI
R5
RI
2
7
3
9-WAY D
CONNECTOR
COM1
8
4
9
5
ADM2209E
1
3
10
EMISSIONS/INTERFERENCE
EN55 022, CISPR22 defines the permitted limits of radiated
and conducted interference from Information Technology (IT)
equipment. The objective of the standard is to minimize the
level of emissions, both conducted and radiated.
DCD
R1
DCD
DSR
R2
DSR
RxD
R3
RxD
RTS
T1
RTS
TxD
T2
TxD
CTS
R4
CTS
DTR
T3
DTR
RI
R5
RI
APPLICATIONS INFORMATION
+3V or +5V
In a typical Data Terminal Equipment (DTE) to Data Circuit
Terminating Equipment (DCE) 9-lead de facto interface implementation, two data lines (TxD and RxD) and six control lines
(RTS, DTR, DSR, CTS and RI) are required. With its six
drivers and ten receivers, the ADM2209E offers a single-chip
solution for the two RS-232 ports normally supplied as standard
in a desktop or notebook personal computer, as shown in Figure
28. The flow-through pinout of the device allows for a very
simple PCB layout, and allows a ground plane to be placed
beneath the IC, and ground lines to be inserted between the
REV. 0
1
6
–11–
+12V
1
6
2
7
3
9-WAY D
CONNECTOR
COM2
8
4
9
5
0.1mF
0.1mF
0.1mF
0.1mF
Figure 28. Typical Application for a Dual Serial Port
ADM2209E
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
38-Lead TSSOP Package (RU-38)
C3642–8–7/99
0.386 (9.80)
0.378 (9.60)
20
38
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
19
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0200 (0.50)
BSC
0.0106 (0.27)
0.0067 (0.17)
0.0079 (0.20)
0.0035 (0.090)
88
08
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
SEATING
PLANE
0.0433 (1.10)
MAX
–12–
REV. 0