QUANTUM QT150-AS

QProx™ QT140 / QT150
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4 AND 5 KEY QTOUCH™ SENSOR ICs
Completely independent QT touch circuits
DIP
SSOP
Individual logic outputs per channel (open drain)
Vss
/RST
Vdd
/RST
Vss
OSC_I
Vdd
OSC_I
Vdd
OSC_O
Vss
OSC_O
Vdd
OPT2
Vss
OPT2
Sensitivity easily adjusted on a per-channel basis
SNS1A
OPT1
Vss
OPT1
100% autocal for life - no adjustments required
SNS1B
SYNC
SNS1A
SYNC
SNS2A
OUT5
SNS1B
OUT5
SNS2B
OUT4
SNS2A
OUT4
SNS3A
OUT3
SNS2B
OUT3
SNS3B
OUT2
SNS3A
OUT2
SNS4A
OUT1
SNS3B
OUT1
SNS4B
AKS
SNS4A
AKS
SNS5A
OC
SNS4B
OC
SNS5B
SNS5A
SNS5B
Projects prox fields through any dielectric
Only one external capacitor required per channel
3~5.5V, 5mA single supply operation
Toggle mode for on/off control (strap option)
10s, 60s, infinite auto-recal timeout (strap options)
AKS™ Adjacent Key Suppression (pin option)
Sync pin for multi-chip sync or line sync
Vss
Less expensive per key than many mechanical switches
Eval board with backlighting - p/n E160
QT150 shown - NOTE: Pinouts are not the same!
APPLICATIONS
PC Peripherals
Backlighted buttons
Appliance controls
Security systems
Access systems
Pointing devices
Instrument panels
Gaming machines
QT140 / QT150 charge-transfer (“QT’”) QTouch ICs are self-contained digital controllers capable of detecting near-proximity or
touch on 4 or 5 electrodes. They allow electrodes to project independent sense fields through any dielectric like glass, plastic,
stone, ceramic, and wood. They can also turn metal-bearing objects into intrinsic sensors, making them responsive to proximity
or touch. This capability coupled with their continuous self-calibration feature can lead to entirely new product concepts, adding
high value to product designs.
Each of the channels operates independently of the others, and each can be tuned for a unique sensitivity level by simply
changing its sample capacitor value.
The devices are designed specifically for human interfaces, like control panels, appliances, gaming devices, lighting controls,
or anywhere a mechanical switch or button may be found; they may also be used for some material sensing and control
applications.
These devices require only a common inexpensive capacitor per sensing channel in order to function. They also offer patent
pending AKS™ Adjacent Key Suppression which suppresses touch from weaker responding keys and allows only a dominant
key to detect, for example to solve the problem of large fingers on tightly spaced keys.
These devices also have a SYNC I/O pin which allows for synchronization with additional similar parts and/or to an external to
suppress interference.
The RISC core of these devices use signal processing techniques pioneered by Quantum which are designed to survive
numerous real-world challenges, such as ‘stuck sensor’ conditions, component ageing, moisture films, and signal drift.
By using the charge transfer principle, these devices deliver a level of performance clearly superior to older technologies yet
are highly cost-effective.
TA
AVAILABLE OPTIONS
SSOP-28
DIP-28
00C to +700C
-400C to +1050C
00C to +700C
-400C to +1050C
QT140-AS
QT150-AS
QT140-D
QT150-D
-
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Copyright © 2002 QRG Ltd
QT140/150 1.01/1102
Table 1-1 Pin Listing
QT140 / QT150 SSOP-28
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Vss
Vss
Vdd
Vdd
SNS1A
SNS1B
SNS2A
SNS2B
SNS3A
SNS3B
SNS4A
SNS4B
NC/SNS5A
Vss
NC/SNS5B
OC
AKS
OUT1
OUT2
OUT3
OUT4
NC/OUT5
SYNC
OPT1
OPT2
OSC_O
OSC_I
/RST
QT140 / QT150 DIP-28
Description
Pin Name
Negative power (Ground)
Negative power (Ground)
Positive power
Positive power
Sense pin (to Cs1, electrode)
Sense pin (to Cs1)
Sense pin (to Cs2, electrode)
Sense pin (to Cs2)
Sense pin (to Cs3, electrode)
Sense pin (to Cs3)
Sense pin (to Cs4, electrode)
Sense pin (to Cs4)
Sense pin (to Cs5, electrode) n/c on QT140
Supply negative rail (ground)
Sense pin (to Cs5) n/c on QT140
Output Option (input pin; 1= open drain)
Adjacent Key Suppression Opt. (input; 1=AKS)
Channel 1 output, o-d or p-p
Channel 2 output, o-d or p-p
Channel 3 output, o-d or p-p
Channel 4 output, o-d or p-p
Channel 5 output, o-d or p-p (n/c on QT140)
Synchronization pin (I/O pin - pull high with 10K)
Option Mode (Input pin - see Table 2-1)
Option Mode (Input pin - see Table 2-1)
Oscillator output
Oscillator input
Reset pin (active low input)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1 - OVERVIEW
1.1 BASIC OPERATION
The devices employ bursts of charge-transfer cycles to
acquire signals. Burst mode permits low power operation,
dramatically reduces RF emissions, lowers susceptibility to
RF fields, and yet permits excellent speed. Internally, signals
are digitally processed to reject impulse noise using a
'consensus' filter that requires three consecutive
confirmations of detection. Each channel is measured in
sequence starting with Channel 1.
Figures 1-6 and 1-7 show basic circuits for these devices.
See Table 1-1 for device pin listings.
DIP
Vss
/RST
Vdd
/RST
Vss
OSC_I
Vdd
OSC_I
Vdd
OSC_O
Vss
OSC_O
Vdd
OPT2
Vss
OPT2
SNS1A
OPT1
Vss
OPT1
SNS1B
SYNC
SNS1A
SYNC
SNS2A
NC
SNS1B
NC
SNS2B
OUT4
SNS2A
OUT4
SNS3A
OUT3
SNS2B
OUT3
SNS3B
OUT2
SNS3A
OUT2
SNS4A
OUT1
SNS3B
OUT1
SNS4B
AKS
SNS4A
AKS
NC
OC
SNS4B
OC
Vss
NC
NC
NC
Description
Positive power
Positive power
Negative power (Ground)
Negative power (Ground)
Negative power (Ground)
Sense pin (to Cs1, electrode)
Sense pin (to Cs1)
Sense pin (to Cs2, electrode)
Sense pin (to Cs2)
Sense pin (to Cs3, electrode)
Sense pin (to Cs3)
Sense pin (to Cs4, electrode)
Sense pin (to Cs4)
Sense pin (to Cs5, electrode) n/c on QT140
Sense pin (to Cs5) n/c on QT140
Output Option (input pin; 1= open drain)
Adjacent Key Suppression Opt. (input ; 1=AKS)
Channel 1 output, o-d or p-p
Channel 2 output, o-d or p-p
Channel 3 output, o-d or p-p
Channel 4 output, o-d or p-p
Channel 5 output, o-d or p-p (n/c on QT140)
Synchronization pin (I/O pin - pull high with 10K)
Option Mode (Input pin - see Table 2-1)
Option Mode (Input pin - see Table 2-1)
Oscillator output
Oscillator input
Reset pin (active low input)
The DIP and SOIC pinouts are not the same and serious
damage can occur if a part is miswired.
QT140/150 devices are burst mode digital charge-transfer
(QT) sensor ICs designed specifically for touch controls; they
include all hardware and signal processing functions
necessary to provide stable sensing under a wide variety of
conditions. Only a single low cost capacitor per channel is
required for operation.
SSOP
Vdd
Vdd
Vss
Vss
Vss
SNS1A
SNS1B
SNS2A
SNS2B
SNS3A
SNS3B
SNS4A
SNS4B
NC/SNS5A
NC/SNS5B
OC
AKS
OUT1
OUT2
OUT3
OUT4
NC/OUT5
SYNC
OPT1
OPT2
OSC_O
OSC_I
/RST
The QT switches and charge measurement hardware
functions are all internal to the device. A single-slope
switched capacitor ADC includes the QT charge and transfer
switches in a configuration that provides direct ADC
conversion; an external Cs capacitor accumulates the charge
from sense-plate Cx, which is then measured.
Larger values of Cx cause the charge transferred into Cs to
rise more rapidly, reducing available resolution; as a
minimum resolution is required for proper operation, this can
result in dramatically reduced gain. Conversely, larger values
of Cs reduce the rise of differential voltage across it,
increasing available resolution by permitting longer QT
bursts. The value of Cs can thus be increased to allow larger
values of Cx to be tolerated. The IC is responsive to both Cx
and Cs, and changes in Cs can result in substantial changes
in sensor gain.
Fig 1-1 QT140 Pinouts
NOTE: SSOP / DIP Pinouts are not the same!
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QT140/150 1.01/1102
sufficient, even if the coupling might seem very tenuous. For
example, powering the sensor via an isolated transformer will
provide ample ground coupling, since there is capacitance
between the windings and/or the transformer core, and from
the power wiring itself directly to 'local earth'. Even when
battery powered, just the physical size of the PCB and the
object into which the electronics is embedded will generally
be enough to couple a few picofarads back to local earth.
Unused channels: If a channel is not used, a dummy sense
capacitor (nominal value: 1nF) of any type must be
connected between the unused SNSnA / SNSnB pins ensure
correct operation.
Unused pins: Unused device pins labeled NC should
remain unconnected.
1.2 ELECTRODE DRIVE
These devices have completely independent sensing
channels. The internal ADC treats Cs on each channel as a
floating transfer capacitor; as a direct result, sense
electrodes can be connected to either SNSnA or SNSnB and
the sensitivity and basic function will be the same; however
there is an advantage in connecting electrodes to SNSnA
lines to reduce EMI susceptibility.
1.3.2 KEY GEOMETRY, SIZE, AND LOCATION
There is no restriction on the shape of the key electrode; in
most cases common sense and a little experimentation can
result in a good electrode design. The devices will operate
with long thin electrodes, round or square ones, or keys with
odd shapes. Electrodes can also be on 3-dimensional
surfaces. Sensitivity is related to the amount of electrode
surface area, overlying panel material and thickness, and the
ground return coupling quality of the circuit.
The PCB traces, wiring, and any components associated
with or in contact with SNSnA and SNSnB will become touch
sensitive and should be treated with caution to limit the touch
area to the desired location.
If a relatively large touch area is desired, and if tests show
that the electrode has more capacitance than the part can
tolerate, the electrode can be made into a sparse mesh
(Figure 1-3) having lower Cx than a solid plane.
Multiple touch electrodes connected to SNSnA can be used,
for example to create control surfaces on both sides of an
object.
Since the channels acquire their signals in time-sequence,
any of the electrodes can be placed in direct proximity to
each other if desired without cross-interference.
It is important to limit the amount of stray capacitance on the
SNSnA and SNSnB terminals, for example by minimizing
trace lengths and widths to allow for higher gains and lower
values of Cs.
1.3.3 BACKLIGHTING KEYS
Touch pads can be back-illuminated quite readily using
electrodes with a sparse mesh (Figure 1-3) or a hole in the
middle (Figure 1-4). The holes can be as large as 4 cm in
diameter provided that the ring of metal is at least twice as
wide as the thickness of the overlying panel, and the panel is
greater than 1/8 as thick as the diameter of the hole. Thin
panels do not work well with this method as they do not
propagate fields laterally very well, and will have poor
sensitivity in the middle. Experimentation is required.
1.3 KEY DESIGN
1.3.1 KIRCHOFF’S CURRENT LAW
Like all capacitance sensors, these parts rely on Kirchoff’s
Current Law (Figure 1-2) to detect the change in capacitance
of the electrode. This law as applied to capacitive sensing
requires that the sensor’s field current must complete a loop,
returning back to its source in order for capacitance to be
sensed. Although most designers relate to Kirchoff’s law with
regard to hardwired circuits, it applies equally to capacitive
field flows. By implication it requires that the signal ground
and the target object must both be coupled together in some
manner for a capacitive sensor to operate properly. Note that
there is no need to provide actual galvanic ground
connections; capacitive coupling to ground (Cx1) is always
A good example of backlighting can be found in the E160
evaluation board.
1.3.4 VIRTUAL CAPACITIVE GROUNDS
When detecting human contact (e.g. a fingertip), grounding
of the person is never required. The human body naturally
has several hundred picofarads of ‘free space’ capacitance
to the local environment (Cx3 in Figure 1-2), which is more
than two orders of magnitude greater than that required to
create a detection. The sensor’s PCB however may be
physically small, so there may be little ‘free space’ coupling
(Cx1 in Figure 1-2) between it and the environment to
Figure 1-2 Kirchoff's Current Law
CX2
Figure 1-3 Mesh Electrode Geometry
S e nse E le ctro de
S EN SO R
CX 1
Su rro und in g e nv iro nm en t
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CX3
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QT140/150 1.01/1102
Figure 1-4 Open Electrode for Back-Illumination
Figure 1-5 Shielding Against Fringe Fields
Sense
wire
Se nse
w ire
complete the return path. If the circuit ground cannot be
earth grounded by wire, for example via the supply
connections, then a ‘virtual capacitive ground’ may be
required to increase return coupling.
A ‘virtual capacitive ground’ can be created by connecting
the IC's circuit ground to:
(1) A nearby piece of metal or metallized housing;
(2) A floating conductive ground plane;
(3) A larger electronic device (to which its output might be
connected anyway).
most direct way to impact sensitivity is to alter the value of
Cs; more Cs yields higher sensitivity.
Free-floating ground planes such as metal foils should
maximize exposed surface area in a flat plane if possible. A
square of metal foil will have little effect if it is rolled up or
crumpled into a ball. Virtual ground planes are more effective
and can be made smaller if they are physically bonded to
other surfaces, for example a wall or floor.
1.3.6.1 Alternative Ways to Increase Sensitivity
Sensitivity can also be increased by using bigger electrodes,
reducing panel thickness, or altering panel composition.
Increasing electrode size can have diminishing returns, as
high values of Cx counteract sensor gain; however, Cs can
be increased to combat this up to the rated device limit. Also,
increasing the electrode's surface area will not substantially
increase touch sensitivity if its diameter is already much
larger in surface area than fingertip contact area.
1.3.5 FIELD SHAPING
The electrode can be prevented from sensing in undesired
directions with the assistance of metal shielding connected
to circuit ground (Figure 1-5). For example, on flat surfaces,
the field can spread laterally and create a larger touch area
than desired. To stop field spreading, it is only necessary to
surround the touch electrode on all sides with a ring of metal
connected to circuit ground. The ring will stop field spreading
from that point outwards.
The panel or other intervening material can be made thinner,
but again there are diminishing rewards for doing so. Panel
material can also be changed to one having a higher
dielectric constant, which will help propagate the field
through to the front. Locally adding some conductive material
to the panel (conductive materials essentially have an infinite
dielectric constant) will also help; for example, adding carbon
or metal fibers to a plastic panel will greatly increase frontal
field strength, even if the fiber density is too low to make the
plastic bulk-conductive.
If one side of the panel to which the electrode is fixed has
moving traffic near it, these objects can cause inadvertent
detections. This is called ‘walk-by’ and is caused by the fact
that the fields radiate from either surface of the electrode
equally well. Again, shielding in the form of a metal sheet or
foil connected to circuit ground will prevent walk-by; putting
an air gap between the grounded shield and the electrode
will help to keep the value of Cx low.
1.3.6.2 Decreasing Sensitivity
In some cases the circuit may be too sensitive. Gain can be
lowered further by a number of strategies: a) making the
electrode smaller, b) making the electrode into a sparse
mesh using a high space-to-conductor ratio (Figure 1-3), or
c) by decreasing the Cs capacitors.
1.3.6 SENSITIVITY
Sensitivity can be altered to suit various applications and
situations on a channel-by-channel basis. The easiest and
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QT140/150 1.01/1102
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Figure 1-6 Basic Circuit (QT140, SSOP Package)
Figure 1-7 Basic Circuit (QT150, SSOP Package)
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Figure 1-8 Synchronized QT140, QT150 Circuits
QT140/150 1.01/1102
2 - QT140/QT150 SPECIFICS
Figure 2-1 Drift Compensation
2.1 SIGNAL PROCESSING
These devices process all signals using 16 bit
math, using a number of algorithms pioneered by
Quantum. These algorithms are specifically
designed to provide for high survivability in the face
of adverse environmental changes.
S ig na l
H ys te res is
T hre sh old
R efer ence
2.1.1 DRIFT COMPENSATION
Signal drift can occur because of changes in Cx,
Cs, and Vdd over time. If a low grade Cs capacitor
Ou tpu t
is chosen, the signal can drift greatly with
temperature. If keys are subject to extremes of
temperature or humidity, the signal can also drift. It
conditions. There are three timeout durations available via
is crucial that drift be compensated, else false detections,
strap option: 10s, 60s, and infinite (Table 2-1).
non-detections, and sensitivity shifts will follow.
Max On-Duration works independently per channel; a
timeout on one channel has no effect on another channel
except when the AKS feature is impacted on an adjacent
key. Note also that the timings in Table 2-1 are dependent on
the oscillator frequency: Doubling the recommended
frequency will halve the timeouts.
Drift compensation (Figure 2-1) is a method that makes the
reference level track the raw signal at a slow rate, only while
no detection is in effect. The rate of reference adjustment
must be performed slowly else legitimate detections can also
be ignored. The IC drift compensates each channel
independently using a slew-rate limited change to the
reference level; the threshold and hysteresis values are
slaved to this reference.
Infinite timeout is useful in applications where a prolonged
detection can occur and where the output must reflect the
detection no matter how long. In infinite timeout mode, the
designer should take care to be sure that drift in Cs, Cx, and
Vdd do not cause the device to ‘stick on’ inadvertently even
when the target object is removed from the sense field.
Once an object is sensed, the drift compensation mechanism
ceases since the signal is legitimately high, and therefore
should not cause the reference level to change.
The signal drift compensation is 'asymmetric'; the reference
level drift-compensates in one direction faster than it does in
the other. Specifically, it compensates faster for decreasing
signals than for increasing signals. Increasing signals should
not be compensated for quickly, since an approaching finger
could be compensated for partially or entirely before even
approaching the sense electrode. However, an obstruction
over the sense pad, for which the sensor has already made
full allowance for, could suddenly be removed leaving the
sensor with an artificially elevated reference level and thus
become insensitive to touch. In this latter case, the sensor
will compensate for the object's removal very quickly, usually
in only a few seconds.
The delay timings for Max On-Duration depend directly on
resonator frequency. Also, if the acquisition burst on one or
more channels lasts longer than 5.5ms per channel, the
specified timings may be longer.
2.1.4 DETECTION INTEGRATOR
It is desirable to suppress false detections due to electrical
noise or from quick brushes with an object. To this end,
these devices incorporate a per-key ‘Detection Integrator’
counter that increments with each signal detection exceeding
the signal threshold (Figure 2-1) until a limit count is
reached, after which an Out pin becomes active. If a ‘no
detect’ is sensed prior to the limit, this counter is reset to
zero. The required limit count is 3.
With large values of Cs and small values of Cx, drift
compensation will appear to operate more slowly than with
the converse.
The Detection Integrator can also be viewed as a
'consensus' vote requiring a detection in three successive
samples to trigger an active output.
2.1.2 THRESHOLD CALCULATION
The internal threshold level is fixed at 6 counts for all
channels. These IC's employ a fixed hysteresis of 2 counts
below the threshold (33%).
2.1.5 FORCED SENSOR RECALIBRATION
Pin 28 is a Reset pin, active-low, which in cases where
power is clean can be simply tied to Vdd. On power-up, the
device will automatically recalibrate all channels of sensing.
2.1.3 MAX ON-DURATION
If a sufficiently large object contacts a key for a prolonged
duration, the signal will trigger a detection output preventing
further normal operation. To cure such ‘stuck key’ conditions,
the sensor includes a timer on each channel to monitor
detection duration. If a detection exceeds the maximum timer
setting, the timer causes the sensor to perform a full
recalibration (if not set for infinite). This is known as the Max
On-Duration feature.
Pin 28 can also be controlled by logic or a microcontroller to
force the chip to recalibrate, by toggling it low for 5µs then
raising it high again.
2.1.6 RESPONSE TIME
Response time is fixed at 99ms at a 10MHz clock. Response
time can be altered by changing the clock frequency;
doubling the frequency to 20MHz will cut the response time
to 49ms.
After the Max On-Duration interval, the sensor channel will
once again function normally, even if partially or fully
obstructed, to the best of its ability given electrode
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QT140/150 1.01/1102
2.2 OUTPUT FEATURES
Table 2-1 OPT Strap Options
These devices are designed for maximum flexibility and can
accommodate most popular sensing requirements via option
pins.
OPT1
OPT1 and OPT2 inputs control the output mode and Max
On-Duration settings;
OC controls the output drive type;
OPT2
Max On-Duration
DC Out
Gnd
Vdd
10s
DC Out
Vdd
Gnd
60s
Toggle
Vdd
Vdd
10s
DC Out
Gnd
Gnd
infinite
AKS controls the use of Adjacent Key Suppression.
All option pins are read by the IC once each complete
acquisition cycle and can be changed during operation.
e.g. batteries. Detection ‘stiction’, the opposite effect, can
occur if a load is shed when an Out pin is active.
OPT1 and OPT2 modes are shown in Table 2-1. These OPT
pins affect all sensing channels.
2.3 AKS™ - ADJACENT KEY SUPPRESSION
These devices feature patent-pending Adjacent Key
Suppression for use in applications where keys are tightly
spaced. If keys are very close and a large finger touches one
key, adjacent keys might also activate. AKS stops such false
detections by comparing relative signal levels among
channels and choosing the channel with the largest signal.
2.2.1 DC MODE OUTPUTS
Outputs can respond in a DC mode, where they are active
upon a confirmed detection. An output will remain active for
the duration of the detection, or until the ‘Max On-Duration’
expires (if not infinite), whichever occurs first. If a Max
On-Duration timeout occurs first, the sensor performs a full
recalibration and the output becomes inactive until the next
detection.
The AKS feature can be disabled via the AKS pin:
AKS=0: Disabled; AKS=1: Enabled
The AKS in these parts is a ‘global’ in nature, meaning that
the signal of each key is compared with all other keys, and
only the key with the strongest signal among all keys will
survive initial detection. The word ‘Adjacent’ therefore should
be taken liberally, as a particular key number can be
physically near any other key number and the AKS feature
will operate correctly.
2.2.2 TOGGLE MODE OUTPUTS
This mode makes the sensor respond in an on/off flip-flop
mode. It is useful for controlling power loads, for example in
kitchen appliances, power tools, light switches, etc. or
wherever a ‘touch-on / touch-off’ effect is required.
Max On-Duration in Toggle mode is fixed at 10 seconds.
When a timeout occurs, the sensor recalibrates but leaves
the output state unchanged.
When a touch is detected on a key, but just before the
corresponding OUT pin is activated, a check is made for a
pending or current detection on the other keys. If any other
key is active, or if a signal of greater strength is found on any
other key, the key detection is suppressed. Once the active
key(s) are released, a pending key is free to detect.
2.2.3 OUTPUT DRIVE; OC OPTION PIN
The OC pin controls the output drive type.
OC=0: When tied low, the output is ‘push-pull’, i.e. ‘normal’.
In this mode, the OUT pins are active-high and can source
1mA and sink 5mA of non-inductive current.
Drift compensation also ceases for any key which has been
suppressed, provided its signal exceeds its threshold level
(Figure 2-1).
OC=1: When tied high, the output is ‘open drain’ or ‘open
collector’, i.e. There is no internal pullup device in this mode;
OUT pins are active-low and can sink 5mA of non-inductive
current.
AKS is also very effective on water films which bridge over
adjacent keys. When touching one key a water film will
‘transport’ the touch to the adjacent keys covered by the
same film. These side keys will receive less signal strength
than the key actually being touched, and so they will be
suppressed even if the signal they are detecting is large
enough to otherwise cause an output.
If inductive loads are used, such as small relays, the
inductances should be diode clamped to prevent damage.
When set to operate in a proximity mode (at high gain)
output pin currents should be limited to 1mA to prevent gain
shifting side effects from occurring, which happens when the
load current creates voltage drops on the die and bonding
wires; these small shifts can materially influence the signal
level to cause detection instability as described below.
The downside of ‘global’ AKS is that it is not possible to have
more than one key active at a time.
When two or more devices are synchronized together and all
are using AKS mode, the AKS feature does not extend
beyond each chip. Therefore, in multi-chip configurations it is
possible to use AKS on all keys but still permit 2 or more
keys to detect at the same time.
Care should be taken when the IC and the loads are both
powered from the same supply, and the supply is minimally
regulated. These devices derive their internal references
from the power supply, and sensitivity shifts can occur with
changes in Vdd, as happens when loads are switched on.
This can induce detection ‘cycling’, whereby an object is
detected, the load is turned on, the supply sags, the
detection is no longer sensed, the load is turned off, the
supply rises and the object is reacquired, ad infinitum. To
prevent this occurrence, the Out pins should only be lightly
loaded if the device is operated from an unregulated supply,
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2.4 SYNCHRONIZATION
Adjacent capacitive sensors that operate independently can
cross-interfere with each other in ways that will create
sensitivity shifts and spurious detections. Because
Quantum’s QT devices operate in burst mode as opposed to
continuous mode, the opportunity exists to solve this problem
by using time-sequencing of the sensing channels so that
physically adjacent channels do not sense within the same
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QT140/150 1.01/1102
3 - CIRCUIT GUIDELINES
time-slot. Within these ICs the sensing channels already
operate in time-sequence, so it is not possible for a given
IC’s channels to cross interfere with each other even if the
electrodes are directly adjacent to one another.
3.1 SAMPLE CAPACITOR
Charge sampler caps Cs can be virtually any plastic film or
low to medium-K ceramic capacitor. The acceptable Cs
range is from 1nF to 200nF depending on the sensitivity
required; larger values of Cs demand higher stability to
ensure reliable sensing. Acceptable capacitor types include
plastic film (especially PPS film), NP0 / C0G ceramic. X7R
ceramic can also be used but these are less stable over
temperature.
However the use of 2 or more chips can create a problem,
because if they are not somehow synchronized to each other
the cross-interference problem will occur between adjacent
channels of the different chips.
2.4.1 MULTI-CHIP SYNC
A bidrectional, open-drain SYNC pin has been provided to
allow 2 or more QT140’s or QT150’s in various combinations
to synchronize to each other (Figure 1-8). All the chips in a
system, whether 1 or 20, should connect to this common line
with a single 10K pullup resistor.
3.2 OPTION STRAPPING
The option pins OC, AKS, OPT1 and OPT2 should never be
left floating. If they are floated, the device can draw excess
power and the options will not be properly read. See Section
2.2 and 2.3 for options.
A single QT140 or QT150 must also use a pullup resistor.
SYNC floats high during the Channel 1 sensing burst. When
the IC completes Channel 1 sensing, it pulls down SYNC.
SYNC will continue to be pulled low until the last sensing
channel has completed, when it is unclamped. The IC waits
until SYNC rises high before it will start Channel 1 sensing
again.
3.3 POWER SUPPLY, PCB LAYOUT
The power supply can range from 3 to 5.5 volts. If this
fluctuates slowly with temperature, the device will track and
compensate for these changes automatically with only minor
changes in sensitivity. If the supply voltage drifts or shift
quickly, the drift compensation mechanism will not be able to
keep up, causing sensitivity anomalies or false detections.
The devices will track slow changes in Vdd, but can be
seriously affected by rapid voltage steps.
If two or more chips are tied into SYNC, all chips must
release SYNC before it actually floats high. Thus, all chips
that us a common SYNC connection will synchronize on
Channel 1.
This mechanism forces all like sensing channels to be
time-aligned among all chips. Thus, all Channel 1’s acquire
at the same time, then all Channel 2’s etc. This means that
when designing a PCB and electrode array, it is important to
not place like channel numbers next to each other or they will
cross interfere. However this leaves a tremendous latitude
for placing channels from different chips having different
channel numbers next to each other.
If the supply is shared with another electronic system, care
should be taken to assure that the supply is free of digital
spikes, sags, and surges which can cause adverse effects.
The supply is best locally regulated using a conventional
78L05 type regulator, or almost any 3-terminal LDO device
from 3V to 5V.
For proper operation a 0.1µF or greater bypass capacitor
must be used between Vdd and Vss; the bypass cap should
be placed very close to the device Vss and Vdd pins.
For example Channel 1 of chip ‘A’ can be routed and
physically placed adjacent to Channel 2 of chip ‘B’, or
Channel 4 of chip ‘F’ and so on. But it is not good to place
Channel 3 of chip ‘A’ next to Channel 3 of chip ‘B’.
The PCB should if possible include a copper pour under and
around the IC, but not extensively under the SNS lines.
2.4.2 NOISE SYNC
3.4 OSCILLATOR
The effects of external noise sources can be heavily
suppressed by synchronizing these devices to the noise
source itself. External noise creates an ‘aliasing’ or ‘beat’
frequency effect between the sampling rate of the QT part
and the external noise frequency.
The oscillator should be a 10MHz resonator with ceramic
capacitors to ground on each side. 3-pin resonators with
built-in capacitors designed for the purpose are inexpensive
and commonly found. Manufacturers include AVX, Murata,
Panasonic, etc.
In many cases, especially with repetitive noise like 50/60Hz
AC fields, the noise effects will vanish if the device is
synchronized to the external field. This can take the form of a
simple AC zero-crossing detector feeding the pullup resistor
on SYNC instead of tying the SYNC resistor to Vdd. Multiple
devices tied to SYNC can be synchronized to the mains
frequency in this fashion.
Alternatively an external clock source can be used in lieu of a
resonator. The OSC_I pin should be connected to the
external clock, and OSC_O should be left unconnected.
These ICs are fully synchronous devices that are slaved to
the OSC_I clock frequency. If the frequency of OSC_I is
changed, all timings will also change in direct proportion,
from the charge and transfer times to the detection response
times and the Max On-duration timings.
In the case of noise from sources such as backlight inverters
etc, it is sometimes best to synchronize by disabling the
inverter for a brief moment while the QT device acquires.
3.5 UNUSED CHANNELS
Unused SNS pins should not be left open. They should have
a small value non-critical dummy Cs capacitor connected to
their SNS pins to allow the internal circuit to continue to
function properly. A nominal value of 1nF (1,000pF) X7R
ceramic will suffice.
lQ
8
QT140/150 1.01/1102
Unused channels should not have sense traces or
electrodes connected to them.
3.7 RFI PROTECTION
PCB layout, grounding, and the structure of the input circuitry
have a great bearing on the success of a design that can
withstand strong RF interference.
3.6 ESD PROTECTION
In cases where the electrode is placed behind a dielectric
panel, the IC will be protected from direct static discharge.
However even with a panel, transients can still flow into the
electrodes via induction, or in extreme cases via dielectric
breakdown. Porous materials may allow a spark to tunnel
right through the material. Testing is required to reveal any
problems. The device does have diode protection on its SNS
pins which absorb and protect the device from most induced
discharges, up to 20mA; the usefulness of the internal
clamping will depending on the dielectric properties, panel
thickness, and rise time of the ESD transients.
The circuit is remarkably immune to RFI provided that certain
design rules are adhered to:
1. Use SMT components to minimize lead lengths.
2. Connect electrodes to SNSnA, not SNSnB pins.
3. Use a ground plane under and around the circuit and
along the sense lines, that is as unbroken as possible
except for relief under and beside the sense lines to
reduce total Cx. Relieved rear ground planes along the
SNS lines should be ‘mended’ by bridging over them at
1cm intervals with 0.5mm ‘rungs’ like a ladder.
In extreme cases ESD dissipation can be aided further by
adding 1K series resistors in series with the electrodes as
shown in Figures 1-6 through 1-8. Because the charge time
is 1.2µs, the circuit can tolerate large values of series-R, up
to 20k ohms in cases where electrode Cx load is below
10pF. Extra diode protection at the electrodes can also be
used, but this often leads to additional RFI problems as the
diodes will rectify RF signals into DC which will disturb the
signals.
4. Ground planes and traces should be connected only to a
common point near the Vss pins of the IC.
5. Route sense traces away from other traces or wires that
are connected to other circuits.
6. Sense electrodes should be kept away from other
circuits and grounds which are not directly connected to
the sensor’s own circuit ground; other grounds will
appear to float at high frequencies and couple RF
currents into the sense lines.
If the series-R is too large, sensitivity will drop off.
Directly placing semiconductor transient protection devices
or MOV's on the sense leads is not advised; these devices
have extremely large amounts of nonlinear parasitic C which
will swamp the capacitance of the electrode and cause
strange sensing problems.
7. Keep the Cs sampling capacitors and all series-R
components close to the IC.
Series-R’s should be low enough to permit at least 6 RC
time-constants to occur during the charge and transfer
phases, where R is the added series-R and C is the load Cx.
9. Use series-R’s in the sense lines, of as large a value as
the circuit can tolerate without degrading sensitivity
appreciably.
If the device is connected to an external control circuit via a
cable or long twisted pair, it is possible for ground-bounce to
cause damage to the Out pins and/or interfere with key
sensing. Noise current injection into the power supply is best
dealt with by shunting the noise aside to chassis ground with
capacitors, and further limited using resistors or ferrites.
10.Bypass input power to chassis ground and again at
circuit ground to reduce line-injected noise effects.
Ferrites over the power wiring may be required to
attenuate line injected noise.
lQ
8. Use a 0.1µF minimum ceramic bypass cap very close to
the Vss / Vdd supply pins.
Achieving RF immunity requires diligence and a good
working knowledge of grounding, shielding, and layout
techniques. Very few projects involving these devices will fail
EMC tests once properly constructed.
9
QT140/150 1.01/1102
4.1 ABSOLUTE MAXIMUM SPECIFICATIONS
Operating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . as designated by suffix
Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55OC to +125OC
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Short circuit duration to VDD, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to (Vdd + 0.6) Volts
4.2 RECOMMENDED OPERATING CONDITIONS
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 to 5.5V
Operating temperature range, 4.5V - 5.5V (QT140-AS, QT150-AS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 - +105C
Operating temperature range, 3.0V - 4.5V (QT140-AS, QT150-AS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 - +85C
Operating temperature range, all voltages (QT140-D, QT150-D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 - +70C
Operating frequency, 4.5V - 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 20MHz
Operating frequency, 3.0V - 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 10MHz
Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mV/s
Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mV
Cs value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nF to 200nF
Cx value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 100pF
4.3 AC SPECIFICATIONS
Parameter
Description
Vdd = 5.0, Ta = recommended, Cx = 5pF, Cs = 39nF, Fosc = 10MHz
Min
Typ
Max
Units
330
ms
TRC
Recalibration time
TPC
Charge duration
1.2
TPT
Transfer duration
1.6
µs
TAC
Acquisition time, all channels
33
ms
TBL
Burst duration, each channel
NBL
Burst length, each channel
TBLMR
TR
Allowable burst duration range
Response time
µs
3
ms
1,000
counts
0.1
Notes
5.5
99
ms
Before all timings degrade
ms
Including detection integrator
4.4 DC SPECIFICATIONS
Vdd = 5.0V, Cs = 39nF, Cx = 5pF, Fosc = 10MHz, Ta = recommended range, unless otherwise noted
Parameter
IDD
Description
VDDS
Supply turn-on slope
VIL
Low input logic level
VHL
High input logic level
VOL
Low output voltage
VOH
Min
Supply current
High output voltage
IIL
Input leakage current
AR
Acquisition resolution
lQ
Typ
Max
Units
2.5
8
mA
100
V/s
0.7
2
10
Req’d for startup, w/o reset circuit
V
OPT1, OPT2, OC, AKS, SYNC
V
OPT1, OPT2 , OC, AKS, SYNC
0.6
V
OUTn, SYNC, @ 4mA sink
V
OUTn, 1mA source
±1
µA
OPT1, OPT2, OC, AKS
14
bits
Vdd-0.7
10
Notes
QT140/150 1.01/1102
4.5 SIGNAL PROCESSING
Description
Value
Units
6
counts
From signal reference
From threshold
Threshold differential
Hysteresis
2
counts
Consensus filter length (Detection integrator)
3
samples
Positive drift compensation rate
990
ms/level
Negative drift compensation rate
231
ms/level
10, 60, infinite
secs
Post-detection recalibration timer duration
Notes
Option pin selected
All curves at Vdd = 5.0V
Burst Duration v s. Cs, Cx
18000
4000
16000
3500
14000
12000
Burst Duration, Microseconds
Burst Duration, Microseconds
Burst Duration v s. Cs, Cx
Cs = 220nF
Cs = 100nF
10000
Cs = 47nF
Cs = 39nF
8000
Cs = 22nF
Cs = 10nF
6000
4000
3000
2500
Cs = 47nF
Cs = 39nF
Cs = 22nF
2000
Cs = 10nF
1500
1000
500
2000
0
0
10
20
30
40
0
50
0
10
20
Cx
30
40
50
Cx
Figure 4-1
Figure 4-2
Burst Duration cs. Cs, Cx
18000
Burst Duration, Microseconds
16000
14000
12000
Cx = 5pF
Cx = 10pF
10000
Cx = 15pF
Cx = 22pF
Cx = 33pF
8000
Cx = 47pF
6000
4000
2000
0
0
50
100
150
200
250
Cs, nF
Figure 4-3
lQ
11
QT140/150 1.01/1102
5 - PACKAGE OUTLINES
Package type: 28-Pin Dual-In-Line
SYMBOL
Min
Millimeters
Max
a
A
M
m
Q
P
L
L1
F
R
r
S
S1
Aa
x
Y
7.112
7.874
34.163
33.02
0.584
0.406
0.203
1.016
2.54
3.175
0.381
3.175
3.632
7.874
8.128
0.203
7.493
8.382
35.179
33.02
1.22
0.559
0.508
1.651
2.54
3.556
3.683
3.632
7.874
9.906
0.203
Notes
BSC
4 places
Typical
BSC
Typical
Min
Inches
Max
0.28
0.31
1.385
1.3
0.023
0.016
0.008
0.04
0.1
0.125
0.015
0.125
0.143
0.31
0.32
0.008
0.295
0.33
1.395
1.3
0.048
0.022
0.02
0.065
0.1
0.14
0.145
0.18
0.31
0.39
0.013
Notes
BSC
4 places
Typical
BSC
Typical
D
L
2a W
e
ø
E
M
Base level
Seating level
h H
Package type: 28-pin SSOP
SYMBOL
Min
Millimeters
Max
Min
Inches
Max
M
10.070
10.33
0.396
0.407
Notes
W
7.650
7.9
0.301
0.311
2a
5.200
5.38
0.205
0.212
D
0.650
0.65
0.026
0.026
L
0.250
0.38
0.010
0.015
E
0.550
0.95
0.022
0.037
e
0.130
0.22
0.005
0.009
Ø
0º
8º
0º
8º
H
1.730
1.99
0.068
0.078
h
0.050
0.21
0.002
0.008
lQ
12
Notes
QT140/150 1.01/1102
8 - ORDERING INFORMATION
PART
TEMP RANGE
PACKAGE
MARKING
QT140-D
QT140-AS
QT150-D
QT150-AS
0 - 70C
-40 - 105C
0 - 70C
-40 - 105C
PDIP-28
SSOP-28
PDIP-28
SSOP-28
QT140
QT140-A
QT150
QT150-A
lQ
13
QT140/150 1.01/1102
lQ
Copyright © 2002 QRG Ltd. All rights reserved.
Patented and patents pending
Corporate Headquarters
1 Mitchell Point
Ensign Way, Hamble SO31 4RF
Great Britain
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939
[email protected]
www.qprox.com
North America
651 Holiday Drive Bldg. 5 / 300
Pittsburgh, PA 15220 USA
Tel: 412-391-7367 Fax: 412-291-1015
The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject
to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order
acknowledgement. QProx, QTouch, QMatrix, QLevel, and QSlide are trademarks of QRG. QRG products are not suitable for medical
(including life-saving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in QRG's
Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in connection
with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and customers are entirely
responsible for their products and applications which incorporate QRG's products.