VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Features • Dual 2x2 Crosspoint Switch • 2.7Gb/s NRZ Data Bandwidth, 2.7GHz Signal Bandwidth • 50Ω Source Terminated Output Driver and Programmable Input Terminations • Single 3.3V Supply, 1W Typical Dissipation • PECL/TTL-Compatible Control Inputs • Power-Down Capability for Unused Outputs • PECL-Compatible High-Speed I/O • Compact 44-Pin PQFP, 10x10mm Package General Description The VSC830 is a monolithic dual 2x2 asynchronous crosspoint switch, designed for critical signal path control and buffering applications, such as loop-back, protection switching, and multi-channel backplane driver/receivers. Signal path delay is tightly matched between each output channel to eliminate the need for delay path compensation when switching between signal sources. The crosspoint function is based on a multiplexer tree architecture. Each 2x2 switch can be considered as a pair of 2:1 multiplexers that share the same inputs. The signal path through each switch is fully differential and delay matched. The signal path is unregistered, so there are no restrictions on the phase, frequency, or signal pattern at each input. Unused outputs can be independently powered off, thereby eliminating power on unused sections (see Design Guide section in this data sheet). The switch control inputs can be configured to be compatible with PECL or TTL levels. The high-speed input and output levels are nominally PECL compatible and capable of interfacing with a wide range of termination schemes. VSC830 Symbol Diagram S1,S2 A1 Y1 A2 Y2 S1,S2 G52192-0, Rev 4.0 05/23/01 A1 Y1 A2 Y2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Functional Block Diagram PEMODE VCC S1A A1A+ A1A- VCCP1A SL 0 Y1A 1 Y1AN TERM_ENABLE_A VEE1A S2A VCCP2A SL A2A+ A2A- 0 Y2A 1 Y2AN VEE2A S1B A1B+ A1B- VCCP1B SL 0 Y1B 1 Y1BN TERM_ENABLE_B VEE1B S2B VCCP2B SL A2B+ A2B- 0 Y2B 1 Y2BN VEE2B Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Functional Description Select As shown in Figure 1, each output can be treated as a 2:1 multiplexer, with the A1 and A2 inputs common to both multiplexers. The select input S1 independently controls the state of the multiplexer that drives output Y1, and select input S2 independently controls the output of Y2. Figure 1: Select Functional Block Diagram S1 S2 A1 Y1 Y2 A2 Table 1 specifies the function of the select inputs. Table 1: Select Function S1 S2 Y1 Y2 0 0 A1 A1 1 0 A2 A1 0 1 A1 A2 1 1 A2 A2 MODE The interface level of the select pins, S1 and S2, can be programmed to either TTL or PECL levels by shorting the MODE pin to either VCC or VEE. Note that the MODE pin must be tied to either VCC or VEE. The function of MODE is specified in Table 2. Table 2: MODE Function MODE G52192-0, Rev 4.0 05/23/01 S1, S2 VEE TTL VCC PECL © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Power-Down Power to each output stage is provided through VCC, VCCP, and VEE. VCC is common to all outputs. To power off unused outputs, tie the respective VEE and VCCP pin to VCC, as shown in Figure 2. Figure 2: Power-Down Mode Example VCC VCCP2A VCCP1A VEE1A “ON” VEE2A “ON” VCCP1B VEE1B “OFF” VCCP2B VEE2B “OFF” Minimum power configuration requires output channel 1A active, so power must be applied to VCCP1A and VEE1A at all times. Programmable input termination Across each differential input (from the + input to the - input) of the VSC830 is a switched 100Ω termination resistor. Using the TERM_ENABLE pin, the termination can be optionally disabled. To enable the input termination, connect the respective TERM_ENABLE pin to VCC. To disable the internal termination, connect TERM_ENABLE to VEE. If unconnected, the TERM_ENABLE pin will self-bias to VEE and disable the internal termination. Independent termination controls are provided for the “A” and “B” switches. Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 AC Characteristics Table 3: AC Timing Symbol Parameter Min Typ Max Units FRATE Signal path data rate 2.7 Gb/s FBW Signal path bandwidth (-3dB) 2.7 GHz TSKW Channel to channel delay skew TCON Switch configuration setup time(1) 50 tR, tF High-speed output rise/fall times, 20% to 80% tjP Signal path added jitter, peak-peak(1) (2) ps 1 ns 150 ps 40 ps 23 NOTES: (1) Tested on a sample basis only, with 2 -1 PRBS data, input signal rise/fall time < 150ps. Value stated in table is added to measurement system jitter. (2) Input signal rise/fall time < 150ps, measured using an alternating 1, 0 pattern. DC Characteristics (All characteristics are over the specified operating conditions) Table 4: Power Supply Symbol Parameter Min Typ Max Units ICC Total VCC(P) supply current 350 mA PD Power dissipation per output (Y1A±, Y2A±, Y1B±, Y2B±) 300 mW PT Total chip power (all outputs powered on) 1.2 W Conditions NOTE: Specified with outputs terminated, 100Ω between true and complement, VCC = 3.45V. Table 5: Select Input Levels—TTL Mode Symbol Parameter Min Typ Max Units 0.8 V 2.0 Conditions VIH Input HIGH voltage (TTL) VIL Input LOW voltage (TTL) V IIH Input HIGH current (TTL) 500 µA VIN = 2.4V IIL Input LOW current (TTL) -500 µA VIN = 0.5V Max Units Table 6: Select Input Levels—PECL Mode Symbol Parameter Min Typ VCC1.0 Conditions VIH Input HIGH voltage (PECL) VIL Input LOW voltage (PECL) VCC1.6 V IIH Input HIGH current (PECL) 500 µA VIN = 2.5V IIL Input LOW current (PECL) -500 µA VIN = 1.5V Max Units V Table 7: Control Inputs Symbol RPEMODE G52192-0, Rev 4.0 05/23/01 Parameter PEMODE pin impedance Min Typ 3100 Conditions Ω © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Table 8: “A” Input Levels (Differential PECL) Symbol VID VICM Parameter Input differential voltage Input common-mode voltage Min Typ Max Units 200 1000 mV VCC1.7 VCC0.9 V Conditions See Note 1 NOTE: (1) Peak-to-peak swing of each side of the differential input. Table 9: “Y” Output Levels (Differential PECL) Symbol Parameter VOD1 Output differential voltage (Data) VOD2 Output differential voltage (Clock) VOCM Output common-mode voltage Min Typ Max Units Conditions 400 700 1000 mV See Note 1 400 550 850 mV See Note 2 VCC1.0 V VCC1.6 NOTES: (1) Peak-peak swing of each side of the differential output. 223-1 PRBS data. (2) Peak-to-peak swing of each side of the differential output. Alternating 1, 0 pattern. Absolute Maximum Ratings Power Supply Voltage (VCC) Potential to GND ..............................................................................-0.5V to +4.0V TTL Input Voltage Applied ................................................................................................... -0.5V to VCC +0.5V ECL Input Voltage Applied .................................................................................................... -0.5V to VCC +0.5V Output Current (IOUT) .................................................................................................................................... 50mA Case Temperature Under Bias (TC) .............................................................................................-55oC to + 125oC Storage Temperature (TSTG)........................................................................................................-65oC to + 150oC NOTE: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Operating Conditions Supply voltage (VEE) .......................................................................................................................................... 0V Supply voltage (VCC) ............................................................................................................................ +3.3V ±5% Supply voltage (VCCP) .......................................................................................................................... +3.3V ±5% Operating Range(1) (T) ..................................................................................................................... 0oC to +85oC NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC830 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Package Pin Descriptions G52192-0, Rev 4.0 05/23/01 VCC S1A A1A- A1A+ VCC TERM_ENABLE_A VCCP1A Y1A+ Y1A- VEE1A VEE1A 44 43 42 41 40 39 38 37 36 35 34 Figure 3: Pin Diagram VCC 1 33 VEE2A S2A 2 32 VEE2A A2A+ 3 31 Y2A+ A2A- 4 30 Y2A- VCC 5 29 VCCP2A PEMODE 6 28 VCC VCCP1B VSC830 20 21 22 Y2B+ VEE2B VEE2B 19 Y2B- VEE1B 18 23 17 11 VCCP2B VCC TERM_ENABLE_B VEE1B 16 Y1B- 24 VCC 25 10 15 9 S1B 14 A1B- A2B- Y1B+ A2B+ 26 13 8 S2B A1B+ 12 7 27 VCC VCC © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Table 10: Pin Identification Page 8 Signal Name Pin(s) Function Description VCC 1, 5, 7, 11, 12, 16, 28, 40, 44 Positive Supply Global supply for chip VEE1A 34, 35 Negative Supply For channel output 1A. Must always be powered on. VEE2A 32, 33 Negative Supply For output 2A. Connect to VCC to power-off. VEE1B 23, 24 Negative Supply For output 1B. Connect to VCC to power-off. VEE2B 21, 22 Negative Supply For output 2B. Connect to VCC to power-off. VCCP1A 38 Positive Supply Output driver supply for channel 1A VCCP2A 29 Positive Supply Output driver supply for channel 2A VCCP1B 27 Positive Supply Output driver supply for channel 1B VCCP2B 18 Positive Supply Output driver supply for channel 2B TERM_ENABLE_A 39 Termination Enable Input termination enable for the “A” switch. Normally low (VEE). Connect to VCC to enable internal 100 ohm termination between AxA+ inputs. TERM_ENABLE_B 17 Termination Enable Input termination enable for the “B” switch. Normally low (VEE). Connect to VCC to enable internal 100Ω termination between AxA+ inputs. PEMODE 6 Control PECL/TTL interface control A1A± 41, 42 PECL Input Channel 1A differential signal input S1A 43 PECL/TTL Input Channel 1A input selector Y1A± 37, 36 PECL Output Channel 1A differential output A2A± 3, 4 PECL Input Channel 2A differential signal input S2A 2 Y2A± 31, 30 PECL/TTL Input Channel 2A input selector PECL Output Channel 2A differential output A1B± S1B 8, 9 PECL Input Channel 1B differential signal input 10 PECL/TTL Input Channel 1B input selector Y1B± A2B± 26, 25 PECL Output Channel 1B differential output 14, 15 PECL Input Channel 2B differential signal input S2B 13 Y2B± 20, 19 PECL/TTL Input Channel 2B input selector PECL Output Channel 2B differential output © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Package Thermal Characteristics The VSC830 is packaged into a standard plastic quad flatpack with an embedded, but unexposed thermal slug. This package adheres to industry-standard EIAJ footprints for a 10x10mm body, 44 lead PQFP. The package construction is as shown in Figure 4. The 44-pin PQFP with embedded slug has the thermal properties shown in Table 11. This package allows the VSC830 to operate with ambient temperatures up to 70oC in still air. Figure 4: Package Cross Reference Die Wire Bond Plastic Molding Compound Lead Insulator Copper Heat Spreader Table 11: 44-Pin PQFP Thermal Resistance Symbol Description Value (oC/W) TA(MAX) (oC) θCA-0 Thermal resistance from case-to-ambient, still air 28.4 50.9 θCA-100 Thermal resistance from case-to-ambient, 100 LFPM air 22.7 57.8 θCA-200 Thermal resistance from case-to-ambient, 200 LFPM air 19.9 61.1 θCA-400 Thermal resistance from case-to-ambient, 400 LFPM air 16.2 65.6 θCA-600 Thermal resistance from case-to-ambient, 600 LFPM air 13.9 68.3 NOTE: TA(MAX) = max case temperature - (max power dissipation • θCA AIRFLOW). G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Package Information 44-Pin PQFP, 10mm x 10mm Package Drawing F G 44 34 1 33 L Item mm Tol. A 2.45 MAX D 2.00 +.10 / -.05 E 0.35 ±.05 F 13.20 ±.25 G 10.00 ±.10 H 13.20 ±.25 I 10.00 ±.10 J 0.88 +.15 / -.10 J1 0.80 +.15 / -.10 K 0.80 BASIC L 3.56 ±.50 DIA. I H 23 11 12 22 10 o TYP D 10 o TYP K 0.30 RAD.TYP. A 0.25 MAX. 0.20 RAD. TYP. 0.17 MAX. 0.25 0 o- 8 o 0.102 MAX. LEAD COPLANARITY J1 J E NOTES: Drawing not to scale. Heat spreader up. All units in mm unless otherwise noted. Package #: 101-299-1 Issue #: 1 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 10 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Ordering Information The order number for this product is formed by a combination of the device number, and package type. VSC830 XX Device Type 2.7Gb/s Asynchronous Dual 2x2 Crosspint Switch Package QZ: 44-Pin PQFP, 10 x 10mm Body Evaluation Boards An evaluation board for the VSC830 is available. Please contact your local sales representative. Notice Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Design Guide Introduction The purpose of this document is to make it easier for system designers to use the VSC830 2.7Gb/s dual 2x2 crosspoint switch. This guide provides guidelines for I/O terminations, power supply decoupling and board layout. Signal Terminations The high-speed inputs (A1A+/-, A1B+/-, A2A+/- and A2B+/-) on the VSC830 are internally terminated with a programmable 100Ω termination between the true and complement input. The input termination can be disabled by connecting the TERM_ENABLE pin to VEE. High impedance internal biasing resistors provide the correct bias voltage at the inputs for AC-coupled applications (Figure 5). Figure 5: High-Speed Input Termination a) Termination Enabled Chip Boundary VCC = 3.3 V CIN ZO 2.0 V 2.0 V R| | = 3.15kΩ (approx.) 100 ZO CIN VEE = GND b) Termination Disabled Chip Boundary VCC = 3.3 V CIN ZO 2.0 V 2.0 V RT = ZO R| | = 3.15 kΩ (approx.) VTT VTT CIN VEE = GND CIN TYP = 0.1µF (capacitor value is selected for data input = 2.7Gb/s) VTT = VCC - 1.3V G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 12 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 The high-speed outputs (Y1A+/-, Y1B+/-, Y2A+/- and Y2B+/-) each consist of a differential pair designed to drive a 50Ω transmission line. The transmission line should be terminated with a 100Ω resistor at the receiver of the downstream device between the true and complement outputs. No connection to a termination voltage is required. The output driver is source terminated to 50Ω on-chip, providing a snubbing of any reflections. Output power can be cut by tying VEE to VCC. In single ended mode, the unused output must be terminated with 50Ω. Some output termination examples are shown in Figures 6 and 7. Figure 6: Examples of High-Speed Output I/O Termination for VSC830 a) AC Termination #1 VCC 50Ω VCC ZO = 50Ω 50Ω 0.1 µF 0.1 µF 50Ω 50Ω VCC VCC b) AC Termination #2 (Internal biasing required for Receiver) VCC 50Ω ZO = 50Ω 0.1 µF 100Ω 0.1 µF 50Ω VCC c) AC Termination #3 VCC 50Ω ZO = 50Ω 0.1 µF 0.1 µF 50Ω 100 pF 50Ω 50Ω VCC G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Figure 7: Examples of High-Speed Output I/O Termination for VSC830 a) Single-Ended AC Termination (Receiver internal biasing required) VCC 50Ω ZO = 50Ω 0.1µF 100Ω 0.1µF 50Ω VCC b) DC Termination VCC 50Ω VCC ZO = 50Ω 50Ω 50Ω 50Ω VCC 0.1µF 0.1µF VCC Power Supply and Layout Considerations The VSC830 is a single supply part, requiring only a 3.3V supply. The location and hook-up of the bypass capacitors is critical to providing the VSC830 with a clean 3.3V power supply. VCC that are adjacent can share a 0.027µF capacitor connected to VEE. Normally the four channel specific VCC pins (VCCP1A, VCCP1B, VCCP2A, VCCP2B) are connected to one common VCC plane. In the same way the four channel specific VEE pins are connected to the common VEE plane. A suggested decoupling schematic for this configuration is shown in Figure 7a. However, a slightly higher signal integrity can be achieved if these pins are treated as different power supplies. In this case, VCCP1A should then be decoupled to VEE1A etc, as shown in Figure 7b. G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 14 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Figure 8: Decoupling Example: Common VCC and VEE Planes VEE VEE 34 35 36 37 38 39 31 4 30 VCC VSC830 Top View Heat Spreader Up 7 VCC VCCP2A 29 VCC 28 VCCP1B 27 8 26 9 25 VEE C1 VEE 22 21 20 19 18 16 15 14 13 12 C1 23 VCCP2B VCC VCC 11 C1 24 10 VCC C1 VEE 40 VCC 32 3 6 C1 33 2 5 VEE 41 VCCS2A 17 C1 VCCP1A 1 VEE 42 VCC C1 VEE 43 C1 44 C1 C1 = 0.027µF VCC = VEE = +3.3V (VEE typically ground) VEE Recommended resistor and capacitor is size 805 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 15 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 Figure 9: Decoupling Example: Separate VCC and VEE Planes VEE 34 35 36 37 38 3 31 4 30 VCC VSC830 Top View Heat Spreader Up 7 VCC VCCP2A 29 VCC 28 VCCP1B 27 8 26 9 25 10 24 C1 VEE C1 C1 VEE2A VEE VEE1B 22 21 20 19 18 16 15 14 13 12 C1 C1 23 VCCP2B VCC VCC 11 VCC C1 VEE 40 VCC 32 6 C1 33 2 5 VEE 41 VCC 17 C1 C1 VCCP1A 1 VEE 42 VCC C1 VEE 43 C1 44 C1 VEE1A 39 VEE C1 VEE VEE2B C1 = 0.027µF VCC = VEE = +3.3V (VEE typically ground) Recommended resistor and capacitor is size 805 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 16 VITESSE SEMICONDUCTOR CORPORATION Data Sheet 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch VSC830 High-Speed Serial I/O Layout Considerations The high-speed serial signals contain digital data at fundamental frequencies up to 2.488GHz clock rate. Given that, in order to preserve the edges of such data sequences, it is necessary to have excellent frequency and phase response up to at least the 3rd harmonic, if not the 7th harmonic. Improved signal quality will result should the reader follow the general design rules below: 1. Keep traces as short as possible. Initial component placement should be very carefully considered. 2. The impedance of the traces must match that of the terminations, connectors and cable(s) in order to reduce reflections and impedance mismatches. Reflections can create standing waves that will increase the signal jitter. 3. Differential transmission line impedance must be maintained at 100Ω. 4. When routing differential pairs, keep the lengths identical for both traces. Differences in trace length translate directly into signal skew and can add to the signal jitter. Remember also that the differential impedance is affected by the separation between the traces. 5. Keep differential pair traces on the same side of the PCB to minimize impedance discontinuity, such as the one caused when using printed-circuit board vias. 6. Eliminate or reduce stubs. 7. Use rounded corners rather than 45° or 90° corners. 8. Keep signal traces far from other signals which might capacitively couple noise into the signals. This includes the other trace of a differential pair or the traces of the parallel PECL or TTL interface. 9. Do not cut up the power or ground planes in an effort to steer current paths. This usually produces more noise, not less. G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 17 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 G52192-0, Rev 4.0 05/23/01 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 18