VITESSE VSC8061FI

VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8061/VSC8062
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
Features
• Serial Data Rate up to 2.5Gb/s
• 16-Bit Wide ECL 100K Compatible Parallel Data
Interface
• Differential High-Speed Data Outputs
• Power Dissipation: VSC8061:2.0W(max),
VSC8062: 1.7W(max)
• Standard ECL Power Supplies: VEE = -5.2V,
VTT = -2.0V
o
o
o
• Differential or Single-Ended High-Speed Data and • Commercial (0 C to +70 C) or Industrial (-40 C
o
to +85 C) Temperature Range
Clock Inputs
• On-Chip Phase Detector (VSC8061 Multiplexer) • Available in 52-Pin Ceramic Leaded Chip Carrier
or 52-Pin Plastic Quad Flat Pack Packages
Functional Description
The VSC8061 and VSC8062 are high-speed interface devices capable of data rates up to 2.5Gb/s. The
devices are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process to achieve highspeed and low power dissipation. For ease of system design using these products, both devices use industrystandard -5.2V and -2V power supplies, and have ECL-compatible I/O for parallel data interfaces. Typical
applications include telecommunication transmission and instrumentation.
VSC8061 Multiplexer
The VSC8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates
a divide-by-16 clock from the high-speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended
ECL compatible inputs (D0...D15) at data rates up to 156Mb/s and bitwise serializes them into a 2.5Gb/s serial
output (DO/DON). The internal timing of the VSC8061 is referenced to the negative going edge of the highspeed clock true input (CLK). This clock is divided by 16 and is provided as an output (CLK16/CLK16N). The
setup and hold time of the parallel inputs (D[0:15]) are specified with respect to the falling edge of CLK16, so
that CLK16/CLK16N can be used to clock the data source of D[0:15]. The on-chip phase detector monitors the
phase relationship between the internally generated divide-by-16 clock and an externally supplied low-speed
reference clock input (DCLK/DCLKN). Phase difference between these two clock signals generates an up or
down output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase
Locked Loop (PLL) to implement a clock multiplication function.
In applications where a 2.5GHz system clock is provided, and the phase detector function is not required, it
is recommended to connect one side of the DCLK/DCLKN input to VTT through a 50Ω resistor. The U and D
output can be left open and unused.
VSC8062 Demultiplexer
The VSC8062 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock
from the high-speed clock input. The demultiplexer accepts a serial data stream input (DI/DIN) at up to 2.5Gb/s
and deserializes it into 16 parallel single-ended ECL compatible outputs (D[0:15]) at data rates up to 156 Mb/s.
The internal timing of the VSC8062 is referenced to the negative going edge of the high-speed clock true input
(CLK). This clock is divided by 16 and provided as an output (CLK16/ CLK16N). The timing parameters of the
parallel data outputs (D[0:15]) are specified with respect to the falling edge of CLK16, so that CLK16/CLK16N
can be used to clock the destination of D[0:15].
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Figure 1: VSC8061 Block Diagram
D0
16:1
D1
Output
Register
Multiplexer
DO
DON
Parallel Data
Receivers
D15
Input
Registers
CLK
CLKN
Timing
Generator
CLK16
CLK16N
Bit Rate Clock
U
Phase
Detector
DCLK
DCLKN
D
Figure 2: VSC8062 Block Diagram
D0
DI
DIN
Input
Register
DeMultiplexer
1:16
D1
Parallel Data
Outputs
D15
Output
Registers
CLK
CLKN
Page 2
Timing
Generator
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
CLK16
CLK16N
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
VSC8061 Multiplexer AC Characteristics (Over recommended operating range)
Figure 3: VSC8061 Multiplexer Waveforms
tCLK
CLK (CLKN)
High-speed differential clock input
tD
CLK16 (CLK16N)
Parallel data clock output
tDSU
D[0:15]
Parallel data inputs
tDH
VALID DATA (1)
VALID DATA (2)
DCLK (DCLKN)
Parallel data clock input
tD
DO (DON)
D0
D1 D2 D3 D4
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
High-speed differential serial data output
Serialized Data
=Don’t care
NOTE:
tD
Table 1: VSC8061 AC Characteristics
Parameter
Description
period(1)
Min
Typ
Max
400
Units
Conditions
tCLK
Clock
ps
tD
CLK16, DCLK period (tCLK x 16)
6.4
tDSU
Parallel data set-up time with respect to CLK16
falling edge
2.0
ns
tDH
Data hold time with respect to CLK16 falling
edge
0.5
ns
tDC
CLK16 duty cycle
40
60
%
tR, tF
DCLK (DCLKN) rise and fall times
1.5
ns
10% to 90%
tR, tF
D[0:15] rise and fall times
2.0
ns
10% to 90%
tR, tF
CLK16 (CLK16N) rise and fall times
0.5
1.0
ns
10% to 90%
tR, tF
DO (DON) rise and fall times
150
165
ps
20% to 80%
15.6
ns
NOTE: (1) Devices are guaranteed to operate to a maximum frequency of 2.5GHz.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
VSC8061 Phase Detector Logic Diagram
The internal phase detector of the VSC8061 compares the phase difference between the internally generated divide-by-16 clock and the DCLK input. If both inputs (CLK16 and DCLK) to the phase detector are in
phase, the U and D outputs will both be low. If the rising edge of CLK16 precedes DCLK, a series of pulses
with pulse widths proportional to the phase difference will be present at the U output. Conversely, if DCLK precedes CLK16, then a series of pulses with widths proportional to the phase difference will be present at the D
output. The other output will remain low. The Phase Detector ignores phase differences for falling edges. This
circuitry is useful for implementing a Clock Multiplier Unit (CMU) function with the VSC8061. For example,
the DLCK can be the system reference clock at the parallel data rate. An external Voltage Controlled Oscillator
(VCO) at 16x the frequency of the reference clock can be used as the CLK input for the VSC8061. The phase
detector outputs (U and D) can then be used by an external integrator to generate an output that controls the
VCO. The generated 16x clock from the VCO will be phase-locked to the reference clock.
Figure 4: VSC8061 Phase Detector Logic Diagram
U
CLK16
R Q
S
S
R Q
DCLK
D
CLK16
~
~ ~
~
Figure 5: Phase Detector Input and Output Waveforms
U
D
Page 4
~
~ ~
~
DCLK
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
VSC8062 Demultiplexer AC Characteristics (Over recommended operating range)
Figure 6: VSC8062 Timing Diagram
CLK (CLKN)
tCLK
High-speed differential clock input
DI (DIN)
High-speed serial data input
tD
CLK16
Parallel data clock output
tD
Demultiplexed Parallel
Data Outputs
tBD
D0
D1
D15
Table 2: VSC8062 AC Characteristics
Parameter
Description
Min
Typ
Max
Units
tCLK
Clock period(1)
400
ps
tD
BYTE CLK16 period (tCLK x 16)
6.4
ns
tDSU
CLK16 falling edge output to valid data
1.0
tDH
t SU + t H
Phase Margin =  1 – ------------------ × 360°
t CLK 
Serial data phase timing margin with respect to
high-speed clock(2)
180(3)
3.0
Conditions
ns
degrees
NOTES: (1) If tCLK changes, all remaining parameters change as indicated by the equations.
(2) tSU and tH are setup and hold times of the serial data input register.
(3) At tCLK = 400ps.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
DC Characteristics
Table 3: ECL Inputs and Outputs
(Over recommended operating conditions with internal V REF, VCC = GND, output load = 50Ω to -2.0V).
Parameter
Description
Min
Typ
Max
Units
Conditions
VOH
Output HIGH voltage
-1100
-700
mV
VIN = VIH (max) or VIL
(min)
VOL
Output LOW voltage
VTT
-1750
mV
VIN = VIH (max) or VIL
(min)
VIH
Input HIGH voltage
-1040
-600
mV
Guaranteed HIGH signal
for all inputs
VIL
Input LOW voltage
VTT
-1600
mV
Guaranteed LOW signal
for all inputs
V
Output load 50Ω to VTT
0.800
1.2
V
AC-coupled
Typ
Max
Units
VSC8061
260
mV
VSC8062
220
mV
VSC8061
260
mV
VSC8062
230
mV
VSC8061
2.0
W
VSC8062
1.7
W
Max
Units
Conditions
V
Output load, 50Ω to -2.0V
∆VECLOUT
Output voltage swing
0.850
∆VECLIN
Input voltage swing
0.600
Note: Differential ECL output pins must be terminated identically.
Table 4: Power Dissipation
(Over recommended operating conditions, V CC= GND, outputs open circuit)
Parameter
IEE
ITT
PD
Description
Power supply current from VEE
Power supply current from VTT
Power dissipation
Min
Conditions
Table 5: High-Speed Input and Output Specifications
(Over recommended operating conditions, V CC = GND, output load = 50Ω to -2.0V)
Parameter
Description
Min
Typ
0.7
0.9
∆VHSOUT
Output voltage swing
∆VHSIN
Input voltage swing
See Table 6
tR, tF
Input voltage rise and fall time (high-speed)
0.2
1.5
AC-coupled
ns
Same for all data rates; no
worse than sine wave at
max speed
NOTES: (1) Built-in references generator, the high-speed inputs are designed for AC-coupling.
(2) If a high-speed input is driven single-ended, a capacitor should be connected between the unused high-speed or complement
input and VTT (see Figures 7 and 8).
Page 6
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8061/VSC8062
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
Absolute Maximum Ratings(1)
Power Supply Voltage (VTT) ............................................................................................................ -3.0V to 0.5V
Power Supply Voltage (VEE) ................................................................................................. VTT + 0.7V to -7.0V
Input Voltage Applied (2) (VECLIN) .................................................................................................. -2.5V to 0.5V
High-Speed Input Voltage Applied (2) (VHSIN) ............................................................... VEE-0.7V to VCC +0.7V
Output Current, IOUT (DC, output HI) ........................................................................................................ -50mA
Case Temperature Under Bias (TC)................................................................................................ -55oC to 125oC
Storage Temperature (TSTG) .......................................................................................................... -65oC to 150oC
NOTES: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may
affect device reliability.
(2) VTT must be applied before the magnitude of any input signal voltage (|VIN|, |VHSIN|) can be greater than |VTT - 0.5V|.
Recommended Operating Conditions
Power Supply Voltage (VTT) .................................................................................................................-2.0V ± 5 %
Power Supply Voltage (VEE) .................................................................................................................-5.2V ± 5 %
Operating Temperature Range(1) (T)............................(Commercial) 0oC to +70oC, (Industrial) -40oC to +85oC
NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature.
ESD Ratings
For performance considerations, minimum ESD protection is provided for the high-speed input pins. Therefore, proper procedures should be used when handling these products. The VSC8061/8062 are rated to the following ESD voltages based on the human body model:
1. All high-speed input pins are rated at or above 500V.
2. All other pins are rated at or above 2000V.
The above ratings apply to both “F” and “QH” packages.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Coupling for Inputs
Figure 7: AC-Coupling for DCLK, DCLKN Inputs
Chip Boundary
VCC = GND
ZO
CIN
DCLK
-1.32V
-1.32V
RT = ZO
R| | = 1kΩ
VTT
CSE
DCLKN
VTT
VTT = -2V
CIN typ = 0.1µF
CSE typ = 0.1µF for single-ended applications
(Capacitor values are selected for DCLK = 155Mb/s.)
DCLK, DCLKN Inputs
Internal biasing will position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differentially. Figure 7 shows the configuration for a single-ended, AC-coupling operation. In the case of direct
coupling and single-ended input, it is recommended that a stable VREF for ECL levels be used for the complementary input.
High-Speed Clock and Serial Data Inputs
It is recommended that all high-speed clock and serial data inputs (CLK/CLKN for the VSC8061; DI/DIN
and CLK/CLKN for the VSC8062) be AC-coupled. Figure 8 shows the configuration for a single-ended ACcoupling operation.
In most situations, these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. The following is to assist in this application.
All serial data and clock inputs have the same circuit topology, as shown in Figure 8. The reference voltage
is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part,
the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended the user provide an
external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value as indicated in the table and can be connected to
either side of the differential gate.
Page 8
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Table 6: High-Speed Clock and Serial Data Inputs
Product
Input
Reference
Min (p-p)
Max (p-p)
VSC8061
DCLK, DCLKN
-1.32V
600mV
1.2V
VSC8061
CLK, CLKN
-3.5V
600mV
1.2V
VSC8062
DI, DIN
-3.5V
250mV
1.2V
VSC8062
CLK, CLKN
-3.5V
250mV
1.2V
Figure 8: High-Speed Clock and Serial Data Inputs
Chip Boundary
VCC = GND
ZO
CIN
CLK,
DI
-3.5V
-3.5V
RT = ZO
R| | = 1.3kΩ
VTT
CSE
CLKN,
DIN
VTT
VEE = -5.2V
CIN typ = 100pF
CSE typ = 100pF for single-ended applications
(Capacitor values are selected for DI = 2.5Gb/s.)
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Package Pin Descriptions
D4
VCC
D3
D2
NC
NC
TEST
TEST
NC
VCC
U
D
VEE
VCC
DCLKN
DCLK
CLK16
VCC
NC
CLKN
D14
D15
VCC
TEST
TEST
NC
VEE*
NC
NC
NC
DO
VCC
DON
NC
NC
NC
CLK
CLK16N
VEE
NC
NC
D15
VTT
D13
NC
NC
NC
NC
VEE*
NC
CLK
CLKN
DIN
VCC
DI
NC
NC
NC
NC
D5
NC
VTT
NC
D6
VCC
D7
NC
VCC
CLK16
D8
VTT
D9
39 38 37 36 35 343332 31 30 29 28 27
26
40
25
41
24
42
23
43
22
44
21
45
VSC8062
46
20
Heat Sink Side
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 1011 12 13
CLK16N
D10
D14
NC
D0
D10
VCC
D9
VCC
D12
VCC
VCC
D8
D13
D7
NC
VTT
D1
D6
NC
D1
D5
D11
VCC
D12
D4
NC
D3
39 38 37 36 35 34 33 32 31 3029 2827
26
40
25
41
24
42
23
43
22
44
VSC8061
21
45
20
46
Heat Sink Side
19
47
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 1213
D11
D2
NC
Heat Sink Up
Top View
D0
Figure 9: VSC8061/8062 F (52-Pin LDCC) Pin Diagrams
*Heat sink is electrically connected to pin 23 and should be biased to VEE.
Page 10
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Figure 10: VSC8061/8062 QH (52-Pin PQFP) Pin Diagrams
VEE*
VCC
NC
VEE
NC
NC
VEE
DO
DON
VEE
VEE
NC
NC
Heat Spreader Up
Top View
52
1
VITESSE
VSC8061QH
VCC
CLK
CLKN
VEE
VTT
CLK16
CLK16N
D15
D14
D13
D12
D11
VCC
VEE*
VCC
NC
VEE
CLK
CLKN
VEE
DIN
DI
VEE
VEE
NC
NC
VTT
D1
D2
D3
D4
D5
D6
VTT
D7
D8
D9
D10
VTT
VCC
VTT
TEST
TEST
VTT
NC
U
D
DCLK
DCLKN
D0
VCC
VTT
11
52
VITESSE
VSC8062QH
VCC
NC
NC
VEE
VTT
NC
NC
NC
CLK16
CLK16N
D0
D1
VCC
VTT
D11
D10
D9
D8
D7
D6
VTT
D5
D4
D3
D2
VTT
VCC
VTT
NC
TEST
VTT
NC
TEST
D15
D14
D13
D12
VCC
VTT
*Heat spreader is electrically connected to pin 52 and should be biased to VEE.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Table 7: VSC8061 Pin Identifications
Pin Number
QH Package
Pin number
F Package
Signal
Name
I/O
Level
38
13
CLK
I
HS
High-speed clock true(1)
37
12
CLKN
I
HS
High-speed clock, complement (1)
9
34
DCLK
I
ECL
Data clock true(1)
10
35
DCLKN
I
ECL
Data Clock complement(1)
34
9
CLK16
O
ECL
Clock divide-by-16, true
33
8
CLK16N
O
ECL
Clock divide-by-16, complement
11, 15-20, 2225, 28-32
1-3, 5, 6,
8-42, 44, 45,
47, 48, 50, 51
D[0:15]
I
ECL
Parallel data inputs
45
19
DO
O
HS
Serial data output, true
44
17
DON
O
HS
Serial data output, complement
7
31
U
O
ECL
Phase detector output - up frequency
8
32
D
O
ECL
Phase detector output - down frequency
1, 12, 27,
39, 51
4, 10, 18, 30,
36, 43, 49
VCC
Pwr
Most positive power supply
2, 5, 13, 14, 21,
26, 35
7,46
VTT
Pwr
DCFL negative power supply
36, 42, 43,
46, 49
33
VEE
Pwr
SCFL negative power supply
6, 40, 41, 47,
48, 50
11, 14-16,
20-22, 24-26,
29, 37, 52
NC
Do not connect, leave open
3, 4
27, 28
Test
Test inputs. Used in factory for testing, connect to
VTT through a resistor
52
23
VEE
Pwr
Description
Heat sink bias, connect to VEE
NOTE: (1) Can be used single-ended.
Page 12
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Table 8: VSC8062 Pin Identifications
Pin Number
QH Package
Pin Number
F Package
Signal
Name
I/O
Level
48
21
CLK
I
HS
High-speed clock, true(1)
47
20
CLKN
I
HS
High-speed clock, complement(1)
44
17
DI
I
HS
Serial data input, true(1)
45
19
DIN
I
HS
Serial data input, complement(1)
31
8
CLK16
O
ECL
Parallel data clock (high-speed clock divide-by16), true
30
6
CLK16N
O
ECL
Parallel data clock (high-speed clock divide-by16), complement
8-11, 15-20,
22-25, 28, 29
3, 5, 31, 32,
34, 35, 39-42,
44, 45, 47, 48,
50, 51
D[0:15]
O
ECL
Parallel data outputs
1, 12, 27,
39, 51
4, 10, 18, 30,
36, 43, 49
VCC
Pwr
Most positive power supply
2, 5, 13, 14, 21,
26, 35
7, 46
VTT
Pwr
DCFL negative power supply
36, 42, 43,
46, 49
33
VEE
Pwr
SCFL negative power supply
3, 6, 32-34, 37,
38, 40, 41, 50
1, 2, 9, 11-16,
22, 24-27, 37,
38, 52
NC
4, 7
28, 29
Test
Pwr
Test inputs. Used in factory for testing, connect
to VTT through a resistor
52
23
VEE*
Pwr
Heat sink bias, connect to VEE
Description
Do not connect, leave open
NOTE: (1) Can be used single-ended.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Package Information
52-Pin Ceramic LDCC (F) Package
B
A
HEAT SINK SIDE
PACKAGE IS
CAVITY DOWN
52
E
45o
K
I
J
C
L
D
M
1
NOTES:
Drawing not to scale.
All units in mm unless otherwise noted.
N
Packages: Ceramic (alumnia)
Heat Sinks: Copper tungsten
Leads: Alloy 42 with gold plating
O
Item
mm (Min/Max)
in (Min/Max)
Item
mm (Min/Max)
in (Min/Max)
A
18.54/19.56
B
1.02/1.52
0.730/0.770
I
0.41/0.61
0.016/0.024
0.040/0.060
J
2.03/2.79
0.080/0.110
C(1)
15.49/16.51
0.610/0.650
K(1)
0.09/0.24
0.003/0.009
D(1)
15.24 TYP
0.600 TYP
L
4.57/5.34
0.180/0.210
E
1.27 TYP
0.050 TYP
M
27.69/30.22
1.090/1.190
N
0.36/0.56
0.014/0.022
O
1.75/1.90
0.069/0.075
NOTE: (1) At package body.
Page 14
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
52 Pin PQFP (QH) Package
F
G
Item
52
mm
Tol.
40
1
39
L
I
13
H
27
14
26
10o
A
2.35
MAX
D
2.00
+.10 / -.05
E
0.35
±.05
F
17.20
±.25
G
14.00
±.10
H
17.20
±.25
I
14.00
±.10
J
0.88
+.15 / -.10
J1
0.80
+.15 / -.10
K
1.00
BASIC
L
5.84
±.50 DIA.
TYP
D
A
100 TYP
K
0.30 RAD. TYP.
A
STANDOFF
0.25 MAX.
0.20 RAD. TYP.
0.17 MAX.
0.25
NOTES:
0o- 8o
0.102 MAX. LEAD
COPLANARITY
J1
E
J
Drawing not to scale.
Heat spreader up.
All units in mm unless otherwise noted.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 15
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Thermal Considerations
The VSC8061 and VSC8062 are available in ceramic LDCC and thermally enhanced plastic quad flatpacks. These packages have been enhanced to improve thermal dissipation through low thermal resistance paths
from the die to the exposed surface of the heat spreader. The thermal resistance of the two packages is shown in
the following table
Table 9: Thermal Resistance
Symbol
Description
F Pack
QH Pack
Units
°C/W
θJC
Thermal resistance from junction-to -case.
1.3
2.1
θCA
Thermal resistance from case-to-ambient still air including
conduction through the leads.
18.5
30.0
°C/W
Thermal Resistance with Airflow
Shown in Table 10 is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the
device multiplied by the thermal resistance.
Table 10: Thermal Resistance with Airflow
Airflow
θCA for F Package
θCA for QH Package
Units
100 lfpm
15.9
24
oC/W
200 lfpm
14.9
21
oC/W
300 lfpm
14.2
19
oC/W
500 lfpm
13.3
15
oC/W
Thermal Resistance with Heat Sink
The determination of appropriate heat sink to use is as shown below, using the VSC8061 in QH package as
an example.
Figure 11: VSC8061 in QH Package
TA
θSA
θCS
Page 16
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
The worst-case temperature rise from case to ambient is given by the equation:
∆T = P ( MAX ) ( θSA + θ CS )
where:
θSA
θCS
ΤA(MAX)
ΤC(MAX)
∆T
P(MAX)
=
=
=
=
=
=
Theta sink-to-ambient
Theta case-to-sink
Air temperature, user supplied (typically +55o C)
Case temperature (+85oC for Industrial range)
TC - TA
Power (2.0 W for VSC8061)
TC – TA
∆T
∴P = ------- = --------------------------Σθ
θ SA + θ CS
∆T
θ SA = ------- – θ CS
P
Ιf TA = 55o C and θCS (user supplied) is typically 0.6o C/W,
( 85 – 55 )°C
θ SA = ----------------------------- – 0.6°C ⁄ W
2W
θ SA = 14.4°C ⁄ W
Therefore, to maintain the proper case and junction temperature, a heat sink with a θSA of 14.4oC/W or less
must be selected at the appropriate air flow.
NOTE: The heat spreader is tied to VEE in both the VSC8061 and VSC8062.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Figure 12: Data Eye From Serial Output of VSC8061 in QH Package (D0/D0N)
Amplitude: 200 mV/div
Time Scale: 50 ps/div
Data Rate: 2.5 Gb/s
Figure 13: Measurement Setup
2.5Gb/s
231
Bit Error
16 Channels
at 155Mb/s
- 1 PRB Data
D0
D1
1:16
De-serializer
Rate Tester
D0
D1
D0
VSC8061
D0N
D15
D15
TEK CSA803
Signal Analyzer
Page 18
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8061/VSC8062
Ordering Information
The order number for this product is formed by a combination of the device number, package type, and the
operating temperature range.
VSC80XX
Device Type
VSC8061: 2.5Gb/s 16-bit Multiplexer
VSC8062: 2.5Gb/s 16-bit Demultiplexer
FC
Package and Temperature
FC: 52 Pin Ceramic Leaded Chip Carrier (LDCC),
0°C ambient to +70°C case
FI: 52 Pin Ceramic Leaded Chip Carrier (LDCC),
-40°C ambient to +85°C case
QH: 52-Pin Plastic Flat Quad Pack (PFQP),
0°C ambient to +85°C case
Notice
Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be
available as described or will be suitable for or will accomplish any particular task.
Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
G52069-0, Rev 4.3
05/11/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 19
VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
Page 20
Data Sheet
VSC8061/VSC8062
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
G52069-0, Rev 4.3
05/11/01