MC10H181 4−Bit Arithmetic Logic Unit/ Function Generator The MC10H181 is a high−speed arithmetic logic unit capable of performing 16 logic operations and 16 arithmetic operations on two four−bit words. Full internal carry is incorporated for ripple through operation. Arithmetic logic operations are selected by applying the appropriate binary word to the select inputs (S0 through S3) as indicated in the tables of arithmetic/logic functions. Group carry propagate (PG) and carry generate (GG) are provided to allow fast operations on very long words using a second order look−ahead. The internal carry is enabled by applying a low level voltage to the mode control input (M). When used with the MC10H179, full−carry look−ahead, as a second order look−ahead block, the MC10H181 provides high−speed arithmetic operations on very long words. This 10H part is a functional/pinout duplication of the standard MECL 10K family part with 100% improvement in propagation delay and no increase in power supply current. • Improved Noise Margin, 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K − Compatible http://onsemi.com MARKING DIAGRAMS 24 CDIP−24 L SUFFIX CASE 758 MC10H181L AWLYYWW 1 24 PDIP−24 P SUFFIX CASE 724 MC10H181P AWLYYWW 1 1 PLCC−28 FN SUFFIX CASE 776 A WL YY WW 10H181 AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 8 1 Package Shipping MC10H181L CDIP−24 15 Units/Rail MC10H181P PDIP−24 15 Units/Rail MC10H181FN PLCC−28 37 Units/Rail Publication Order Number: MC10H181/D MC10H181 S3 13 LOGIC DIAGRAM S2 15 S1 17 S0 14 2 F0 B0 20 A0 21 3 F1 B1 19 A1 18 7 F2 B2 11 A2 16 6 F3 B3 9 8 PG A3 10 4 GG 5 Cn+4 Cn 22 M 23 VCC1 = Pin 1 VCC2 = Pin 24 VEE = Pin 12 http://onsemi.com 2 MC10H181 FUNCTION SELECT TABLE LOGIC DIAGRAM Function Select S3 S2 S1 S0 13 15 17 14 S0 S1 21 A0 20 B0 18 A1 19 B1 16 A2 11 B2 10 A3 9 B3 22 Cn 23 M S2 Logic Functions M is High C = D.C. F Arithmetic Operation M is Low Cn is low F L L L L F=A L L L H F=A+B F=A F = A plus (A • B) L L H L F=A+B F = A plus (A • B) L L H H F = Logical “1” L H L L F=A•B F = A times 2 F = (A + B) plus 0 S3 F0 2 L H L H F=B F1 3 L H H L F=AB F = A plus B L H H H F=A+B F = A plus (A + B) F2 7 H L L L F=A•B F = (A + B) plus 0 F3 6 H L L H F=AB F = A minus B minus 1 H L H L F=B F = (A + B) plus (A • B) GG 4 H L H H F=A+B PG 8 H H L L F = Logical “0” H H L H F=A•B F = (A • B) minus 1 Cn+4 5 H H H L F=A•B F = (A • B) minus 1 H H H H F=A F = (A + B) plus (A • B) F = A plus (A + B) F = minus 1 (two’s complement) F = A minus 1 DIP PIN ASSIGNMENT VCC1 1 24 VCC2 F0 2 23 M F1 3 22 CN GG 4 21 A0 CN + 4 5 20 B0 F3 6 19 B1 F2 7 18 A1 PG 8 17 S1 B3 9 16 A2 A3 10 15 S2 B2 11 14 S0 VEE 12 13 S3 Pin assignment is for Dual−in−Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). MAXIMUM RATINGS Symbol Rating Unit VEE Power Supply (VCC = 0) Characteristic −8.0 to 0 Vdc 0 to VEE Vdc 50 100 mA 0 to +75 °C −55 to +150 −55 to +165 °C °C VI Input Voltage (VCC = 0) Iout Output Current− Continuous − Surge TA Operating Temperature Range Tstg Storage Temperature Range− Plastic − Ceramic http://onsemi.com 3 MC10H181 ELECTRICAL CHARACTERISTICS (VEE = −5.2 V ±5.0%) (See Note 1.) 0° Characteristic Power Supply Current +25° +75° Symbol Min Max Min Max Min Max Unit IE − 159 − 145 − 159 mA − − − − − 720 405 515 475 465 − − − − − 450 255 320 300 275 − − − − − 450 255 320 300 275 Input Current High Pin 22 Pins 14,23 Pins 13,15,17 Pins 10,16,18,21 Pins 9,11,19,20 IinH Input Current Low Pins 9−11, 13−22 IinL 0.5 − 0.5 − 0.3 − μA High Output Voltage VOH −1.02 −0.84 −0.98 −0.81 −0.92 −0.735 Vdc Low Output Voltage VOL −1.95 −1.63 −1.95 −1.63 −1.95 −1.60 Vdc High Input Voltage VIH −1.17 −0.84 −1.13 −0.81 −1.07 −0.735 Vdc Low Input Voltage VIL −1.95 −1.48 −1.95 −1.48 −1.95 −1.45 Vdc μA 1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50−ohm resistor to −2.0 volts. AC PARAMETERS AC Switching Characteristics 0°C Characteristic +25°C +75°C Symbol Input Output Conditions Min Max Min Max Min Max Unit Propagation Delay Rise Time, Fall Time t+ +, t− − t+, t− Cn Cn Cn+4 Cn+4 A0,A1,A2,A3 A0,A1,A2,A3 0.7 0.6 2.0 2.0 0.7 0.6 2.0 2.0 0.7 0.7 2.2 2.2 ns ns Propagation Delay t+ +, t+ −, t− +, t− − t+, t− Cn Cn Cn F1 F1 F1 A0 1.0 0.7 3.0 2.2 1.0 0.7 3.0 2.2 1.2 0.7 3.3 2.4 Rise Time, Fall Time t+ +, t+ −, t− +, t− − t+, t− A1 A1 A1 F1 F1 F1 1.5 0.7 3.7 2.0 1.5 0.7 3.7 2.0 1.6 0.7 4.0 2.2 Propagation Delay Rise Time, Fall Time t+ +, t− − t+, t− A1 A1 PG PG S0,S3 S0,S3 1.5 0.9 3.7 2.4 1.5 0.9 3.7 2.4 1.6 0.9 4.0 2.6 ns ns Propagation Delay Rise Time, Fall Time t+ +, t− − t+, t− A1 A1 GG GG A0,A2,A3,Cn A0,A2,A3,Cn 1.5 0.7 3.7 2.2 1.5 0.7 3.7 2.2 1.6 0.7 3.9 2.4 ns ns Propagation Delay Rise Time, Fall Time t+ −, t− + t+, t− A1 A1 Cn+4 Cn+4 A0,A2,A3,Cn A0,A2,A3,Cn 1.5 0.5 3.6 2.0 1.5 0.5 3.6 2.0 1.6 0.5 3.9 2.2 ns ns Propagation Delay Rise Time, Fall Time t+ +, t− + t+, t− B1 B1 F1 F S3,Cn S3,Cn 2.0 0.7 4.5 2.3 2.0 0.7 4.5 2.3 2.1 0.7 4.8 2.5 ns ns Propagation Delay Rise Time, Fall Time t+ +, t− − t+, t− B1 B1 PG PG S0,A1 S0,A1 1.5 0.7 3.8 2.2 1.5 0.7 3.8 2.2 1.6 0.7 4.0 2.4 ns ns Propagation Delay Rise Time, Fall Time t+ +, t− − t+, t− B1 B1 GG GG S3,Cn S3,Cn 1.5 0.7 3.7 2.2 1.5 0.7 3.7 2.2 1.6 0.7 4.0 2.4 ns ns Propagation Delay Rise Time, Fall Time t+ −, t− + t+, t− B1 B1 Cn+4 Cn+4 S3,Cn S3,Cn 2.0 0.5 4.0 2.0 2.0 0.5 4.0 2.2 2.1 0.5 4.3 2.2 ns ns Propagation Delay Rise Time, Fall Time t+ +, t+ − t+, t− M M F1 F1 − − 1.5 0.8 4.2 2.3 1.5 0.8 4.2 2.3 1.6 0.8 4.5 2.5 ns ns Propagation Delay Rise Time, Fall Time t+ −, t− + t+, t− S1 S1 F1 F1 A1,B1 A1,B1 1.5 0.7 4.5 2.0 1.5 0.7 4.5 2.0 1.6 0.7 4.8 2.2 ns ns Propagation Delay Rise Time, Fall Time t− +, t+ − t+, t− S1 S1 PG PG A3,B3 A3,B3 1.5 0.7 4.0 2.0 1.5 0.7 4.0 2.2 1.6 0.7 4.3 2.4 ns ns Propagation Delay Rise Time, Fall Time t+ −, t− + t+, t− S1 S1 Cn+4 Cn+4 A3,B3 A3,B3 1.5 0.7 4.1 2.2 1.5 0.7 4.1 2.2 1.6 0.7 4.4 2.4 ns ns Propagation Delay Rise Time, Fall Time t+ −, t− + t+, t− S1 S1 GG GG A3,B3 A3,B3 1.3 0.5 4.5 3.2 1.3 0.5 4.5 3.2 1.4 0.5 4.8 3.4 ns ns Rise Time, Fall Time Propagation Delay ns ns † Logic high level (+1.11 Vdc) applied to pins listed. All other input pins are left floating or tied to +0.31 Vdc. VCC1 = VCC2 = +2.0 Vdc, VEE = −3.2 Vdc http://onsemi.com 4 MC10H181 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE D −N− 0.007 (0.180) B Y BRK T L−M M 0.007 (0.180) U M N S T L−M S S N S D Z −M− −L− W 28 D X V 1 G1 A 0.007 (0.180) R 0.007 (0.180) C M M T L−M T L−M S S N N S 0.007 (0.180) H G J S S N M T L−M S N S K1 0.004 (0.100) −T− SEATING K PLANE F VIEW S G1 T L−M N S S E S T L−M S VIEW D−D Z 0.010 (0.250) 0.010 (0.250) 0.007 (0.180) VIEW S S NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 http://onsemi.com 5 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10_ 0.410 0.430 0.040 −−− MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10_ 10.42 10.92 1.02 −−− M T L−M S N S MC10H181 PACKAGE DIMENSIONS CDIP−24 L SUFFIX CERAMIC DIP PACKAGE CASE 758−02 ISSUE A L B 24 13 1 12 P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. J −A− DIM A B C D F G J K L N P N C SEATING PLANE −T− K G D 24 PL 0.25 (0.010) F M T A PDIP−24 P SUFFIX PLASTIC DIP PACKAGE CASE 724−03 ISSUE D M −A− 24 13 1 12 L C NOTE 1 K SEATING PLANE G M N E J F D 24 PL 0.25 (0.010) M T B M 24 PL 0.25 (0.010) M T A MILLIMETERS MIN MAX 31.50 32.64 7.24 7.75 4.07 5.08 0.38 0.53 1.14 1.57 2.54 BSC 0.20 0.33 2.54 4.19 7.62 7.87 0.51 1.27 9.14 10.16 NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. −B− −T− INCHES MIN MAX 1.240 1.285 0.285 0.305 0.160 0.200 0.015 0.021 0.045 0.062 0.100 BSC 0.008 0.013 0.100 0.165 0.300 0.310 0.020 0.050 0.360 0.400 M DIM A B C D E F G J K L M N INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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