Product Specification PE4309 50 Ω RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHz Product Description The PE4309 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Features • Best in class 2.0 kV HBM ESD tolerance • Low Insertion Loss: 1.6 dB typical • Attenuation: 0.5 dB steps to 31.5 dB • High Linearity: Typical 52 dB IP3 • Best in Class Attenuation accuracy • Parallel programming interface • Single supply, 3V to 5V operation • Standard 3V or 5V CMOS control logic independent of supply voltage • Very low power consumption • RoHS-compliant 24-lead 4x4 mm QFN Figure 1. Functional Schematic Diagram Figure 2. Package Type This product is a high linearity, 6-bit RF Digital Step Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5 dB steps. The Peregrine 50Ω RF DSA provides a parallel CMOS control interface and it operates on 3-volt to 5-volt supply. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. This Peregrine DSA is available in a 4x4 mm 24 lead QFN footprint with an exposed ground paddle. 4x4 mm 24-Lead QFN Switched Attenuator Array RF Input Parallel Control RF Output 6 Control Logic Interface Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V - 5.0 V Parameter Test Conditions4 Frequency Operation Frequency Any Bit or Bit Combination Any Bit or Bit Combination 0.5 - 7.5 dB States 3 8.0 - 15.5 dB States 3 16.0 - 31.5 dB States3 1 dB Compression2 Input IP31 Two-tone inputs +18 dBm Notes: 1. 2. 3. 4. 50% of control voltage to 90% of final attenuation level Maximum Units 4000 MHz DC - 2.2 GHz 2.2 - 4.0 GHz - 1.6 2.2 2 3.4 dB dB DC ≤ 1.0 GHz 1.0 < 2.2 GHz 2.2 < 3.8 GHz 2.2 < 3.8 GHz 2.2 < 3.8 GHz - 0.15 0.7 1.2 ±(0.10 + 3% of atten setting), not to exceed +0.20 dB ±(0.15 + 3% of atten setting) - dB dB dB dB dB 1 MHz - 2.2 GHz 2.2 - 4.0 GHz 30 - 32 32 - dBm dBm 1 MHz - 2.2 GHz 2.2 - 4.0 GHz - 52 45 - dBm dBm 15 10 20 20 - dB dB - - 1 µs DC - 2.2 GHz 2.2 - 4.0 GHz Return Loss Switching Speed Typ DC Insertion Loss Attenuation Accuracy Min Device Linearity will begin to degrade below 5 MHz. Note Absolute Maximum in Table 4. See Figures 12 and 13 for typical attenuation error. Measurements made in a 50 ohm system (see Figure 4, Test Circuit Block Diagram). Resistors (R2, R3, R5, R6, R7) with a value of 10K-ohm are used to decouple the RF path from the control inputs. Document No. 70-0218-06 │ www.psemi.com ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 9 PE4309 Product Specification C16 C8 Table 3. Operating Ranges Parameter VDD Power Supply Voltage 19 21 C2 22 20 C1 23 C4 C 0.5 24 Figure 3. Pin Configuration (Top View) N/C 1 18 N/C VDD 2 17 N/C IDD Power Supply Current N/C 3 16 N/C PIN Input power (50Ω) RF1 4 15 RF2 N/C 5 14 N/C ACG 6 13 ACG Max Units 3.0 3.3 5.5 V 100 250 µA +24 dBm Parameter/Conditions Min Max Units Power supply voltage -0.3 6.0 V VI Voltage on any DC input -0.3 6.0 V TST Storage temperature range -65 150 °C TOP Operating temperature range -40 85 °C PIN Input power (50Ω) 30 dBm 12 Symbol VDD Table 2. Pin Descriptions Pin No. Pin Name 1 N/C No Connect 2 VDD Power supply pin 3 N/C No Connect 4 RF1 RF port 5 N/C5 No Connect 6 ACG6 AC Ground connection 7 ACG6 AC Ground connection 8 ACG6 AC Ground connection 9 ACG6 AC Ground connection 10 ACG6 AC Ground connection 11 ACG6 AC Ground connection 7 Typ Table 4. Absolute Maximum Ratings N/C 10 11 ACG ACG 9 ACG 8 ACG ACG 7 Exposed Ground Paddle Min Description No Connect ESD voltage (Human Body Model) VESD 2000 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 4. 12 N/C 13 ACG6 AC Ground connection Latch-Up Avoidance 14 N/C5 No Connect 15 RF2 RF port Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. 16 N/C5 No Connect 17 N/C5 No Connect 18 N/C5 No Connect 19 C16 Attenuation control bit, 16 dB 20 C8 Attenuation control bit, 8 dB 21 C4 Attenuation control bit, 4 dB 22 C2 Attenuation control bit, 2 dB 23 C1 Attenuation control bit, 1 dB 24 C0.5 Attenuation control bit, 0.5 dB Paddle GND Ground for proper operation Notes: 5. For improved RF performance these No Connect pins can be connected to RF ground. 6. Pins can either be grounded directly or through coupling capacitors 7. Pin can either be grounded or No Connect Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 9 V Table 5. Control Voltage State Bias Condition Low 0 to +1.0 Vdc at 2 µA (typ) High +2.0 to +5 Vdc at 10 µA (typ) The standard 3V or 5V CMOS control logic is independent of supply voltage. Table 6. Truth Table C16 C8 C4 C2 C1 1 1 1 1 1 1 Reference Loss (IL) 1 1 1 1 1 0 0.5 dB 1 1 1 1 0 1 1 dB 1 1 1 0 1 1 2 dB 1 1 0 1 1 1 4 dB 1 0 1 1 1 1 8 dB 0 0 1 0 1 0 1 0 1 0 1 0 16 dB 31.5 dB Document No. 70-0218-06 C0.5 Attenuation State │ UltraCMOS™ RFIC Solutions PE4309 Product Specification Figure 4. Test Circuit Block Diagram Peregrine Specification 102-0371 DNI C1 0.1µF Z=50 Ohm C3 100pF 1 NC NC 18 2 VDD NC 17 3 NC NC 16 4 U1 MLPQ4X4_24L RF1 5 NC 6 ACG 7 ACG 2 J2 SMASM 1 C2 100pF C0.5 R1 0 OHM VDD RF2 15 NC 14 ACG 13 J3 SMASM Z=50 Ohm C4 100pF 1 2 R4 10K VDD R8 1 19 DB1 C16 GND NC 2 12 C0.5 10K 3 20 DB2 C8 GND ACG 4 11 C1 10K 5 R7 DB3 R6 GND 21 6 C4 C2 ACG 7 10 DB4 10K GND R5 8 22 DB5 C2 C4 GND ACG C8 9 9 11 10K DB6 23 GND 10 C1 12 ACG C16 8 13 10K DB7 R3 GND R2 14 24 J1 CWN-350-14-0000 ECT BP050-0024UJ03 4x4 MLP 24 Ld Socket Document No. 70-0218-06 │ www.psemi.com ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 9 PE4309 Product Specification Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4309 Digital Step Attenuator. Connect J2 by mini clip to Vdd to power the IC. Connect J8 by mini clip to power the evaluation board support circuits. The control bits for the six parallel data inputs (C0.5 to C16) are controlled using S2-S7 to select bits or bit combinations. This allows any attenuation setting to be specified as shown in Table 6. Figure 5. Evaluation Board Layout Peregrine Specification 101/0299 The de-embed trace (J6 to J7) estimates the PCB insertion loss for removal from the evaluation board measurement data. To evaluate using customer software, J1 can be installed using a standard 0.100 IDC header (some circuit modification required, see schematic). The ability to supply different voltages for the Control circuitry (using J8) and IC Vdd (using J2) circuits allows for evaluation of circuits using different control vs. supply voltages. Figure 6. Evaluation Board Schematic Peregrine Specification 102/0366 ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 9 Document No. 70-0218-06 │ UltraCMOS™ RFIC Solutions PE4309 Product Specification Typical Performance Data Figure 7. Insertion Loss, Vdd = 3.0 V Figure 8. Attenuation at Major Steps 31.5 dB 16 dB 8 dB 2 dB 4 dB 1 dB 0.5 dB Figure 9. Input Return Loss at Major Attenuation Steps Figure 10. Output Return Loss at Major Attenuation Steps 0 dB 16 dB 0 dB 16 dB 31.5 dB 31.5 dB Document No. 70-0218-06 │ www.psemi.com ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 9 PE4309 Product Specification Typical Performance Data Figure 11. Attenuation Error Vs. Frequency 16 dB 8 dB 31.5 dB Figure 12. Attenuation Error vs. Setting: Low Frequency ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 9 Figure 13. Attenuation Error vs. Setting: High Frequency Document No. 70-0218-06 │ UltraCMOS™ RFIC Solutions PE4309 Product Specification Figure 16. Package Drawing QFN 4x4 mm A MAX 0.900 NOM 0.850 MIN 0.800 Document No. 70-0218-06 │ www.psemi.com ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 9 PE4309 Product Specification Figure 17. Tape and Reel Drawing Figure 18. Marking Specifications 4309 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of Lot Number Table 7. Ordering Information Order Code Part Marking Description 4309-00 PE4309-EK PE4309-24QFN 4x4mm-EK Evaluation Kit 1 / Box 4309-51 4309 PE4309G-24QFN 4x4mm-75A Green 24-lead 4x4mm QFN 75 units / Tube 4309-52 4309 PE4309G-24QFN 4x4mm-3000C Green 24-lead 4x4mm QFN 3000 units / T&R ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 9 Package Document No. 70-0218-06 Shipping Method │ UltraCMOS™ RFIC Solutions PE4309 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Space and Defense Products Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0218-06 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP and MultiSwitch are trademarks of Peregrine Semiconductor Corp. ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 9