Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Product Features Product Description • Using external 32.768kHz quartz crystal The PT7C4307 serial real-time clock is a low-power • Supports I2C-Bus's high speed mode (400 kHz) clock/calendar with a programmable square-wave output • Includes time (Hour/Minute/Second) and calendar and 56 bytes of nonvolatile RAM. (Year/Month/Date/Day) counter functions (BCD code) Address and data are transferred serially via a 2-wire, • Programmable square wave output signal bidirectional bus. The clock/calendar provides seconds, • 56-byte, battery-backed, nonvolatile (NV) RAM for minutes, hours, day, date, month, and year information. data storage The date at the end of the month is automatically Automatic power-fail detect and switch circuitry of adjusted for months with fewer than 31 days, including battery backup corrections for leap year. The clock operates in either the Consumes less than 500nA in battery backup mode 24-hour or 12-hour format with AM/PM indicator. • • with oscillator running The PT7C4307 has a built-in power sense circuit that detects power failures and automatically switches to the Ordering Information battery supply. Part Number PT7C4307P Package 8-Pin DIP PT7C4307W 8-Pin SOIC Table 1 shows the basic functions of PT7C4307. More details are shown in section: overview of functions. Note: Lead free package is available by adding “E” after each part number. For example: PT7C4307PE. Table 1. Basic functions of PT7C4307 Item 1 2 Function Oscillator Time PT7C4307 Source: Crystal: 32.768kHz √ Oscillator enable/disable √ Oscillator fail detect - Time display 12-hour √ 24-hour √ Century bit 3 Alarm interrupt 4 Programmable square wave output (Hz) 5 RAM 6 Battery backup 1, 4.096k, 8.192k, 32.768k 56×8 √ PT0206(02/05) Ver: 0 1 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Contents Product Features ............................................................................................................................................................................... 1 Product Description .......................................................................................................................................................................... 1 Pin Assignment.................................................................................................................................................................................. 3 Pin Description .................................................................................................................................................................................. 3 Function Block .................................................................................................................................................................................. 4 Recommended Layout for Crystal .................................................................................................................................................. 4 Crystal Specifications ....................................................................................................................................................................... 4 Function Description......................................................................................................................................................................... 5 Overview of Functions .................................................................................................................................................................. 5 Registers......................................................................................................................................................................................... 6 Control and status register........................................................................................................................................................... 7 Time Counter .............................................................................................................................................................................. 8 Days of the week Counter ........................................................................................................................................................... 9 Calendar Counter ........................................................................................................................................................................ 9 2 I C Bus Interface............................................................................................................................................................................. 10 Overview of I2C-BUS .................................................................................................................................................................. 10 System Configuration ................................................................................................................................................................. 10 Starting and Stopping I2C Bus Communications ..................................................................................................................... 11 Slave Address .............................................................................................................................................................................. 13 Maximum Ratings........................................................................................................................................................................... 15 Recommended Operating Conditions ........................................................................................................................................... 15 DC Electrical Characteristics......................................................................................................................................................... 16 AC Electrical Characteristics......................................................................................................................................................... 17 Mechanical Information ................................................................................................................................................................. 18 PT0206(02/05) Ver: 0 2 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Assignment PT7C4307 1 X1 VCC 8 2 X2 SQW/OUT 7 3 VBAT SCL 6 4 GND SDA 5 DIP-8 SOIC-8 Pin Description Pin no. Pin Type Description 1 X1 I Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them. 2 X2 O Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them. When 32.768kHz external input, X2 must be float. 6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. 5 SDA I/O Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor. 7 SQW/OUT O Square Wave/Output Driver. Open drain. Four frequencies selectable: 32.768k, 8.192k, 4.096k, 1Hz when SQWE bit is set to 1. 8 VCC P Power. Primary power for PT7C4307. 3 VBAT P +3V Battery Power. 4 GND P Ground. PT0206(02/05) Ver: 0 3 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Block PT7C4307 X1 CD 32.768 kHz X2 Counter Chain OSC Time Counter (Sec,Min,Hour,Day,Date,Month,Year) CG SQW/OUT Address Decoder Control Register Address Register SCL I /O Interface (I2C) VCC VBAT 56 x 8 RAM Power Manager SDA Shift Registers Recommended Layout for Crystal PT7C4307 X1 32.768kHz Crystal X2 Local Ground plane Layer 2 Guard Ring (connect to gound) Crystal Specifications Parameter Nominal Frequency Series Resistance Load Capacitance Symbol fO ESR CL Min Typ 32.768 Max 45 12.5 Unit kHz kΩ pF The crystal, traces and crystal input pins should be isolated from RF generating signals. PT0206(02/05) Ver: 0 4 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Description Overview of Functions Clock function CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. Programmable square wave output A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 4.096k, 8.192k, 32.768k Hz. Interface with CPU Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode. Oscillator enable/disable Oscillator can be enabled or disabled by /EOSC bit. But time count chain does not shut down when the bit is logic 1. RAM 56×8 nonvolatile RAM are available for customer use. PT0206(02/05) Ver: 0 5 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Registers Allocation of registers Register definition Addr. (hex)*1 Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 Seconds (00-59) /EOSC*2 S40 S20 S10 S8 S4 S2 S1 01 Minutes (00-59) 0 M40 M20 M10 M8 M4 M2 M1 02 Hours (00-23 / 01-12) 0 12, /24 H20 or P, /A H10 H8 H4 H2 H1 03 Days of the week (01-07) 0 0 0 0 0 W4 W2 W1 04 Dates (01-31) 0 0 D20 D10 D8 D4 D2 D1 05 Months (01-12) 0 0 0 MO10 MO8 MO4 MO2 MO1 06 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 07 Control*3 OUT*4 0 0 SQWE*5 0 0 RS1*6 RS0*6 - - - - - - - - 08~3F RAM*7 Caution points: *1. PT7C4307 uses 6 bits for address. That is if write data to 41H, the data will be written to 01H address register. *2. Oscillator Enable bit. When this bit is set to 1, oscillator is stopped but time count chain is still active. *3. Control register was used to select SQW/OUT pin output square wave with one of 4 kinds of frequency or DC level. *4. Control SQW/OUT pin output DC level when square wave is disabled. *5. Square wave outputs enable at SQW/OUT pin. *6. Square wave output frequency select. *7. PT7C4307 has 56×8 static RAM for customer use. It is volatile RAM. *8. All bits marked with "0" are read-only bits. Their value when read is always "0". All bits marked with "-" are customer using space. PT0206(02/05) Ver: 0 6 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Control and status register Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 07 Control (default) OUT 0 0 0 0 0 SQWE 0 0 0 0 0 RS1 1 RS0 1 • OUT It controls the output level of the SQW/OUT pin when the square wave output is disabled. OUT Data Description 0 When SQWE = 0, SQW/OUT pin output low. 1 When SQWE = 0, SQW/OUT pin output high. Default Read / Write • SQWE (Square Wave Enable) This bit, when set to a logic 1, will enable the oscillator output. The frequency of the square wave output depends upon the value of the RS0 and RS1 bits. With the square wave output set to 1Hz, the clock registers update on the falling edge of the square wave. • RS (Rate Select) These bits control the frequency of the square wave output when the square wave output has been enabled. RS1, RS0 Data SQW output freq. (Hz) 00 1 01 4.096k 10 8.192k 11 32.768k Read / Write Default PT0206(02/05) Ver: 0 7 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Time Counter Time digit display (in BCD code): • Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. • Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. • Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. (hex) Description D7 00 Seconds (default) /EOSC* 1 S40 S20 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 01 Minutes (default) 0 0 M40 M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 02 Hours (default) 0 0 12, /24 H20 or P,/A H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined D6 D5 D4 D3 D2 D1 D0 * Note: /EOSC bit must be written into 0 to start the time count. • 12, /24 bit This bit is used to select between 12-hour clock system and 24-hour clock system. 12, /24 Data Description 0 24-hour system 1 12-hour system Read / Write This bit is used to select between 12-hour clock operation and 24-hour clock operation. 12, /24 Description Hours register 0 24-hour time display 1 12-hour time display 24-hour clock 00 01 02 03 04 05 06 07 08 09 10 11 12-hour clock 52 ( AM 12 ) 41 ( AM 01 ) 42 ( AM 02 ) 43 ( AM 03 ) 44 ( AM 04 ) 45 ( AM 05 ) 46 ( AM 06 ) 47 ( AM 07 ) 48 ( AM 08 ) 49 ( AM 09 ) 50 ( AM 10 ) 51 ( AM 11 ) 24-hour clock 12 13 14 15 16 17 18 19 20 21 22 23 12-hour clock 72 ( PM 12) 61 ( PM 01 ) 62 ( PM 02 ) 63 ( PM 03 ) 64 ( PM 04 ) 65 ( PM 05 ) 66 ( PM 06 ) 67 ( PM 07 ) 68 ( PM 08 ) 69 ( PM 09 ) 70 ( PM 10 ) 71 ( PM 11 ) * Be sure to select between 12-hour and 24-hour clock operation before writing the time data. PT0206(02/05) Ver: 0 8 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Days of the week Counter The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. Description D7 D6 D5 D4 D3 D2 D1 D0 (hex) 03 Days of the week (default) 0 0 0 0 0 0 0 0 0 0 W4 W2 W1 Undefined Undefined Undefined Calendar Counter The data format is BCD format. • Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. • Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. • Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years. Addr. (hex) Description D7 D6 04 Dates (default) 0 0 0 0 05 Months (default) 0 0 0 0 06 Years (default) D5 D4 D3 D2 D1 D0 D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined 0 0 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction. PT0206(02/05) Ver: 0 9 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| I2C Bus Interface Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. System Configuration All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed). Fig 1. System configuration Vcc RP RP SDA SCL Master MCU Slave RTC Other Peripheral Device Note: When there is only one master, the MCU is ready for driving SCL to "H" and R P of SCL may not required. PT0206(02/05) Ver: 0 10 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Starting and Stopping I2C Bus Communications Fig 2. Starting and stopping on I2C bus 1) START condition, repeated START condition, and STOP condition a) START condition SDA level changes from high to low while SCL is at high level b) STOP condition SDA level changes from low to high while SCL is at high level c) Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. 2) Data Transfers and Acknowledge Responses during I2C-BUS Communication a) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. *Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition. PT0206(02/05) Ver: 0 11 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| b) Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level. SCL from Master 1 8 2 SDA from transmitter (sending side) 9 Release SDA Low active SDA from receiver (receiving side) ACK signal After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master. PT0206(02/05) Ver: 0 12 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Slave Address The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. Table Slave address R / W bit Operation Transfer data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read D1 h 1 (= Read) 1 1 0 1 0 0 0 Write D0 h 0 (= Write) I2C Bus’s Basic Transfer Format S Start indication Sr Restart indication P Stop indication A RTC Acknowledge A Master Acknowledge 1) Write via I2C bus Slave address (7 bits) S 1 Start 1 0 1 0 0 write 0 Slave address + write specification A Addr. setting A 0 A C K Address Specifies the write start address. PT0206(02/05) A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Write data A P A C K Stop Ver: 0 13 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2) Read via I2C bus a) Standard read Slave address (7 bits) S 1 Start 1 0 1 0 0 write 0 Slave address (7 bits) 1 1 0 1 0 0 A C K Read 0 A 1 A C K Restart Slave address + read specification b) A 0 Slave address + write specification Sr Addr. setting A A C K Address Specifies the read start address. bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (1) Data is read from the specified start address and address auto increment. A A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (2) Address auto increment to set the address for the next data to be read. /A P N O Stop A C K Simplified read Slave address (7 bits) S 1 Start 1 0 1 0 0 Read 0 Slave address + read specification A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A C K Data read (1) Data is read from the address pointed by the internal address register and address auto increment. 1 A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A C K Data read (2) Address register auto increment to set the address for the next data to be read. /A P N O Stop A C K Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses. PT0206(02/05) Ver: 0 14 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Maximum Ratings Storage Temperature...................................................................................................................-65oCto +150oC Ambient Temperature with Power Applied.........................................................................-40oCto +85oC Supply Voltage to Ground Potential (Vcc to GND) ........................................................-0.3V to +6.5V DC Input (All Other Inputs except Vcc & GND).............................................................-0.3V to (Vcc+0.3V) DC Output Voltage (SDA, /INTA, /INTB pins).................................................................-0.3V to +6.5V DC Output Current (FOUT).....................................................................................................-0.3V to (Vcc+0.3V) Power Dissipation.........................................................................................................................320mW (depend on package) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Part No. PT7C4307 Symbol Description Min Type Max 5 5.5 VCC Power voltage 4.5 VBAT Battery voltage 2 3.5 VIH Input high level 2.2 VCC+0.3 VIL Input low level -0.3 0.8 TA Operating temperature -40 85 PT0206(02/05) Unit V ºC Ver: 0 15 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical Characteristics Unless otherwise specified, VDD = 4.5 ~ 5.5 V, TA = -40 °C to +85 °C Sym. Item VCC Supply voltage VBAT Supply voltage VPF Pin Condition VCC VBATT Power fail voltage Note 4 ICC Current consumption VCC IBAT Current consumption VBAT VIL VIH VOL IIL Low-level input voltage High-level input voltage Low-level output voltage Input leakage current SCL SCL SDA SCL IOZ Output current when OFF SDA OSC on, Note 3 OSC off, Note 1 OSC on, SQW/OUT off, Note 2 OSC on, SQW/OUT on (32kHz) IOL = 5mA Min Typ Max Unit 4.5 2.0 5.0 5.5 3.5 V 1.216× 1.25× 1.284× VBAT VBAT VBAT 1.5 200 300 500 480 800 0.8 2.0 0.4 1 1 V mA µA nA V V µA µA Note: 1. VCC = 5.0V and SDA, SCL = 5.0V. 2. VCC = 0V, VBAT = 3V. 3. SCL clocking at max frequency = 100kHz. SDA pin open, /EOSC bit = 0 (oscillator enabled) 4. VPF measured at VBAT = 3.0V. PT0206(02/05) Ver: 0 16 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| AC Electrical Characteristics Sym VHM VHL Description Rising and falling threshold voltage high Rising and falling threshold voltage low Value 0.8 VCC 0.2 VCC Unit V V Signal VHM VLM tr tf Over the operating range Symbol Item Min. Typ. Max. Unit 400 kHz fSCL tSU;STA SCL clock frequency START condition set-up time 0.6 µs tHD;STA START condition hold time 0.6 tSU;DAT tHD;DAT1 tHD;DAT2 Data set-up time (RTC read/write) Data hold time (RTC write) Data hold time (RTC read) 200 35 0 µs ns ns tSU;STO STOP condition setup time 0.6 µs tBUF Bus idle time between a START and STOP condition 1.3 µs tLOW When SCL = "L" 1.3 µs tHIGH When SCL = "H" 0.6 tr Rise time for SCL and SDA 0.3 µs tf Fall time for SCL and SDA 0.3 tSP* CB Allowable spike time on bus Capacitance load for each bus line 50 400 µs ns pF µs µs * Note: only reference for design S SCL Sr tLOW fSCL tHIGH P tHD;STA tSP tSU;STA tBUF SDA tHD;STA S Start condition Sr Restart condition tSU;DAT tHD;DAT P tSU;STA tSU;STO tHD;STA Stop condition PT0206(02/05) Ver: 0 17 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information DIP-8 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS Note: 1) Controlling dimensions in inches. 2) Ref: JDDEC MS-001 BA PT0206(02/05) Ver: 0 18 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| SOIC-8 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS Note: 1) Controlling dimensions in millimeters. 2) Ref: JDDEC MS-012 AA PT0206(02/05) Ver: 0 19 Preliminary Data Sheet PT7C4307 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Notes Pericom Technology Inc. Email: [email protected] Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0206(02/05) Ver: 0 20