PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Features Description Using external 32.768kHz quartz crystal The PT7C4363 serial real-time clock is a low-power Supports I2C-Bus's high speed mode (400 kHz) clock/calendar with a programmable square-wave output. Includes time (Hour/Minute/Second) and calendar (Year/Month/Date/Day) counter functions (BCD Address and data are transferred serially via a 2-wire code) bidirectional bus. The clock/calendar provides seconds, Programmable square wave output signal minutes, hours, day, date, month, and year information. Oscillator stop flag The date at the end of the month is automatically Low backup current: typ. 400nA at VDD=3.0V and adjusted for months with fewer than 31 days, including TA=25°C corrections for leap year. The clock operates in the 24- Operating range: 1.3V to 5.5V hour format indicator. Table 1 shows the basic functions of PT7C4363. More details are shown in section: overview of functions. Table 1. Basic functions of PT7C4363 Item Function PT7C4363 - Source: Crystal: 32.768kHz 1 Oscillator Oscillator enable/disable 12-hour - 24-hour Oscillator fail detect Time display 2 Time Century bit Time count chain enable/disable Alarm interrupt 3 Interrupt 4 Programmable square wave output (Hz) 5 Communicati on 6 Control 1, 32, 1.024k, 32.768k Timer interrupt output - 2-wire I2C bus 3-wire bus Burst mode Write protection - External clock test mode Power-on reset override 2013-06-0002 PT0207-6 1 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Configuration PT7C4363 1 X1 VCC 2 X2 SQW 7 3 INT SCL 6 4 GND SDA 5 8 DIP-8 SOIC-8 TSSOP-8 Pin Description Pin no. Pin Type Description 1 X1 I Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them. 2 X2 O Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them. 3 INT O Interrupt Output. Open drain, active low. 4 GND P Ground. 5 SDA I/O 6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. 7 SQW O Clock Output. Open drain. Four frequencies selectable: 32.768k, 1.024k, 32, 1Hz when SQWE bit is set to 1. 8 VCC P Power. Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor. 2013-06-0002 PT0207-6 2 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Block PT7C4363 Alarm Register Comparator (Min, Hour, Day, Date) X1 CD 32.768 kHz X2 OSC Timer Counter Chain Time Counter (Sec,Min,Hour,Day,Date,Month,Year) CG Address Decoder Control Register INT SCL I /O Interface (I2C) Timer / Alarm Interrupt Control Square Wave Output Control SQW Address Register Shift Register SDA Note: PT7C4363 need to add a 10pF ~ 30pF capacitor between X1 and GND to get the accurate 32k frequency. Maximum Ratings Storage Temperature............................................................................................................... -65oCto +150oC Ambient Temperature with Power Applied ...................................................................... -40oCto +85oC Supply Voltage to Ground Potential (Vcc to GND) ......................................................-0.3V to +6.5V DC Input (All Other Inputs except Vcc & GND) ...........................................................-0.3V to (Vcc+0.3V) DC Output Voltage (SDA, /INTA, /INTB pins).............................................................. -0.3V to +6.5V Power Dissipation.................................................................................................................... 320mW (Depend on package) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol Description Min Type Max VCC Power voltage 1.3 - 5.5 VIH Input high level 0.7 VCC - VCC+0.3 VIL Input low level -0.3 - 0.3 VCC TA Operating temperature -40 - 85 2013-06-0002 PT0207-6 3 Unit V ºC 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical Characteristics Unless otherwise specified, GND =0V, VCC = 1.3 ~ 5.5 V, TA = -40 °C to +85 °C, fOSC = 32.768kHz. Sym. Description Pin Conditions Min Typ Max 1) VCC Unit Supply voltage VCC Interface inactive. TA = 25°C Interface active. fSCL = 400kHz 1) 1.1 1.3 - 5.5 5.5 Supply voltage for clock data integrity VCC - 1.1 - 5.5 fSCL = 400kHz fSCL = 100kHz VCC = 5.0V VCC = 3.0V VCC = 5.0V - 450 400 650 25 15 700 650 900 VCC = 3.0V - 600 850 0 0.7VCC -3 -1 - - 0.3VCC VCC 1 A - - 1 A Interface active ICC Supply current VIL1 Low-level input voltage VIH1 High-level input voltage IOL Low-level output voltage IIL Input leakage current Interface inactive (fSCL = 0Hz), pin 7 disabled 2) TA=-40~85°C Interface inactive (fSCL = 0Hz), pin 7 enabled at 32kHz 2) TA=40~85°C SCL SCL SDA VOL = 0.4V, VCC = 5V /INT, SQW VOL = 0.4V, VCC = 5V SCL VCC IOZ Output current when OFF Note: 1) For reliable oscillator start-up at power-up: VCC(min)power-up = VCC(min) + 0.3 V. 2) Timer source clock = 1/60 Hz, voltage of SCL and SDA is VCC or GND. V A nA nA V mA AC Electrical Characteristics Sym VHM VHL Description Rising and falling threshold voltage high Rising and falling threshold voltage low Value 0.8 VCC 0.2 VCC Unit V V Signal VHM VLM tr tf 2013-06-0002 PT0207-6 4 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Over the operating range Symbol Item fSCL SCL clock frequency tSU;STA START condition set-up time Min. 0.6 Typ. - Max. 400 - Unit kHz s tHD;STA tSU;DAT tHD;DAT1 tHD;DAT2 START condition hold time Data set-up time (RTC read/write) Data hold time (RTC write) Data hold time (RTC read) 0.6 200 35 0 - - s ns ns tSU;STO STOP condition setup time 0.6 - - s tBUF Bus idle time between a START and STOP condition 1.3 - - s tLOW When SCL = "L" 1.3 - - s tHIGH When SCL = "H" 0.6 - - s tr Rise time for SCL and SDA - - 0.3 s - - 0.3 50 400 s ns pF tf Fall time for SCL and SDA tSP* Allowable spike time on bus CB Capacitance load for each bus line * Note: Only reference for design. S SCL Sr tLOW fSCL tHIGH P tHD;STA tSP s tSU;STA tBUF SDA tHD;STA S Start condition Sr Restart condition tSU;DAT tHD;DAT P tSU;STA tSU;STO tHD;STA Stop condition 2013-06-0002 PT0207-6 5 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Recommended Layout for Crystal Note: The crystal, traces and crystal input pins should be isolated from RF generating signals. Built-in Capacitors Specifications and Recommended External Capacitors Parameter Symbol Typ Unit X1 to GND CG 5 pF Build-in capacitors X2 to GND CD 20 pF X1 to GND C1 18 pF Recommended External capacitors X2 to GND C2 4 pF Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768Hz, C1 and C2 should meet the equation as below: Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL Cpar is all parasitical capacitor between X1 and X2. CL is crystal’s load capacitance. Crystal Specifications Parameter Nominal Frequency Series Resistance Load Capacitance Symbol fO ESR CL Min - Typ 32.768 12.5 2013-06-0002 Max 70 - Unit kHz k pF PT0207-6 6 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Description Overview of Functions 1. Clock function CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100. 2. Alarm function These devices have one alarm system that outputs interrupt signals from INTA for PT7C4363 or INT/OUT/SQW for PT7C4341 to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time. The alarm may be selectable between on and off for matching alarm or repeating alarm. 3. Programmable square wave output A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 32, 1.024k, 32.768k Hz. 4. Interface with CPU Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I 2C bus's high-speed mode. 5. Oscillator fail detect When oscillator fail, OSF bit will be set. 6. Oscillator enable/disable Only time count chain can be enable or disable by STOP bit.. 7. Timer function The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1/60 Hz) and enables or disables the timer. The timer counts down from software loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. Bit TI/TP is used to control this mode selection. When reading the timer, the current countdown value is returned. 8. Reset function The PT7C4363 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I 2C-bus logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, OSF, TD1, TD0, TESTC and AE which are set to logic 1. 2013-06-0002 PT0207-6 7 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Registers 1. Allocation of registers Addr. (hex) *1 Function (time range BCD format) Register definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TESTC*4 Bit 2 Bit 1 Bit 0 - - - 00 Control/status 1 TEST1*2 - STOP*3 - 01 Control/status 2 - - - TI/TP*5 AF*6 TF*6 AIE*7 TIE*7 02 Seconds (00-59) OSF*8 S40 S20 S10 S8 S4 S2 S1 03 Minutes (00-59) M40 M20 M10 M8 M4 M2 M1 04 Hours (00-23) H20 H10 H8 H4 H2 H1 05 Dates (01-31) D20 D10 D8 D4 D2 D1 06 Days of the week (00-06) W4 W2 W1 07 Months (01-12) Century MO10 MO8 MO4 MO2 MO1 08 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 09 Alarm: Minutes (00-59) AE*9 M40 M20 M10 M8 M4 M2 M1 0A Alarm: Hours (01-12) AE*9 H20 H10 H8 H4 H2 H1 0B Alarm: Dates (01-31) AE*9 D20 D10 D8 D4 D2 D1 0C Alarm: Weekday (00-06) AE*9 W4 W2 W1 0D SQW control SQWE RS1 RS0 0E Timer control TE*10 TD1*11 TD0*11 0F Timer Timer count down value Caution points: *1. PT7C4363 uses 8 bits for address. For excess 0FH address, PT7C4363 will not respond. *2. EXT_CLK test mode select bit. *3. When the bit is logic 1, time count chain stops but oscillator still runs. *4. Power-on reset override enable bit. *5. Timer interrupt output select bit. *6. Alarm and timer interrupt flag bits. *7. Alarm and timer interrupt enable bits. *8. Oscillator fail indicates. Indicate clock integrity. *9. Alarm enable bit. Alarm will be active when related time is matching if AE = 0. *10. Timer enable bit. *11. Timer source clock frequency select. *12. All bits marked with "" are not implemented. All bits marked with "-" are not used bits and should always be written with logic 0. If read them, they could be logic 0 or 1. 2013-06-0002 PT0207-6 8 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2. Control and status register Addr. (hex) Description D7 D6 D5 D4 D3 D2 00 Control/status 1 (default) TEST1 0 Undefined STOP 0 Undefined TESTC 1 Undefined 01 Control/status 2 (default) 0D SQW control (default) 0E Timer control (default) 0F a) Undefined Undefined Undefined D0 Undefined Undefined AF TF Undefined Undefined AIE 0 TIE 0 SQWE 1 Undefined Undefined Undefined Undefined Undefined RS1 0 RS0 0 TE 0 Undefined Undefined Undefined Undefined Undefined TD1 1 TD0 1 Timer (default) TI/TP 0 D1 Timer count down value Undefined Timer TE: Timer Enable bit. TE Data Description 0 Timer disabled 1 Timer enabled Default Read / Write TD1, TD0: timer source clock frequency select. These bits determine the source clock for the countdown timer. TD1, TD0 Data Timer source clock freq. (Hz) 00 4.096k 01 64 10 1 11 1/60 Read / Write Timer: Timer Read / Write When not in use, TD1 TD0 should be set to 11 for power saving. Data 00~FF Description Countdown Period = n / Source Clock Frequency Count down value (n) For example: If TE = 1, TD1 TD0 = 10, Timer = 03 are written into PT7C4363, timer counts down every 1 second from 03 to 01 then 03 cycled. b) Timer Interrupt TIE: Timer Interrupt Enable bit. TIE Data 0 Timer interrupt disabled 1 Timer interrupt enabled Description Default Read / Write TF: Timer Flag 2013-06-0002 PT0207-6 9 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| TF Data Read Write Description 0 Timer flag inactive 1 Timer flag active. At the end of a timer countdown, TF is set to 1. 0 Timer flag is cleared 1 Timer flag remains unchanged TI/TP: Timer Interrupt output select TI/TP Data 0 Description INT is active when TF is active (subject to the status of TIE) INT pulses active according to source clock frequency and timer count down value (subject to the status of TIE). Source clock INT negative pulse width (s) (Hz) n=1 n>1 1 1 4096 /8192 /4096 1 1 64 /128 /64 1 1 1 /64 /64 1 1 1/60 /64 /64 Read / Write 1 Note: TF and INT become active simultaneously. n = loaded countdown value. Timer stopped when n = 0. Example 1: If TE = 1, TD1 TD0 = 00, Timer = 03, TIE = 1, TF = 0, TI/TP = 1 are written into PT7C4363, timer register counts down every 1/4.096kHz seconds from 03 to 01 then 03 cycled and INT output negative pulse with 1/4096 seconds width. See Fig.1. 4.096kHz internal clock Timer=02 Timer=01 Timer=03 Timer=02 Timer=01 Timer=03 Set TF=1 INT Fig.1 Example 1 of timer interrupts 2013-06-0002 PT0207-6 10 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Example 2: If TE = 1, TD1 TD0 = 10, Timer = 03, TIE = 1, TF = 0, TI/TP = 1 are written into PT7C4363, timer counts down every 1/4.096kHz seconds from 03 to 01 then 03 cycled and INT output negative pulse with 1/64 seconds width. See Fig.2. 1Hz internal clock Timer=02 Timer=01 Timer=03 Timer=02 1/64 INT Set TF=1 Fig.2 Example 2 of timer interrupts c) Alarm Interrupt AIE: Alarm Interrupt Enable bit. AIE Data 0 Alarm interrupt disabled 1 Alarm interrupt enabled Description Default Read / Write AF: Alarm Flag AF Read Write d) Data Description 0 Alarm flag inactive 1 Alarm flag active 0 Alarm flag is cleared 1 Alarm flag remains unchanged SQW control SQWE: SQW output clock enable bit. SQWE Data Description 0 the SQW output is inhibited and SQW output is set to high-impedance 1 the SQW output is activated Read / Write Default RS1, RS0: SQW output frequency select. RS1, RS0 Data 00 32.768k 01 1.024k 10 32 11 1 SQW output freq. (Hz) Default Read / Write 2013-06-0002 PT0207-6 11 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| e) Time count STOP STOP Data Default 0 RTC source clock runs. 1 All RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (SQW at 32.768 kHz is still available) Read / Write f) Description Test TEST1 TEST1 Data Description 0 Normal mode. 1 EXT_CLK test mode. Default Read / Write TESTC TESTC Data Description 0 Power-on reset override facility is disabled; set to logic 0 for normal operation. 1 Power-on reset override may be enabled Read / Write 3. Default Time Counter Time digit display (in BCD code): Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. Description D7 D6 D5 D4 D3 D2 D1 D0 (hex) 02 Seconds (default) OSF*1 1 S40 S20 S10 S8 S4 Undefined Undefined Undefined Undefined Undefined S2 S1 Undefined Undefined 03 Minutes (default) 0 M40 M20 M10 M8 M4 Undefined Undefined Undefined Undefined Undefined M2 M1 Undefined Undefined Hours H20 H10 H8 H4 H2 H1 (default) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined *1 Note: Indicate clock integrity. When the bit is 1, the clock integrity is no longer guaranteed and the time need be adjusted. 04 2013-06-0002 PT0207-6 12 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 4. Days of the week Counter The day counter is a divide-by-7 counter that counts from 00 to 06 and up 06 before starting again from 00. Values that correspond to the day of week are user defined but must be sequential (i.e., if 0 equals Sunday, then 1 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. (hex) Description D7 D6 D5 D4 D3 06 Days of the week (default) 0 0 0 0 0 5. D2 D1 D0 W4 W2 W1 Undefined Undefined Undefined Calendar Counter The data format is BCD format. Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years. Addr. (hex) Description D7 D6 05 Dates (default) 0 0 07 Months (default) Century*1 Undefined 0 D5 D4 D3 D2 D1 D20 D10 D8 D4 Undefined Undefined Undefined Undefined 0 D0 D2 D1 Undefined Undefined M10 M8 M4 Undefined Undefined Undefined M2 M1 Undefined Undefined Years Y80 Y40 Y20 Y10 Y8 Y4 (default) Undefined Undefined Undefined Undefined Undefined Undefined *1: The century bit is toggled when the years register overflows from 99 to 00. Y2 Y1 Undefined Undefined 08 6. Alarm Register PT7C4363: Alarm Register Addr. 09 0A 0B 0C Description Alarm: Minutes (default) Alarm: Hours (default) Alarm: Dates (default) Alarm: Weekday D7 D6 AE*1 M40 Undefined Undefined D5 D4 M20 Undefined AE*2 H20 Undefined D3 D2 D1 D0 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined H10 H8 H4 H2 H1 0 Undefined Undefined Undefined Undefined Undefined Undefined *3 AE Undefined 0 D20 Undefined D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined AE*4 0 0 0 0 (default) Undefined *1 Note: Minute alarm enable bit. *2 Note: Hour alarm enable bit. *3 Note: Date alarm enable bit. *4 Note: Weekday alarm enable bit. 2013-06-0002 W4 W2 Undefined Undefined Undefined PT0207-6 13 W1 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Alarm Function Related register 01 02 A Function d d r Control/status 2 . Register definition Bit 4 Bit 3 Bit 7 Bit 6 Bit 5 Bit 2 Bit 1 Bit 0 - - - TI/TP AF TF AIE TIE OSF S40 S20 S10 S8 S4 S2 S1 M40 M20 M10 M8 M4 M2 M1 H20 H10 H8 H4 H2 H1 04 Seconds ( h Minutese x Hours ) 05 Dates D20 D10 D8 D4 D2 D1 06 Days of the week W4 W2 W1 09 Alarm: Minutes AE M40 M20 M10 M8 M4 M2 M1 0A Alarm: Hours H20 H10 H8 H4 H2 H1 0B Alarm: Dates AE D20 D10 D8 D4 D2 D1 0C Alarm: Weekday AE W2 W1 03 AE W4 When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable (AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE at logic 1 will be ignored. EXT_CLK Test Mode and POR override 1. EXT_CLK Test Mode A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit TEST1 in control/status1 register. Then pin SQW becomes an input. The test mode replaces the internal 64 Hz signal with the signal applied to pin SQW. Every 64 positive edges applied to pin SQW will then generate an increment of one second. The signal applied to pin SQW should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from SQW, is divided down to 1 Hz by a 2 6 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0 (STOP must be cleared before the pre-scaler can operate again). From a STOP condition, the first 1 second increment will take place after 32 positive edges on SQW. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the pre-scaler can be made. 2013-06-0002 PT0207-6 14 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Operation example: 1. Set EXT_CLK test mode (control/status 1, bit TEST1 = 1) 2. Set STOP (control/status 1, bit STOP = 1) 3. Clear STOP (control/status 1, bit STOP = 0) 4. Set time registers to desired value 5. Apply 32 clock pulses to SQW 6. Read time registers to see the first change 7. Apply 64 clock pulses to SQW 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. 2. Power-On Reset (POR) override The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Fig 6.4.2. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus access. The override mode may be cleared by writing a logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent from entering the POR override mode. Power up Override active Fig.3 POR override sequence Communication 1. I2C Bus Interface a) Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. b) System Configuration All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed). 2013-06-0002 PT0207-6 15 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Vcc RP RP SDA SCL Master MCU Slave RTC Other Peripheral Device Note: When there is only one master, the MCU is ready for driving SCL to "H" and R P of SCL may not required. Fig.4 System configuration c) Starting and Stopping I2C Bus Communications Fig.5 Starting and stopping on I2C bus START condition, repeated START condition, and STOP condition START condition SDA level changes from high to low while SCL is at high level STOP condition SDA level changes from low to high while SCL is at high level Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. d) Data Transfers and Acknowledge Responses during I2C-BUS Communication Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. 2013-06-0002 PT0207-6 16 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. *Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition. Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level. SCL from Master 1 8 2 SDA from transmitter (sending side) 9 Release SDA Low active SDA from receiver (receiving side) ACK signal After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master. e) Slave Address The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. 2013-06-0002 PT0207-6 17 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Operation Read Write 2. a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 1 0 1 0 0 0 1 A3 h A2 h R / W bit bit 0 1 (= Read) 0 (= Write) I2C Bus’s Basic Transfer Format S Start indication Sr Restart indication Stop indication P A RTC Acknowledge A Master Acknowledge Write via I2C bus Slave address (7 bits) S 1 Start b) Slave address Transfer data 0 1 0 0 Addr. setting write A 0 1 A 0 A C K Slave address + write specification A C K Address Specifies the write start address. bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Write data A P A C K Stop Read via I2C bus Standard read Slave address (7 bits) S 1 Start 0 1 0 0 0 1 Slave address (7 bits) 1 0 1 0 0 0 A C K Read 1 Restart Slave address + read specification A 0 Slave address + write specification Sr Addr. setting write A A 1 A C K A C K Address Specifies the read start address. bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (1) Data is read from the specified start address and address auto increment. 2013-06-0002 A A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (2) Address auto increment to set the address for the next data to be read. PT0207-6 18 / A N O P Stop A C K 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Simplified read Slave address (7 bits) S 1 Start 0 1 0 0 0 Read 1 Slave address + read specification A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A C K Data read (1) Data is read from the address pointed by the internal address register and address auto increment. 1 A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A C K Data read (2) Address register auto increment to set the address for the next data to be read. / A N O P Stop A C K Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses. 2013-06-0002 PT0207-6 19 06/18/13 PT7C4363 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information WE (Lead free and Green SOIC-8) Symbol A A1 A2 b c D E E1 e L θ Note: 1) Controlling dimensions in millimeters. 2) Ref : JEDEC MS-012E/AA Dimensions In Millimeters Min Max 1.350 1.750 0.100 0.250 1.350 1.550 0.330 0.510 0.170 0.250 4.700 5.100 3.800 4.000 5.800 6.200 1.27 BSC 0.400 1.270 0° 8° Ordering Information Part Number PT7C4363WE Package Code W Package Lead free and Green 8-Pin SOIC Note: E = Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 2013-06-0002 PT0207-6 20 06/18/13