PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Description Features The PT7C4337 serial real-time clock is a low-power Using external 32.768kHz quartz crystal for clock/calendar with two programmable time-of-day PT7C4337 alarms and a programmable square-wave output. Supports I2C-Bus's high speed mode (400 kHz) Includes time (Hour/Minute/Second) and calendar Address and data are transferred serially via a 2-wire, bidirectional bus. The clock/calendar provides seconds, (Year/Month/Date/Day) counter functions (BCD minutes, hours, day, date, month, and year information. code) Programmable square wave output signal Two Time-of-Day Alarms Oscillator Stop Flag Operating range: 1.8V to 5.5V Timekeeping range: 1.2V to 1.8V The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The device is fully accessible through the serial interface while VCC is between 1.8V and 5.5V. I2C operation is not guaranteed below 1.8V. Timekeeping operation is maintained with VCC as low as 1.2V. Table 1 shows the basic functions of PT7C4337. More details are shown in section: overview of functions. Table 1. Basic functions of PT7C4337 Item Function PT7C4337 Source 1 Oscillator Time External crystal Oscillator enable/disable Oscillator fail detect Time display 2 Crystal(32.768KHz) 12-hour 24-hour Century bit - Time count chain enable/disable Alarm interrupt output 2 3 Interrupt 4 Programmable square wave output (Hz) 5 Communication 1, 4.096k, 8.192k, 32.768k 2-wire I2C bus 2013-06-0002 PT0205-9 1 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Assignment PT7C4337 1 X1 VCC 2 X2 3 INTA SCL 6 4 GND SDA 5 8 SQW/INTB 7 DIP-8、SOIC-8 MSOP8 Pin Description Pin No. Pin Type Description Oscillator Circuit Input. Together with X1, 32.768kHz crystal is connected between them. Or external clock input. Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them. When 32.768kHz external input, X2 must be float. 1 X1 I 2 X2 O 6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. 5 SDA I/O Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor. 3 INTA O Interrupt Output. When enabled, INTA is asserted low when the time matches the values set in the alarm registers. This pin is an open-drain output and requires an external pull up resistor. 7 SQW/I NTB O Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. It is an open-drain output and requires an external pull up resistor. 8 VCC P Power. Primary power for PT7C4337. 4 GND P / NC Ground. No Connect. These pins are not connected internally, but must be grounded for proper operation. Maximum Ratings Storage Temperature ............................................................ -65℃ to +150℃ Ambient Temperature with Power Applied ........................... -40℃ to +85℃ Supply Voltage to Ground Potential (VCC to GND) ............... -0.3V to +6.5V DC Input (All Other Inputs except Vcc & GND) ...................................... -0.3V to (Vcc +0.3V) DC Output Voltage (SDA, /INTA, /INTB pins)........................................-0.3V to +6.5V DC Output Current (FOUT) ............................................... -0.3V to (Vcc +0.3V) Power Dissipation .............................................320mW(depend on package) 2013-06-0002 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PT0205-9 2 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Operating Mode The amount of current consumed by the PT7C4337 is determined, in part, by the I2C interface and oscillator operation. The following table shows the relationship between the operating mode and the corresponding I CC parameter. VCC Operating Mode Power I2C Interface Active 1.8V ≤ VCC ≤ 5.5V ICC Active (ICCA) I2C Interface Inactive 1.8V ≤ VCC ≤ 5.5V ICC Standby (ICCS) I2C Interface Inactive 1.2V ≤ VCC ≤ 1.8V Timekeeping (ICCTOSC) I2C Interface Inactive, Oscillator Disabled 1.2V ≤ VCC ≤ 1.8V Data Retention (ICCTDDR) Recommended Operating Conditions Part No. Sym. VCC VCCT VOSC PT7C4337 Description VCC supply voltage Oscillator start up voltage SCL, SDA VIH Input high level INTA, SQW/INTB Min Type Max 1.8 3.3 5.5 1.2 - 1.8 1.2 - 5.5 0.7VCC - VCC+0.3 - - 5.5 VIL Input low level -0.3 - 0.3VCC TA Operating temperature -40 - 85 Unit V ºC DC Electrical Characteristics Unless otherwise specified, VCC = 1.8~5.5V, TA = -40 °C to +85 °C Sym. VCC VCCT VOSC VIL1 VIH1 VIL2 VIH2 IOL Item Pin Condition Full operation Timekeeping (Note 5) Min 1.8 1.2 1.2 -0.3 0.7VCC 3 Typ Max Unit 5.5 V 1.8 5.5 V 0.3VCC V VCC+0.3 0.53 V 0.53 mA Supply voltage VCC Oscillator voltage Low-level input voltage High-level input voltage Low-level input voltage High-level input voltage Low-level output current VCC SCL SCL X1 X1 SDA, /INTA, /INTB IIL Input leakage current SCL -1 - 1 A IOZ Output current when OFF SDA, /INTA, /INTB -1 - 1 A VOL = 0.4V 2013-06-0002 PT0205-9 3 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical Characteristics Sym. Item Pin Condition Unless otherwise specified, VCC = 1.3~1.8V, TA = -40 °C to +85 °C VCC Note 2, 4, 5 ICCTOSC Timekeeping current VCC Note 2,4,5,6 ICCTDDR Data retention current Unless otherwise specified, VCC = 1.8~3.6V, TA = -40 °C to +85 °C ICCA Active supply current VCC Note 1, 5 ICCS Standby current VCC Note 2, 3, 5 Unless otherwise specified, VCC = 3.6~5.5V, TA = -40 °C to +85 °C ICCA Active supply current VCC Note 1, 5 ICCS Standby current VCC Note 2, 3, 5 Note: 1. SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC. 2. Specified with 2-wire bus inactive, VIL = 0.0V, VIH = VCC. 3. SQW enabled. 4. Specified with the SQW function disabled by setting INTCN = 1. 5. Using recommended crystal on X1 and X2. 6. Crystal oscillator is disabled. 2013-06-0002 Min Typ Max Unit - 450 - 800 160 nA - 0.6 100 1.0 A - 1.0 150 1.8 A PT0205-9 4 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Recommended Layout for Crystal Note: The crystal, traces and crystal input pins should be isolated from RF generating signals. Built-in Capacitors Specifications and Recommended External Capacitors Parameter Symbol Typ Unit X1 to GND CG 12 pF Build-in capacitors X2 to GND CD 12 pF X1 to GND C1 13 pF Recommended External capacitors for crystal CL=12.5pF X2 to GND C2 13 pF X1 to GND C1 0 pF Recommended External capacitors for crystal CL=6pF X2 to GND C2 0 pF Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768KHz, C1 and C2 should meet the equation as below: Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL Cpar is all parasitical capacitor between X1 and X2. CL is crystal’s load capacitance. Crystal Specifications Parameter Nominal Frequency Series Resistance Load Capacitance Symbol fO ESR CL Min - Typ 32.768 6/12.5 2013-06-0002 Max 70 - Unit kHz k pF PT0205-9 5 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| AC Electrical Characteristics Sym VHM VHL Description Rising and falling threshold voltage high Rising and falling threshold voltage low Value 0.8 VCC 0.2 VCC Unit V V Signal VHM VLM tr tf Over the operating range Symbol Item fSCL SCL clock frequency tSU;STA START condition set-up time tHD;STA START condition hold time tSU;DAT Data set-up time (RTC read/write) tHD;DAT1 Data hold time (RTC write) tHD;DAT2 Data hold time (RTC read) tSU;STO STOP condition setup time Min. 0.6 0.6 200 35 0 0.6 Typ. - Max. 400 - Unit kHz s s ns ns s s s tBUF tLOW Bus idle time between a START and STOP condition When SCL = "L" 1.3 1.3 - - tHIGH When SCL = "H" 0.6 - - s s - - 0.3 0.3 50 400 10 100 s s ns pF pF ms tr Rise time for SCL and SDA tf Fall time for SCL and SDA tSP* Allowable spike time on bus CB Capacitance load for each bus line CI/O * I/O Capacitance (SDA, SCL) TOSF Oscillator Stop Flag (OSF) Delay * Note: only reference for design S SCL Sr tLOW fSCL tHIGH P tHD;STA tSP tSU;STA tBUF SDA tHD;STA S Start condition Sr Restart condition tSU;DAT tHD;DAT P tSU;STA tSU;STO tHD;STA Stop condition 2013-06-0002 PT0205-9 6 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Block Alarm 1 Register Comparator 1 (Sec, Min, Hour, Day/Date) PT7C4337 Alarm 2 Register Comparator 2 (Min, Hour, Day/Date) X1 CG 32.768 kHz X2 OSC Time Counter Counter Chain (Sec,Min,Hour,Day,Date,Month,Year) CD Address Decoder Control Register INTA SQW/INTB Address Register SCL I /O Interface (I2C) Interrupt Control Square Wave Output Control Shift Register SDA Oscillator Circuit PT7C4337 The PT7C4337 uses an external 32.768 kHz crystal. Table2 specifies several crystal parameters for the external crystal. The Block Diagram shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics. Table2 Crystal Specifications Parameter Symbol Min Typ Max Nominal Frequency fO 32.768 Series Resistance ESR 70 Load Capacitance CL 6/12.5 Note: The crystal, traces, and crystal input pins should be isolated from RF generating signals. Unit kHz k pF Clock Accuracy The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 1 shows a typical PC board layout for isolating the crystal and oscillator from noise. 2013-06-0002 PT0205-9 7 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Description Overview of Functions Clock function CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100. Alarm function This device has two alarm system (Alarm 1 and Alarm 2) that outputs interrupt signals from INTA or INTB to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time. The alarm is be selectable between on and off for matching alarm or repeating alarm. Programmable square wave output A square wave output enable bit controls square wave output at pin 7. Frequencies are selectable: 1, 4.096k, 8.192k, 32.768k Hz. Interface with CPU Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I 2C bus's high-speed mode. Oscillator fail detect When oscillator fail, PT7C4337 OSF bit will be set. Oscillator enable/disable Oscillator and time count chain can be enabled or disabled at the same time by /ETIME bit. Registers Allocation of registers Register definition Addr. (hex)*1 Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 Seconds (00-59) 0 S40 S20 S10 S8 S4 S2 S1 01 Minutes (00-59) 0 M40 M20 M10 M8 M4 M2 M1 02 Hours (00-23 / 01-12) 0 12, /24 H20 or P, /A H10 H8 H4 H2 H1 03 Days of the week (01-07) 0 0 0 0 0 W4 W2 W1 04 Dates (01-31) 0 0 D20 D10 D8 D4 D2 D1 05 Months (01-12) Century 0 0 MO10 MO8 MO4 MO2 MO1 06 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 07 Alarm 1: Seconds A1M1*2 S40 S20 S10 S8 S4 S2 S1 2013-06-0002 PT0205-9 8 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 08 Alarm 1: Minutes A1M2*2 M40 09 Alarm 1: Hours A1M3*2 12, /24 0A Alarm 1: Day, Date A1M4*2 Day, /Date H20 or P, /A 0, D20 0B Alarm 2: Minutes A2M2*3 M40 M20 0C Alarm 2: Hours A2M3*3 12, /24 0D Alarm 2: Day, Date A2M4*3 Day, /Date H20 or P, /A 0, D20 0E Control /ETIME*4 0 0F Status 0 OSF*9 M20 M10 M8 M4 M2 M1 H10 H8 H4 H2 H1 0, D10 0, D8 W4, D4 W2, D2 W1, D1 M10 M8 M4 M2 M1 H10 H8 H4 H2 H1 0, D10 0, D8 W4, D4 W2, D2 W1, D1 0 RS2*5 RS1*5 A2IE*7 A1IE*7 0 0 0 A2F*8 A1F*8 INTCN*6 0 Caution points: *1. PT7C4337 uses 8 bits for address. For excess 0FH address, PT7C4337 will not respond (no acknowledge signal was given). *2. Alarm 1 mask bits. Select alarm repeated rate when an alarm occurs. *3. Alarm 2 mask bits. Select alarm repeated rate when an alarm occurs. *4. Oscillator and time count chain enable/disable bit. *5. Square wave output frequency select. *6. Interrupt output pin select bit. *7. Alarm 1 and alarm 2 enable bits. *8. Alarm 1 and alarm 2 flag bits. *9. Oscillator stop flag. *10. All bits marked with "0" are read-only bits. Their value when read is always "0". Control and status register Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 0E Control (default) /ETIME 0 0 0 0 0 RS2 1 RS1 1 INTCN 0 A2IE 0 A1IE 0 0F Status (default) OSF 1 0 0 0 0 0 0 0 0 0 0 A2F A1F Undefined Undefined Oscillator related bits /ETIME Enable oscillator and time count chain bit. /ETIME Data Description 0 Enable oscillator and time count chain. 1 Disable oscillator and time count chain. Default Read / Write OSF Oscillator Stop Flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC is insufficient to support oscillation. 3) The /ETIME bit is turned off. 4) External influences on the crystal (e.g., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. 2013-06-0002 PT0205-9 9 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Square wave frequency selection bits RS2, RS1 Square wave Rate Select. These bits control the frequency of the square-wave output when the square wave has been enabled. RS2, RS1 Data SQW output freq. (Hz) 00 1 01 4.096k 10 8.192k 11 32.768k Read / Write Default Interrupt related bits INTCN Interrupt Output pin select bit. This bit controls the relationship between the two alarms and the interrupt output pins. INTCN Data Description 1 A match between the timekeeping registers and the alarm 1 registers activates the INTA pin (if the alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the SQW/INTB pin (if the alarm 2 is enabled). 0 A match between the timekeeping registers and either alarm 1 or alarm 2 registers activates the INTA pin (if the alarms are enabled). In this configuration, a square wave is output on the SQW/INTB pin. Read / Write Default A1IE Alarm 1 Interrupt Enable. Description A1IE Data Read / Write 0 The A1F bit does not initiate the INTA signal. 1 Permits the alarm 1 flag (A1F) bit in the status register to assert INTA. Default A1F Alarm 1 Flag. A1F Data Description Read / Write 0 The time do not match the alarm 1 registers. Read 1 Indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Default A2IE Alarm 2 Interrupt Enable. A2IE Data Read / Write Description Default 0 The A2F bit does not initiate an interrupt signal. 1 Permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). 2013-06-0002 PT0205-9 10 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| A2F Alarm 2 Flag. A1F Data Read / Write 0 The time do not match the alarm 2 registers. 1 Indicates that the time matched the alarm 1 registers. This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN bit. If the INTCN = 0 and A2F = 1 (and A2IE = 1), the INTA pin goes low. If the INTCN = 1 and A2F = 1 (and A2IE = 1), the SQW/INTB pin goes low. A2F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Read Description Default Time Counter Time digit display (in BCD code): Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. Description D7 D6 D5 D4 D3 D2 D1 D0 (hex) 00 Seconds (default) 0 0 S40 S20 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 01 Minutes (default) 0 0 M40 M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Hours 0 12, /24 H20 or P,/A H10 H8 H4 H2 H1 (default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note: Any registered imaginary time should be replaced with correct time, otherwise it will cause the clock counter malfunction. 02 12, /24 bit This bit is used to select between 12-hour clock system and 24-hour clock system. 12, /24 Data Description 0 24-hour system 1 12-hour system Read / Write 2013-06-0002 PT0205-9 11 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| This bit is used to select between 12-hour clock operation and 24-hour clock operation. 12, /24 Description Hours register 0 24-hour time display 1 12-hour time display 24-hour clock 00 01 02 03 04 05 06 07 08 09 10 11 12-hour clock 52 ( AM 12 ) 41 ( AM 01 ) 42 ( AM 02 ) 43 ( AM 03 ) 44 ( AM 04 ) 45 ( AM 05 ) 46 ( AM 06 ) 47 ( AM 07 ) 48 ( AM 08 ) 49 ( AM 09 ) 50 ( AM 10 ) 51 ( AM 11 ) 24-hour clock 12 13 14 15 16 17 18 19 20 21 22 23 12-hour clock 72 ( PM 12) 61 ( PM 01 ) 62 ( PM 02 ) 63 ( PM 03 ) 64 ( PM 04 ) 65 ( PM 05 ) 66 ( PM 06 ) 67 ( PM 07 ) 68 ( PM 08 ) 69 ( PM 09 ) 70 ( PM 10 ) 71 ( PM 11 ) * Be sure to select between 12-hour and 24-hour clock operation before writing the time data. Days of the week Counter The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. Description D7 D6 D5 D4 D3 D2 D1 D0 (hex) 03 Days of the week (default) 0 0 0 0 0 0 0 0 0 0 W4 W2 W1 Undefined Undefined Undefined Calendar Counter The data format is BCD format. Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years. Addr. (hex) Description D7 D6 04 Dates (default) 0 0 0 0 05 Months (default) Century*1 Undefined 0 0 06 Years (default) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined D5 D4 D3 D2 D1 D0 D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined 0 0 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined *1: The century bit is toggled when the years register overflows from 99 to 00. 2013-06-0002 PT0205-9 12 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Alarm Register Alarm 1, Alarm 2 Register Addr. Description 07 Alarm 1: Seconds (default) 08 09 0A 0B 0C 0D Alarm 1: Minutes (default) D7 D6 A1M1*1 S40 Undefined Undefined A1M2*1 M40 D4 S20 Undefined M20 D3 D2 D1 D0 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined A1M3 12, /24 H20 or P,/A Undefined Undefined Undefined Day, 0, Alarm 1: Day, Date A1M4*1 /Date*1 D20 (default) Undefined Undefined Undefined H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined 0, 0, W4, W2, W1, D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Alarm 1: Hours (default) Alarm 2: Minutes (default) Undefined Undefined D5 *1 A2M2*2 M40 Undefined Undefined M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined A2M3*2 12, /24 H20 or P,/A Undefined Undefined Undefined Day, 0, Alarm 2: Day, Date A2M4*2 /Date*2 D20 (default) Undefined Undefined Undefined H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined 0, 0, W4, W2, W1, D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Alarm 2: Hours (default) *1 Note: Alarm mask bit, using to select Alarm 1 alarm rate. *2 Note: Alarm mask bit, using to select Alarm 2 alarm rate. 2013-06-0002 PT0205-9 13 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Alarm Function Related register Addr. Function (hex) Bit 7 Bit 6 Bit 5 Register definition Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 Seconds 0 S40 S20 S10 S8 S4 S2 S1 01 Minutes 0 M40 M20 M10 M8 M4 M2 M1 02 Hours 0 12, /24 H20 or A, /P H10 H8 H4 H2 H1 03 Days of the week 0 0 0 0 0 W4 W2 W1 04 Dates 0 0 D20 D10 D8 D4 D2 D1 07 Alarm 1: Seconds A1M1 S40 S20 S10 S8 S4 S2 S1 08 Alarm 1: Minutes A1M2 M40 M20 M10 M8 M4 M2 M1 09 Alarm 1: Hours A1M3 12, /24 H10 H8 H4 H2 H1 0A Alarm 1: Day, Date A1M4 Day, /Date H20 or A, /P 0, D20 0, D10 0, D8 W4, D4 W2, D2 W1, D1 0B Alarm 2: Minutes A2M2 M40 M20 M10 M8 M4 M2 M1 0C Alarm 2: Hours A2M3 12, /24 H10 H8 H4 H2 H1 0D Alarm 2: Day, Date A2M4 Day, /Date H20 or A, /P 0, D20 0, D10 0, D8 W4, D4 W2, D2 W1, D1 0E Control /ETIME 0 0 RS2 RS1 INTCN A2IE A1IE 0F Status OSF 0 0 0 0 0 A2F A1F Note: Alarm function does not support different hour system adopted in time and alarm register. The PT7C4337 contains two time-of-day/date alarms. The alarms can be programmed (by the INTCN bit of the control register) to operate in two different modes - each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of each of the time-of-day/date alarm registers are mask bits. When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h ~ 04h match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 2 and Table 3 shows the possible settings. The Day, /Date bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 ~ 5 of that register reflects the day of the week or the date of the month. If the bit is written to logic 0, the alarm is the result of a match with date of the month. If the bit is written to logic 1, the alarm is the result of a match with day of the week. When the PT7C4337 register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set to logic 1. If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1, the alarm condition activates one of the interrupt output (INTA or SQW/INTB) signals. The match is tested on the once-per-second update of the time and date registers. 2013-06-0002 PT0205-9 14 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Table 1. Alarm 1 Mask Bits Alarm 1 register mask bits Day, /Date A1M4 A1M3 A1M2 A1M1 Alarm rate 1 1 1 1 Alarm once per second 1 1 1 0 1 1 0 0 Alarm when seconds match Alarm when minutes and seconds match 1 0 0 0 Alarm when hours, minutes, and seconds match 0 0 0 0 0 Alarm when date, hours, minutes, and seconds match 1 0 0 0 0 Alarm when day, hours, minutes, and seconds match Others Ignored. Table 2. Alarm 2 Mask Bits Alarm 2 register mask bits Day, /Date A2M4 A2M3 A2M2 1 1 1 Alarm rate Alarm once per minute (00 seconds of every minute) 1 1 0 Alarm when minutes match 0 1 0 0 Alarm when hours, minutes 0 0 0 Alarm when date, hours, and minutes match 1 0 0 0 Alarm when day, hours, and minutes match Others Ignored. 2013-06-0002 PT0205-9 15 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| I2C Bus Interface Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. System Configuration All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed). Fig 1. System configuration Vcc RP RP SDA SCL Master MCU Slave RTC Other Peripheral Device Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required. 2013-06-0002 PT0205-9 16 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Starting and Stopping I2C Bus Communications Fig 2. Starting and stopping on I2C bus 1) START condition, repeated START condition, and STOP condition a) START condition SDA level changes from high to low while SCL is at high level b) STOP condition SDA level changes from low to high while SCL is at high level c) Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. 2) Data Transfers and Acknowledge Responses during I2C-BUS Communication a) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. *Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition. b) Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level. 2013-06-0002 PT0205-9 17 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| SCL from Master 1 8 2 SDA from transmitter (sending side) 9 Release SDA Low active SDA from receiver (receiving side) ACK signal After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master. Slave Address The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. Table Slave address R / W bit Operation Transfer data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read D1 h 1 (= Read) 1 1 0 1 0 0 0 Write D0 h 0 (= Write) I2C Bus’s Basic Transfer Format S Start indication Sr Restart indication P Stop indication 2013-06-0002 A RTC Acknowledge A Master Acknowledge PT0205-9 18 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 1) Write via I2C bus Slave address (7 bits) S 1 Start 1 0 1 0 write 0 0 Addr. setting A A 0 A C K Slave address + write specification A C K Address Specifies the write start address. bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Write data A P A C K Stop 2) Read via I2C bus a) Standard read Slave address (7 bits) S 1 Start 1 0 1 0 0 write 0 Slave address (7 bits) 1 1 0 1 0 0 A C K Read 0 A 1 A C K Restart Slave address + read specification b) A 0 Slave address + write specification Sr Addr. setting A A C K Address Specifies the read start address. bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (1) Data is read from the specified start address and address auto increment. A A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 /A P N O Stop Data read (2) Address auto increment to set the address for the next data to be read. A C K Simplified read Slave address (7 bits) S 1 Start 1 0 1 0 0 Read 0 Slave address + read specification A 1 A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (1) Data is read from the address pointed by the internal address register and address auto increment. A A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (2) Address register auto increment to set the address for the next data to be read. /A P N O Stop A C K Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses. 2013-06-0002 PT0205-9 19 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information WE (Lead free and Green SOIC-8) Symbol A A1 A2 b c D E E1 e L θ Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012E/AA 2013-06-0002 Dimensions In Millimeters Min Max 1.350 1.750 0.100 0.250 1.350 1.550 0.330 0.510 0.170 0.250 4.700 5.100 3.800 4.000 5.800 6.200 1.27 BSC 0.400 1.270 0° 8° PT0205-9 20 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| UE(Lead free and Green MSOP-8) Symbol Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MO-187E/BA 2013-06-0002 A A1 A2 b c D E E1 e L θ Dimensions In Millimeters Min Max 0.82 1.10 0.02 0.15 0.75 0.95 0.25 0.38 0.09 0.23 2.90 3.10 2.90 3.10 4.75 5.05 0.65 BSC 0.40 0.80 0° 6° PT0205-9 21 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| LE (Lead free and Green 8-Pin TSSOP) PKG. DIMENSIONS(MM) SYMBOL MIN MAX A 1.20 A1 0.02 0.15 A2 0.80 1.00 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 4.30 4.50 E1 6.25 6.55 e 0.65 BSC L 0.50 0.70 θ 1° 7° Note: 1) Controlling dimensions in millimeters. 2013-06-0002 PT0205-9 22 06/18/13 PT7C4337 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ZEE (Lead free and Green 8-Pin TDFN) PKG. DIMENSIONS(MM) SYMBOL MIN. MAX A 0.700 0.800 A1 0.000 0.500 0.203REF A3 D 1.924 2.076 E 2.924 3.076 D1 1.400 1.600 E1 1.400 1.600 0.200MIN k b 0.200 0.300 0.500TYP e L 0.224 0.376 Note: Ref: JEDEC MO-229 Ordering Information Part Number PT7C4337WE PT7C4337UE PT7C4337ZEE PT7C4337LE Package Code W U ZE L Package Lead free and Green 8-Pin SOIC Lead free and Green 8-Pin MSOP Lead free and Green 8-Pin TDFN Lead free and Green 8-Pin TSSOP Notes: E = Pb-free or Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 2013-06-0002 PT0205-9 23 06/18/13