MAXIM MAX13000E

19-3692; Rev 0; 6/05
超低电压电平转换器
____________________________________特性
MAX13000E–MAX13005E是6通道电平转换器，能够为多
电压系统的数据传输提供电平转换功能。外接电源电压
VCC 和VL 分别设置器件两侧的逻辑电平。器件VL 侧的逻
辑信号在器件的VCC 侧转换为高压逻辑信号，反之亦然。
♦ 保证数据速率：
230kbps (MAX13000E/MAX13001E/MAX13002E)
20Mbps (MAX13003E/MAX13004E/MAX13005E)
MAX13000E–MAX13005E具有小于4µA的VCC 和VL 静态电
源电流。MAX13000E–MAX13005E还为VCC 侧的I/O提供
±15kV ESD 保护，在连接外部信号时，可提供更强的保
护。ESD 保护符合人体模型标准 (HBM)。MAX13000E/
MAX13001E/MAX13002E保证工作于230kbps的数据速率。
MAX13003E/MAX13004E/MAX13005E则可在VCC > +1.65V
的情况下，保证工作于20Mbps的数据速率。
MAX13000E/MAX13003E是双向电平转换器，允许在任意
一条数据线上进行双向 (V L ↔ V CC ) 电平转换，而无需
DIRECTION 输入来控制方向。MAX13001E/MAX13002E/
MAX13004E/MAX13005E为单向电平转换器，可在数据线
的一个方向上进行数据电平的转换 (VL → VCC 或VCC →
VL)。MAX13001E/MAX13002E/MAX13004E/MAX13005E单
向转换器的输入可与CMOS和开漏极 (OD) 输出连接。若
想了解更多信息，请参见 定购信息、选型指南 和 输入驱
动要求 部分。
MAX13000E–MAX13005E的VL 电压范围为+0.9V至+3.6V，
VCC 电压范围为+1.5V至+3.6V。MAX13000E–MAX13005E
采用 16 焊球 UCSP TM 和 16 引脚 TSSOP 封装，可在-40°C 至
+85°C扩展工业级温度范围保证性能指标。
____________________________________应用
♦ 双向电平转换，无需DIRECTION输入控制
♦ VL 电压可低至+0.9V，VCC 电压可低至+1.5V
♦ VCC 侧I/O线具有±15kV ESD保护 (人体模型)
♦ 低静态电流：< 4µA
♦ 使能/关断控制
♦ 2mm x 2mm、16焊球UCSP封装和带引脚封装
♦ 可与CMOS或开漏极输出连接
UCSP是Maxim Integrated Products, Inc.的商标。
SPI是Motorola, Inc.的商标。
MICROWIRE是National Semiconductor Corp.的商标。
________________________________定购信息
PART
MAX13000EEUE
-40°C to +85°C
16 TSSOP
________________________________引脚配置
BOTTOM VIEW
MAX13000E/MAX13003E
漏极开路I/O转换
I/OVCC3
VCC
GND
I/OVCC4
I/OVCC1
I/OVCC2
I/OVCC5
I/OVCC6
I/OVL1
I/OVL2
I/OVL5
I/OVL6
I/OVL3
VL
EN
I/OVL4
1
2
3
4
D
低压ASIC电平转换
蜂窝电话
PINPACKAGE
定购信息后续于本数据资料末尾。
CMOS逻辑电平转换器
OD至CMOS信号变换
TEMP RANGE
C
SPI TM 和MICROWIRE TM 电平转换
智能读卡器
B
便携式POS系统
便携式通信设备
低成本串行接口
A
电信设备
4 X 4 UCSP
引脚配置后续于本数据资料末尾。
典型工作电路和选型指南见本数据资料末尾。
________________________________________________________________ Maxim Integrated Products
1
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MAX13000E– MAX13005E
____________________________________概述
MAX13000E– MAX13005E
超低电压电平转换器
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to GND.
VCC ...........................................................................-0.3V to +4V
VL ..............................................................................-0.3V to +4V
I/OVCC_ .......................................................-0.3V to (VCC + 0.3V)
I/OVL_ ............................................................-0.3V to (VL + 0.3V)
EN .................................................................-0.3V to (VL + 0.3V)
Short-Circuit Duration I/OVL_, I/OVCC_ to GND ..........Continuous
Continuous Power Dissipation (TA = +70°C)
16-Pin TSSOP (derate 9.4mW/°C at +70°C) ................755mW
16-Bump UCSP (derate 8.2mW/°C at +70°C) .............659mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
VL Supply Range
VCC Supply Range
Supply Current from VCC
(Note 3)
SYMBOL
VL
VCC
IQVCC
CONDITIONS
UNITS
0.9
VCC
V
1.5
3.6
V
TA = +25°C
4
TA = +85°C
40
IQVL
ISHDN-VCC
MAX
(Note 2)
TA = +85°C
VCC Shutdown Supply Current
(Note 3)
TYP
VL ≤ VCC (Note 2)
TA = +25°C
Supply Current from VL (Note 3)
MIN
(Note 3)
1
VL < VCC - 0.2V
(Note 3)
5
2
4
VL < VCC - 0.2V
40
2
EN = GND, TA = +85°C
20
VL < VCC - 0.2V,
EN = GND
EN = GND
VL Shutdown Supply Current
(Note 3)
TA = +85°C
1
4
VL < VCC - 0.2V,
EN = GND
20
EN = GND
40
I/O VL_, I/O VCC_,
EN = GND
TA = +25°C
0.35
TA = +85°C
1
I/O Tri-Stated Output Leakage
Current
VL < VCC - 0.2V, I/O
VL_, I/O VCC_,
EN = GND
TA = +25°C
0.2
TA = +85°C
0.5
2
µA
2
I/O Tri-State Output Leakage
Current
EN Input Leakage Current
µA
20
EN = GND, TA = +25°C
TA = +25°C
µA
µA
µA
µA
TA = +25°C
0.35
TA = +85°C
1
_______________________________________________________________________________________
µA
超低电压电平转换器
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2/3 × VL
V
LOGIC-LEVEL THRESHOLDS
I/OVL_ Input-Voltage-High
Threshold
VIHL
I/OVL_ Input-Voltage-Low
Threshold
VILL
I/OVCC_ Input-Voltage-High
Threshold
VIHC
I/OVCC_ Input-Voltage-Low
Threshold
VILC
EN Input-Voltage-High Threshold
VIHEN
EN Input-Voltage-Low Threshold
VILEN
I/OVL_ Output-Voltage High
VOHL
I/OVL_ Output-Voltage Low
I/OVCC_ Output-Voltage High
I/OVCC_ Output-Voltage Low
VOLL
VOHC
VOLC
1/3 × VL
V
2/3 ×
VCC
1/3 ×
VCC
V
2/3 × VL
I/OVL_ source current = 20µA
V
1/3 × VL
V
VL 0.25
V
MAX13002E/MAX13005E,
OVL_ sink current = 1µA
0.3
MAX13000E/MAX13001E/MAX13003E/
MAX13004E, I/OVL_ sink current = 20µA
0.25
I/OVCC_ source current = 20µA
V
V
VCC 0.25
V
MAX13001E/MAX13004E,
OVCC_ sink current = 1µA
0.3
MAX13000E/MAX13002E/MAX13003E/
MAX13005E, I/OVCC_ sink current = 20µA
0.25
V
OUTPUT CURRENTS
Output Sink Current During
Transient (VCC Side)
Output Sink Current During
Transient (VL Side)
VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
25
mA
VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
VL = +1.2V, VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
30
VL = +1.2V, VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
mA
_______________________________________________________________________________________
3
MAX13000E– MAX13005E
ELECTRICAL CHARACTERISTICS (continued)
MAX13000E– MAX13005E
超低电压电平转换器
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
SYMBOL
Output Source Current During
Transient (VCC Side)
CONDITIONS
MIN
TYP
VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
22
VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
VL = +1.2V, VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
25
VL = +1.2V, VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
MAX
UNITS
mA
Output Source Current During
Transient (VL Side)
mA
ESD PROTECTION
I/OVCC_
Human Body Model
±15
Air-Gap Discharge (IEC61000-4-2)
±10
Contact Discharge (IEC61000-4-2)
±8
kV
TIMING CHARACTERISTICS
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
I/OVCC_ Rise Time
SYMBOL
tRVCC
CONDITIONS
tFVCC
MAX
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 1a, 1b
15
400
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 1a, 1b
15
400
_______________________________________________________________________________________
UNITS
ns
1400
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 1a, 1b
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
4
TYP
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 1a, 1b
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
I/OVCC_ Fall Time
MIN
1400
ns
超低电压电平转换器
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
I/OVL_ Rise Time
SYMBOL
tRVL
CONDITIONS
tFVL
MAX
15
CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15
300
15
CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 1a, 1b
300
I/OVCC-VL
Propagation Delay from
I/OVL to I/OVCC_ after EN
(Note 5)
ns
ns
1200
20
ns
I/OVL-VCC
Propagation Delay
(Driving I/OVCC_)
UNITS
1200
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
Propagation Delay
(Driving I/OVL_)
TYP
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
I/OVL_ Fall Time
MIN
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
1000
VCC > +1.65V, CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20
VCC = 1.5V, CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
1000
CI/OVCC = 50pF, CMOS output, Figure 3
2
CI/OVCC = 50pF, OD output, Figure 3
6
ns
µs
tEN-VCC
_______________________________________________________________________________________
5
MAX13000E– MAX13005E
TIMING CHARACTERISTICS (continued)
TIMING CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
SYMBOL
Propagation Delay from
I/OVCC to I/OVL after EN
(Note 5)
CONDITIONS
MIN
TYP
MAX
CI/OVL = 50pF, CMOS output, Figure 4
2
CI/OVL = 50pF, OD output, Figure 4
6
Channel-to-Channel Skew
tSKEW
Part-to-Part Skew (Note 6)
UNITS
µs
tEN-VL
Each translator equally loaded,
MAX13003E/MAX13004E/MAX13005E
±5
ns
tPPSKEW
Maximum Data Rate
Each translator equally loaded,
MAX13000E/MAX13001E/MAX13002E
±250
CI/OVL = 15pF, CI/OVCC = 15pF,
VL = +1.8V, VCC = +2V, ΔT = +5°C,
MAX13003E/MAX13004E/MAX13005E
10
ns
MAX13003E/MAX13004E/MAX13005E
VCC > +1.65V, CI/OVL = 50pF,
CI/OVCC = 50pF
20
Mbps
MAX13000E/MAX13001E/MAX13002E
CI/OVL = 50pF, CI/OVCC = 50pF
230
kbps
Note 1: All devices are 100% production tested at TA = +25°C. Limits are guaranteed by design over the entire temperature range.
Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 3: This consumption is referred to as no signal transmission.
Note 4: Guaranteed by design with an input signal full swing, rise/fall time ≤ 3ns, source resistance is 50Ω.
Note 5: Enable input signal full swing and rise/fall time ≤ 50ns.
Note 6: Guaranteed by design, not production tested.
_______________________________________________________________________典型工作特性
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
10
DATA RATE = 230kbps
1
0.1
0.1
0.01
DATA RATE = 230kbps
1.8
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
3.3
3.6
DATA RATE = 20Mbps
1
0.1
DATA RATE = 230kbps
0.01
0.001
1.5
6
DATA RATE = 20Mbps
10
VCC SUPPLY CURRENT (mA)
100
MAX13000Etoc02
DATA RATE = 20Mbps
1
VL SUPPLY CURRENT (mA)
MAX13000Etoc01
1000
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VL = 0.9V)
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VCC, VL = 0.9V)
MAX13000Etoc03
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VL = 0.9V)
VL SUPPLY CURRENT (μA)
MAX13000E– MAX13005E
超低电压电平转换器
1.5
1.8
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
3.3
3.6
1.5
1.8
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3.3
3.6
超低电压电平转换器
VL SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
0.1
DATA RATE = 230kbps
0.01
MAX13000E toc05
310
DATA RATE = 20Mbps
1.8
2.1
2.4
2.7
3.0
3.3
DATA RATE = 20Mbps
4.00
3.95
3.85
-40
3.6
4.05
3.90
290
1.5
-15
10
35
60
85
-40
-15
10
35
85
60
TEMPERATURE (°C)
TEMPERATURE (°C)
VL SUPPLY CURRENT vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
VCC SUPPLY CURRENT vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
RISE/FALL TIME vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
60
40
20
DATA RATE = 230kbps
6
5
4
3
8
7
DATA RATE = 230kbps
30
40
50
60
70
80
20
30
40
50
60
70
80
RISE/FALL TIME vs.
CAPACITIVE LOAD ON I/O VL
(DRIVING I/OVCC, = 3.3V, VL = +0.9V)
PROPAGATION DELAY vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC, = 3.3V, VL = +0.9V)
tF
5
4
3
tR
2
9.0
8.5
PROPAGATION DELAY (ns)
MAX31000Etoc10
6
8.0
7.5
7.0
6.5
6.0
1
5.5
0
5.0
10
20
30
40
50
60
70
CAPACITIVE LOAD (pF)
80
90 100
10
20
30
40
50
60
70
80
90 100
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
7
tF
3
90 100
CAPACITIVE LOAD (pF)
8
4
0
10
90 100
PROPAGATION DELAY vs.
CAPACITIVE LOAD ON I/O VL
(DRIVING I/OVCC, VCC = 3.3V, VL = +0.9V)
6.5
6.0
PROPAGATION DELAY (ns)
20
5
1
0
10
tR
6
2
2
1
0
MAX31000Etoc09
MAX31000Etoc08
DATA RATE = 20Mbps
7
MAX13000Etoc12
80
8
9
RISE/FALL TIME (ns)
DATA RATE = 20Mbps
100
9
VCC SUPPLY CURRENT (mA)
120
MAX31000Etoc07
SUPPLY VOLTAGE (V)
140
VL SUPPLY CURRENT (μA)
320
300
0.001
RISE/FALL TIME (ns)
330
4.10
MAX13000E toc06
1.0
340
MAX31000Etoc11
VCC SUPPLY CURRENT (mA)
DATA RATE = 20Mbps
VCC SUPPLY CURRENT (μA)
MAX13000Etoc04
10
VCC SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
VCC SUPPLY CURRENT (mA)
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/OVCC, VL = +0.9V)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
10
20
30
40
50
60
70
CAPACITIVE LOAD (pF)
80
90 100
10
20
30
40
50
60
70
80
90 100
CAPACITIVE LOAD (pF)
_______________________________________________________________________________________
7
MAX13000E–]MAX13005E
_____________________________________________________________________典型工作特性 (续)
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
_____________________________________________________________________典型工作特性 (续)
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
OD RAIL-TO-RAIL DRIVING (MAX13002E)
(DRIVING I/OVL, VCC = +3.3V,
VL = +0.9V, CI/OVCC = 56pF,
DATA RATE = 230kbps, RPULLUP = 15kΩ)
I/OVL_
500mV/div
GND
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 230kbps)
MAX31000Etoc15
MAX31000Etoc14
I/OVL_
500mV/div
GND
I/OVCC
2V/div
GND
I/OVCC
2V/div
GND
I/OVCC
2V/div
GND
1μs/div
2μs/div
200ns/div
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 20Mbps)
I/OVL_
500mV/div
GND
I/OVCC
2V/div
GND
VCC + VL SUPPLY CURRENT vs. FREQUENCY
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V)
I/OVL_
500mV/div
GND
I/OVCC
2V/div
GND
40ns/div
VCC + VL SUPPLY CURRENT (mA)
MAX31000Etoc17
MAX31000Etoc16
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 4Mbps)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I/OVL IS DRIVEN WITH A
0.9V SQUARE WAVE
VCC + VL
VCC
VL
100
10ns/div
4250
8400 12,550 16,700 20,850 25,000
FREQUENCY (kHz)
VOHL vs. IOHL FOR VL SIDE
(VCC = 3.3V)
VL = +2.5V
2.5
0.25
0.20
VL = +2.5V
VOHL (V)
VCC
VL
VL = +1.8V
1.5
8400 12,550 16,700 20,850 25,000
FREQUENCY (kHz)
VL = +1.8V
0.15
VL = +0.9V
0.10
1.0
VL = +0.9V
0.05
0.5
0
4250
VOLL (V)
VCC + VL
2.0
MAX13000Etoc21
I/OVCC IS DRIVEN WITH A
3.3V SQUARE WAVE
100
8
3.0
MAX31000Etoc19
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VOLL vs. IOLL FOR VL SIDE
(VCC = 3.3V)
MAX13000Etoc20
VCC + VL SUPPLY CURRENT vs. FREQUENCY
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
0
0
5
10 15 20 25 30 35 40 45 50
IOHL (μA)
I/OVL_
500mV/div
GND
MAX31000Etoc18
MAX31000Etoc13
OD RAIL-TO-RAIL DRIVING (MAX13005E)
(DRIVING I/OVL, VCC = +3.3V,
VL = +0.9V, CI/OVCC = 56pF,
DATA RATE = 230Mbps, RPULLUP = 1kΩ)
VCC + VL SUPPLY CURRENT (mA)
MAX13000E– MAX13005E
超低电压电平转换器
0
5
10 15 20 25 30 35 40 45 50
IOLL (μA)
_______________________________________________________________________________________
超低电压电平转换器
VOLC (V)
0.20
VCC = +3.3V
VCC = +1.8V
0.10
VCC = +3.3V
3.0
VOHC (V)
VCC = +2.5V
0.15
3.5
MAX13000Etoc22
0.25
MAX13000Etoc23
VOHC vs.
IOHC FOR VCC SIDE
VOLC vs.
IOLC FOR VCC SIDE
VCC = +2.5V
2.5
2.0
VCC = +1.8V
1.5
0.05
1.0
0
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
IOHC (μA)
IOLC (μA)
_____________________________________________________________________________引脚说明
MAX13000E/MAX13003E
引脚
名称
功能
TSSOP
1
UCSP
B1
I/OVL1
CMOS输入/输出1，以VL 为参考。
2
B2
I/OVL2
CMOS输入/输出2，以VL 为参考。
3
A1
I/OVL3
CMOS输入/输出3，以VL 为参考。
4
A2
VL
逻辑输入电压，+0.9V ≤ VL ≤ VCC。在VL 和GND之间接0.1µF旁路电容。
5
A3
EN
使能输入。若EN置低，则I/O VCC1至I/O VCC6和I/O VL1至I/O VL6均为三态。
EN置高 (VL) 时正常工作。
6
A4
I/OVL4
CMOS输入/输出4，以VL 为参考。
7
B3
I/OVL5
CMOS输入/输出5，以VL 为参考。
8
B4
I/OVL6
CMOS输入/输出6，以VL 为参考。
9
C4
I/OVCC6
CMOS输入/输出6，以VCC 为参考。
10
C3
I/OVCC5
CMOS输入/输出5，以VCC 为参考。
11
D4
I/OVCC4
CMOS输入/输出4，以VCC 为参考。
12
D3
GND
地
13
D2
VCC
VCC 输入电压，+1.5V ≤ VCC ≤ 3.6V。在VCC 和GND之间接0.1µF旁路电容。
要实现完全的ESD保护，须在VCC 端接1µF旁路电容。
14
D1
I/OVCC3
CMOS输入/输出3，以VCC 为参考。
15
C2
I/OVCC2
CMOS输入/输出2，以VCC 为参考。
16
C1
I/OVCC1
CMOS输入/输出1，以VCC 为参考。
_______________________________________________________________________________________
9
MAX13000E– MAX13005E
_____________________________________________________________________典型工作特性 (续)
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
MAX13000E– MAX13005E
超低电压电平转换器
_______________________________________________________________________引脚说明 (续)
MAX13001E/MAX13004E
引脚
10
名称
功能
TSSOP
1
UCSP
B1
OVL1
CMOS输出1，以VL 为参考。
2
B2
OVL2
CMOS输出2，以VL 为参考。
3
A1
OVL3
CMOS输出3，以VL 为参考。
4
A2
VL
逻辑输入电压，+0.9V ≤ VL ≤ VCC。在VL 和GND之间接0.1µF旁路电容。
5
A3
EN
使能输入。若EN置低，则OVCC1至OVCC6和IVL1至IVL6均为三态。EN置高 (VL)
时正常工作。
6
A4
OVL4
CMOS输出4，以VL 为参考。
7
B3
OVL5
CMOS输出5，以VL 为参考。
8
B4
OVL6
CMOS输出6，以VL 为参考。
开漏极兼容的输入6，以VCC 为参考。
9
C4
IVCC6
10
C3
IVCC5
开漏极兼容的输入5，以VCC 为参考。
11
D4
IVCC4
开漏极兼容的输入4，以VCC 为参考。
12
D3
GND
地
13
D2
VCC
VCC 输入电压，+1.5V ≤ VCC ≤ 3.6V。在VCC 和GND之间接0.1µF旁路电容。要实
现完全的ESD保护，须在VCC 端接1µF旁路电容。
14
D1
IVCC3
15
C2
IVCC2
开漏极兼容的输入3，以VCC 为参考。
开漏极兼容的输入2，以VCC 为参考。
16
C1
IVCC1
开漏极兼容的输入1，以VCC 为参考。
______________________________________________________________________________________
超低电压电平转换器
MAX13002E/MAX13005E
引脚
名称
功能
TSSOP
1
UCSP
B1
IVL1
开漏极兼容的输入1，以VL 为参考。
2
B2
IVL2
开漏极兼容的输入2，以VL 为参考。
3
A1
IVL3
开漏极兼容的输入3，以VL 为参考。
4
A2
VL
逻辑输入电压，+0.9V ≤ VL ≤ VCC。在VL 和GND之间接0.1µF旁路电容。
5
A3
EN
使能输入。若EN置低，则OVCC1至OVCC6和IVL1至IVL6均为三态。EN置高 (VL)
时正常工作。
6
A4
IVL4
开漏极兼容的输入4，以VL 为参考。
7
B3
IVL5
开漏极兼容的输入6，以VL 为参考。
开漏极兼容的输入5，以VL 为参考。
8
B4
IVL6
9
C4
OVCC6
CMOS输出6，以VCC 为参考。
10
C3
OVCC5
CMOS输出5，以VCC 为参考。
11
D4
OVCC4
CMOS输出4，以VCC 为参考。
12
D3
GND
地
13
D2
VCC
VCC 输入电压，+1.5V ≤ VCC ≤ 3.6V。在VCC 和GND之间接0.1µF旁路电容。要实
现完全的ESD保护，须在VCC 端接1µF旁路电容。
14
D1
OVCC3
CMOS输出2，以VCC 为参考。
15
C2
OVCC2
CMOS输出3，以VCC 为参考。
16
C1
OVCC1
CMOS输出1，以VCC 为参考。
______________________________________________________________________________________
11
MAX13000E– MAX13005E
_______________________________________________________________________引脚说明 (续)
MAX13000E– MAX13005E
超低电压电平转换器
______________________________________________________________________测试电路/时序图
I/OVL_
90%
VL
VCC
50%
MAX13000E
10%
EN
tRISE/FALL
I/OVL-VCC
I/OVCC
I/OVL_
SOURCE
I/OVCC_
90%
RS
CI/OVCC
50%
10%
tFVCC
tRVCC
I/OVL-VCC
UNUSED I/Os ARE GROUNDED.
tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E)
tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E)
图1b. 驱动I/OVL 时序图
图1a. 驱动I/OVL
tRISE/FALL
VL
VCC
I/OVCC_
MAX13000E
90%
50%
EN
10%
I/OVCC-VL
I/OVL_
I/OVCC
I/OVL_
I/OVCC-VL
90%
50%
CI/OVL
RS
SOURCE
10%
tFVL
tRVL
tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E)
UNUSED I/Os ARE GROUNDED.
图2a. 驱动I/OVCC
12
tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E)
图2b. 驱动I/OVCC 时序图
______________________________________________________________________________________
超低电压电平转换器
VL
EN
EN
SOURCE
MAX13000E
t'EN-VCC
0
VL
I/OVCC
I/OVL_
I/OVL_
0
CI/OVCC
VL
VCC
VCC / 2
I/OVCC_
0
VL
t"EN-VCC
EN
SOURCE
MAX13000E
0
EN
I/OVL_
VL
I/OVCC_
0
VCC
I/OVCC
I/OVL_
CI/OVCC
VCC / 2
0
tEN-VCC IS WHICH EVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
图3. EN使能后，I/OVL 到I/OVCC 的传输延迟
VL
EN
VL
EN
SOURCE
MAX13000E
t'EN-VL
VCC
I/OVCC_
I/OVCC
I/OVL_
0
0
VL
CI/OVL
VCC
I/OVL_
VL / 2
0
VL
EN
VL
EN
SOURCE
t"EN-VL
MAX13000E
VCC
I/OVCC_
I/OVL_
CI/OVL
0
0
VL
I/OVCC
I/OVL_
VL / 2
0
tEN-VL IS WHICH EVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL.
图4. EN使能后，I/OVCC 到I/OVL 的传输延迟
______________________________________________________________________________________
13
MAX13000E– MAX13005E
__________________________________________________________________测试电路/时序图 (续)
MAX13000E– MAX13005E
超低电压电平转换器
________________________________详细说明
MAX13000E–MAX13005E逻辑电平转换器为多电压系统的
数据传输提供电平转换功能。外接电源电压 (V CC 和 V L )
设置器件两侧的逻辑电平。器件VL 侧的逻辑信号在器件
的VCC 侧转换为高压逻辑信号，反之亦然。
MAX13000E/MAX13003E 是双向电平转换器，允许在任
意一条数据线上双向 (V L ↔ V CC ) 转换数据电平，而
无需 DIRECTION 输入控制。MAX13001E/MAX13002E/
MAX13004E/MAX13005E为单向电平转换器，可在数据线
的一个方向 (VL → VCC 或VCC → VL) 进行数据电平的转
换。MAX13001E/MAX13002E/MAX13004E/MAX13005E单
向转换器的输入可与CMOS和开漏极 (OD) 输出连接。若
想了解更多信息，请参见定购信息 和输入驱动要求 部分。
MAX13000E–MAX13005E的VL 可接受+0.9V至+3.6V的电
压，所有器件的VCC 可接受+1.5V至+3.6V的电压，非常适
合低压ASIC/PLD与高压系统之间的数据传输。
MAX13000E–MAX13005E具有小于4µA的VCC 静态电源电
流，关断时 V L 静态电源电流低于 2µA。MAX13000E–
MAX13005E 还为VCC 侧的I/O提供±15kV ESD保护，当连
接外部信号时，可提供更强的保护。ESD保护符合人体模
型标准 (HBM)。MAX13000E/MAX13001E/MAX13002E保
证工作于230kbps的数据速率。MAX13003E/MAX13004E/
MAX13005E 则可在VCC > +1.65V的情况下，保证工作于
20Mbps的数据速率。
电平转换
为 使 芯 片 正 常 工 作 ， 需 确 保 +1.5V ≤ V CC ≤ +3.6V 和
+0.9V ≤ V L ≤ V CC。上电过程中，只要保证 V L 在极限参
数之内 (参见 Absolute Maximum Ratings )，即使出现 VL ≥
VCC 也不会损坏器件。上电过程中，如果VCC 端浮空而VL
端上电，允许VL 侧向每路负载源出1mA电流而不会使芯
片锁定。
MAX13000E–MAX13005E 设计用于工作在VCC ≥ VL 条件
下，不过，即使关断VCC，芯片也不会被损坏和锁定。为
了防止在I/O端口和电源线上有过大的漏电流，VL 侧的I/O
端口必须停留在高电平。
14
MAX13000E–MAX13005E最大的数据速率很大程度上取决
于负载电容 (详见 典型工作特性 )、驱动器输出阻抗和工
作电压范围 (详见 Timing Characteristics 表）。
开漏极工作
MAX13001E/MAX13002E/MAX13004E/MAX13005E的输入
级专为适应外部开漏驱动器而设计。当使用开漏极驱动
器时，MAX13001E/MAX13002E/MAX13004E/MAX13005E
工作在单向模式，从开漏极 (OD) 侧向CMOS侧转换信号。
为改善性能，在CMOS侧和OD侧都具有上升时间和下降
时间加速电路。参见 输入驱动器要求 部分。为保证正常
工作，上拉电阻阻值不要大于15kΩ，而且工作速度越高，
要求上拉电阻越小。
输入驱动器要求
MAX13000E–MAX13005E有4种不同的内部结构，分别提
供不同的工作速度，以及 CMOS 至 CMOS 或 OD 至 CMOS
转换。
20Mbps CMOS 至CMOS双向转换器
（MAX13003E）
MAX13003E采用一种单稳态触发加速器输出结构 (图5)。
稳态下加速器输出级始终处于三态，当任何一个转换器
的输入端 (I/OVL 或I/OVCC) 发生跳变时，单稳态触发输出
级，产生一个短脉冲，对I/O口上的电容进行充/放电。由
于其双向工作特性，当I/O口发生由低到高或者由高到低
的跳变时，I/OVCC 和I/OVL 端口上的加速器输出级均会被
触发。这会导致一部分电流被馈入正在驱动转换器的外
部信号源。不过，这有利于加速驱动侧信号电平的跳变。
通常，驱动MAX13003E输入级的器件都会有一个规定的
输出驱动电流容量 (IOUT)。在驱动MAX13003E的输入时，
可达到的最大速率受限于这个驱动电流。为了保证最
大可能的 20Mbps 数据速率，外部驱动器必须满足以下
条件：
IOUT ≥ 1.67 × 108 × V × (CIN + CP)
______________________________________________________________________________________
超低电压电平转换器
MAX13000E– MAX13005E
VL
VCC
P
ONE-SHOT
5kΩ
I/OVL
I/OVCC
INVERTER 2
INVERTER 1
N
ONE-SHOT
P
ONE-SHOT
5kΩ
INVERTER 4
INVERTER 3
N
ONE-SHOT
图5. 20Mbps CMOS 至CMOS双向转换器结构
其中，CP 是连线的寄生电容，V是驱动端的电源电压 (VL
或 V CC )，C IN 是驱动端的输入电容 (V L 侧 C IN = 10pF，
VCC 侧CIN = 20pF)。
20Mbps OD 至CMOS单向转换器
（MAX13004E/MAX13005E）
MAX13004E/MAX13005E 的结构与双向CMOS 至CMOS转
换器基本一样，唯一的区别在于驱动侧的输出反相器
(inverter 4)，该反相器能够适应开漏极输出的驱动能力
(见图6)。
为保证正常工作，开漏极输出与驱动侧电源之间需连接
一个上拉电阻。上拉电阻的阻值不能大于15kΩ。
230kbps CMOS至CMOS双向转换器
(MAX13000E)
MAX13000E 的结构中省掉了单稳态触发加速器输出级，
因为该器件只需要处理230kbps以内的数据速率 (见图7)。
为保证正常工作，驱动器必须满足以下条件：最大输出阻
抗1kΩ，最小输出电流1mA。
230kbps OD 至CMOS单向转换器
（MAX13001E/MAX13002E）
MAX13001E/MAX13002E 的结构与230kbps CMOS 至CMOS
双向转换器相似，区别仅在于它能够适应驱动侧开漏
极输出器件的驱动能力，并有一个单稳态触发输出级 (见
图8)。
为了正常工作，开漏极输出与驱动侧电源之间需连接一
个上拉电阻。上拉电阻的阻值不能大于15kΩ。
图9给出了上述各种结构的典型输入电流随输入电压变化
的曲线。
输出使能模式 (EN)
MAX13000E– MAX13005E 具有使能输入 (EN)。驱动EN为
低可设置 MAX13000E – MAX13005E的I/O端口为三态。正
常工作应驱动EN为高 (VL)。
±15kV ESD保护
和 Maxim 其他器件一样，该系列器件的所有引脚均带有
ESD保护结构，以免在装配和操作过程中的静电放电损坏
器件。I/OVCC 线上还具有更高的静电放电保护。Maxim工
程师开发的先进的ESD保护结构可提供高达±15kV的ESD
保护。这种ESD保护结构可在任何状态下承受高ESD冲击：
______________________________________________________________________________________
15
MAX13000E– MAX13005E
超低电压电平转换器
20Mbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR
VCC/VL
VL/VCC
P
ONE-SHOT
5kΩ
IVCC/IVL
OVL/OVCC
INVERTER 2
OPEN-DRAIN
COMPATIBLE INPUT
INVERTER 1
CMOSCOMPATIBLE INPUT
N
ONE-SHOT
P
ONE-SHOT
INVERTER 3
5kΩ
75kΩ
INVERTER
4
N
ONE-SHOT
图6. 20Mbps OD至CMOS单向转换器结构
230kbps Bidirectional CMOS-TO-CMOS Level Translator
VL
VCC
5kΩ
I/OVL
I/OVCC
INVERTER 1
INVERTER 2
5kΩ
INVERTER 4
INVERTER 3
图7. 230kbps CMOS至CMOS双向转换器结构
16
______________________________________________________________________________________
超低电压电平转换器
MAX13000E– MAX13005E
230kbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR
VCC/VL
VL/VCC
5kΩ
IVCC/IVL
OVL/OVCC
INVERTER 1
OPEN-DRAIN
COMPATIBLE INPUT
INVERTER 2
CMOSCOMPATIBLE INPUT
INVERTER 3
5kΩ
75kΩ
INVERTER
4
5kΩ
N
ONE-SHOT
图8. 230kbps OD至CMOS单向转换器结构
正常工作、三态输出模式以及断电。ESD 冲击过后，
Maxim器件保持正常工作而不会锁定，而竞争者的产品则
需要断电，以解除锁定状态。
IIN
ESD 保护具有多种不同测试方法。MAX13000E–MAX13005E
的I/OVCC 线采用±15kV的人体模型进行测试。
VTH_IN / RIN1
ESD测试条件
0
VTH_IN
VIN
VS
WHERE, VS = VCC OR VL
(VS - VTH_IN) /
RIN2
RIN1 = RIN2 = 5kΩ FOR CMOS-TO-CMOS TRANSLATORS
RIN1 = 75kΩ FOR OD-TO-CMOS TRANSLATORS
ESD性能依赖于诸多因素。如需可靠性报告，请与Maxim
公司联系，该报告详细说明了测试装置、测试方法和测
试结果。
人体模型
图 10 表示人体模型，图 11 给出了当它通过低阻放电时产
生的电流波形。该模型包括一个100pF的电容，被充电至
ESD目标电压，然后，经过一个1.5kΩ电阻，通过待测器
件对其放电。
图9. 典型IIN 随VIN 的变化
______________________________________________________________________________________
17
MAX13000E– MAX13005E
超低电压电平转换器
RC 1MΩ
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
CS
100pF
RC
50Ω TO 100Ω
RD 1500Ω
DISCHARGE
RESISTANCE
CHARGE-CURRENTLIMIT RESISTOR
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
HIGHVOLTAGE
DC
SOURCE
Cs
150pF
RD
330Ω
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
图10. 人体ESD测试模型
图12. IEC 61000-4-2接触放电测试模型
IP 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
关于UCSP封装的考虑
AMPERES
关于 UCSP 封装的一般性信息及其印制板布局方面的考
虑，可参考 Maxim应用笔记：晶片级封装。
36.8%
10%
0
0
tRL
TIME
UCSP可靠性
tDL
CURRENT WAVEFORM
图11. 人体模型电流波形
IEC 61000-4-2标准ESD保护
IEC 61000-4-2 标准规定了电子系统的 ESD 耐受力。IEC
61000-4-2模型规定，采用150pF电容通过330Ω电阻对测试
器件放电。 MAX13000E–MAX13005E的VCC 侧I/O端口满
足 IEC 61000-4-2标准（8kV接触放电，±10kV气隙放电）
。
IEC 61000-4-2模型具有比HBM更高的放电峰值电流和更
高的能量，因为采用较低的串联电阻和较大的电容。
________________________________应用信息
晶片级封装 (UCSP) 是一种特殊的封装形式，或许不能象
其他封装产品那样通过传统的机械可靠性测试。UCSP的
可靠性与用户的组装工艺、电路板材料以及使用环境密
切相关。用户考虑使用UCSP封装时，请仔细审视这几个
方面。工作寿命测试期间的性能和抗潮湿能力与传统封
装相比没有差异，因为这主要取决于晶片生产工艺。
机械应力性能是 UCSP 封装需要重点考虑的一个问题。
UCSP芯片通过焊接直接附着在用户的印制板上，不再具
有传统封装产品所固有的、由引线架所提供的应力缓解
机制。焊接点的完整性也要考虑。有关Maxim的质量认证
计划、测试数据和建议，请参考 UCSP 应用笔记 (可在
Maxim网站：www.maxim-ic.com.cn上找到)。
电源退耦
为降低纹波和数据出错的概率，使用0.1µF的陶瓷电容将
V L 和 V CC 旁路至地。为了确保完全的 ±15kV ESD 保护，
需采用1µF电容旁路VCC 到地。所有电容应尽可能靠近电
源引脚放置。
18
______________________________________________________________________________________
超低电压电平转换器
VL
VCC
EN
MAX13000E–MAX13005E
I/OVL1
I/OVCC1
I/OVL2
I/OVCC2
I/OVL3
I/OVCC3
I/OVL4
I/OVCC4
I/OVL5
I/OVCC5
I/OVL6
I/OVCC6
GND
______________________________________________________________________________________
19
MAX13000E– MAX13005E
___________________________________________________________________________功能框图
MAX13000E– MAX13005E
超低电压电平转换器
_______________________________________________________________________典型工作电路
+0.9V
+2.8V
0.1μF
1μF
VCC
VL
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
MAX13001E
DATA1
DATA2
EN
MAX13004E
OVL_1
IVCC_1
OVL_2
IVCC_2
DATA3
OVL_3
IVCC_3
DATA3
DATA4
OVL_4
IVCC_4
DATA4
DATA5
OVL_5
IVCC_5
DATA5
DATA6
OVL_6
IVCC_6
DATA6
DATA1
DATA2
GND
+0.9V
+2.8V
0.1μF
1μF
VCC
VL
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
MAX13002E
DATA1
DATA2
EN
MAX13005E
IVL_1
OVCC_1
IVL_2
OVCC_2
DATA3
IVL_3
OVCC_3
DATA3
DATA4
IVL_4
OVCC_4
DATA4
DATA5
IVL_5
OVCC_5
DATA5
DATA6
IVL_6
OVCC_6
DATA6
DATA1
DATA2
GND
20
______________________________________________________________________________________
超低电压电平转换器
+0.9V
+2.8V
0.1μF
1μF
VCC
VL
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
MAX13000E
DATA1
DATA2
EN
MAX13003E
I/OVL_1
I/OVCC_1
I/OVL_2
I/OVCC_2
DATA3
I/OVL_3
I/OVCC_3
DATA3
DATA4
I/OVL_4
I/OVCC_4
DATA4
DATA5
I/OVL_5
I/OVCC_5
DATA5
DATA6
I/OVL_6
I/OVCC_6
DATA6
DATA1
DATA2
GND
____________________________________________________________________________选型指南
DATA
RATE
(bps)
NUMBER OF
BIDIRECTIONAL
TRANSLATORS
NUMBER OF
VL → VCC
TRANSLATORS
NUMBER OF
VCC → VL
TRANSLATORS
MAX13000E
230k
6
—
—
CMOS-to-CMOS
MAX13001E
230k
—
—
6
OD-to-CMOS
MAX13002E
230k
—
6
—
OD-to-CMOS
MAX13003E
20M
6
—
—
CMOS-to-CMOS
MAX13004E
20M
—
—
6
OD-to-CMOS
MAX13005E
20M
—
6
—
OD-to-CMOS
PART
TRANSLATOR
CONFIGURATION
______________________________________________________________________________________
21
MAX13000E– MAX13005E
___________________________________________________________________典型工作电路 (续)
MAX13000E– MAX13005E
超低电压电平转换器
_______________________________________________________________________引脚配置 (续)
BOTTOM VIEW
MAX13001E/MAX13004E
IVCC3
VCC
GND
MAX13002E/MAX13005E
IVCC4
D
OVCC3
VCC
GND
OVCC4
OVCC1
OVCC2
OVCC5
OVCC6
IVL1
IVL2
IVL5
IVL6
IVL3
VL
EN
IVL4
2
3
4
D
IVCC1
IVCC2
IVCC5
IVCC6
C
C
OVL1
OVL2
OVL5
OVL6
B
B
OVL3
VL
EN
OVL4
A
A
2
1
3
4
1
4 X 4 UCSP
4 X 4 UCSP
TOP VIEW
I/OVL1 1
16 I/OVCC1
OVL1 1
16 IVCC1
IVL1 1
16 OVCC1
I/OVL2 2
15 I/OVCC2
OVL2 2
15 IVCC2
IVL2 2
15 OVCC2
I/OVL3 3
14 I/OVCC3
OVL3 3
14 IVCC3
IVL3 3
14 OVCC3
VL 4
EN 5
13 VCC
MAX13000E
MAX13003E
EN 5
13 VCC
MAX13001E
MAX13004E
VL 4
12 GND
EN 5
13 VCC
MAX13002E
MAX13005E
12 GND
I/OVL4 6
11 I/OVCC4
OVL4 6
11 IVCC4
IVL4 6
11 OVCC4
I/OVL5 7
10 I/OVCC5
OVL5 7
10 IVCC5
IVL5 7
10 OVCC5
I/OVL6 8
9
OVL6 8
9
IVL6 8
9
TSSOP
22
12 GND
VL 4
I/OVCC6
TSSOP
IVCC6
TSSOP
______________________________________________________________________________________
OVCC6
超低电压电平转换器
PART
TEMP RANGE
PINPACKAGE
MAX13000EEBE-T*
-40°C to +85°C
16 UCSP-16
(4mm × 4mm)
MAX13001EEUE
-40°C to +85°C
16 TSSOP
MAX13001EEBE-T*
-40°C to +85°C
16 UCSP-16
(4mm × 4mm)
MAX13002EEUE
-40°C to +85°C
16 TSSOP
MAX13002EEBE-T*
-40°C to +85°C
16 UCSP-16
(4mm × 4mm)
MAX13003EEUE
-40°C to +85°C
16 TSSOP
MAX13003EEBE-T*
-40°C to +85°C
16 UCSP-16
(4mm × 4mm)
MAX13004EEUE
-40°C to +85°C
16 TSSOP
MAX13004EEBE-T*
-40°C to +85°C
16 UCSP-16
(4mm × 4mm)
MAX13005EEUE
-40°C to +85°C
16 TSSOP
MAX13005EEBE-T*
-40°C to +85°C
16 UCSP-16
(4mm × 4mm)
________________________________芯片信息
PROCESS: BiCMOS
* 未来产品 —— 供货状况请联络厂方。
______________________________________________________________________________________
23
MAX13000E– MAX13005E
____________________________定购信息 (续)
____________________________________________________________________________封装信息
(本数据资料提供的封装图可能不是最近的规格，如需最近的封装外型信息，请查询 www.maxim-ic.com.cn/packages。)
TSSOP4.40mm.EPS
MAX13000E– MAX13005E
超低电压电平转换器
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
24
______________________________________________________________________________________
G
1
1
超低电压电平转换器
16L,UCSP.EPS
PACKAGE OUTLINE, 4x4 UCSP
21-0101
H
1
1
MAXIM 北京办事处
北京 8328信箱 邮政编码 100083
免费电话：800 810 0310
电话：010-6211 5199
传真：010-6211 5299
Maxim不对Maxim产品以外的任何电路使用负责，也不提供其专利许可。Maxim保留在任何时间、没有任何通报的前提下修改产品资料和规格的权利。
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2005 Maxim Integrated Products
Printed USA
是 Maxim Integrated Products, Inc. 的注册商标。
MAX13000E– MAX13005E
__________________________________________________________________________封装信息 (续 )
(本数据资料提供的封装图可能不是最近的规格，如需最近的封装外型信息，请查询 www.maxim-ic.com.cn/packages。)
MAX13000E, MAX13001E, MAX13002E, MAX13003E, MAX13004E, MAX13005E 超低电压电平转换器 - 概述
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Maxim > 产品 > 接口、互联、信号完整 > MAX13000E, MAX13001E, ...
MAX13000E, MAX13001E, MAX13002E, MAX13003E, MAX13004E, MAX13005E
超低电压电平转换器
6通道、超低电压、双向电平转换器
概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况
状况：生产中。
概述
数据资料
MAX13000E–MAX13005E是6通道电平转换器，能够为多电压系统的数据传输提供电平转换功能。外 接电源电压VCC和VL 分别设置器件两侧的逻辑电平。器件VL 一侧的逻辑信号在器件的VCC一侧转换为高
压逻辑信号，反之亦然。
完整的数据资料
提供更新的英文版数据资料
英文
MAX13000E–MAX13005E具有小于4µA的VCC和VL 静态电源电流。MAX13000E–MAX13005E还
为VCC侧的I/O提供±15kV ESD保护，可在具有外部信号走线的应用中提供更强大的保护。ESD保护采
用人体模型(HBM)。MAX13000E/MAX13001E/MAX13002E能够确保实现230kbps的数据速
率。MAX13003E/MAX13004E/MAX13005E则可在VCC > +1.65V的情况下，确保实现20Mbps的数据
速率。
下载
中文
Rev. 1 (PDF, 292kB)
E-Mail
下载
Rev. 0 (PDF, 948kB)
E-Mail
MAX13000E/MAX13003E是双向电平转换器，允许在任意单根数据线上进行双向(VL <—> VCC)电平转
换，而无需DIRECTION输入控制。MAX13001E/MAX13002E/MAX13004E/ MAX13005E为单向电平转
换器，可在任意单根数据线上进行单向电平转换(VL —> VCC或VCC —>
VL )。MAX13001E/MAX13002E/MAX13004E/MAX13005E单向转换器的输入可与CMOS和开漏
极(OD)输出连接。若想了解更多信息，请参见完整数据资料中的定购信息、选型指南和输入驱动器要
求部分。
MAX13000E–MAX13005E的VL 电压范围为+0.9V至+3.6V，VCC电压范围
为+1.5V至+3.6V。MAX13000E–MAX13005E采用16焊球UCSP™和16引脚TSSOP封装，可工作在40°C至+85°C扩展级温度范围。
关键特性
应用/使用
可保证的数据速率选项
230kbps (MAX13000E/MAX13001E/MAX13002E)
20Mbps (MAX13003E/MAX13004E/MAX13005E)
双向电平转换，无DIRECTION输入控制
VL 电压可低至+0.9V，VCC电压可低至+1.5V
VCC侧I/O线具有±15kV ESD保护(HBM)
低静态电流：<4µA
使能/关断控制
2mm x 2mm、16焊球UCSP封装以及引脚封装
可连接CMOS或开漏极输出
蜂窝电话
CMOS逻辑电平转换
低成本串行接口
低电压ASIC电平转换
OD至CMOS信号变换
漏极开路I/O转换
便携式通信设备
便携式POS系统
智能读卡器
SPI™和MICROWIRE™电平转换
电信设备
Key Specifications: Logic Level Translators
Part Number
Level
Transl.
VL
(V)
V CC
(V)
Data
Rate
(Mbps)
Features
max
I/O V CC
State
I/O V L
State
Shutdn.
Shutdn.
I CC
IL
I CC V L
Budgetary
(Shutdn.) (Shutdn.)
Price
(µA) (µA)
(µA)
(µA)
max max
max
max
See Notes
MAX13000E 0.23
Bidirectional
CMOS/ Push-Pull
Drive
MAX13001E 0.23
CMOS/ Push-Pull
Drive
Open Drain Drive
-
MAX13002E 0.23
CMOS/ Push-Pull
Drive
Open Drain Drive
-
0.9 to
1.5 to
http://china.maxim-ic.com/datasheet/index.mvp/id/4759[2011-05-19 10:30:02]
High
High
-
MAX13000E, MAX13001E, MAX13002E, MAX13003E, MAX13004E, MAX13005E 超低电压电平转换器 - 概述
6
40
40
2
1
20
Bidirectional
CMOS/ Push-Pull
Drive
Open Drain Drive
MAX13004E 20
CMOS/ Push-Pull
Drive
Open Drain Drive
-
MAX13005E 20
CMOS/ Push-Pull
Drive
Open Drain Drive
-
MAX13003E 3.6
3.6
Impedance
Impedance
查看所有Logic Level Translators (55)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may
differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized
distributor.
图表
典型工作电路
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MAX13000E, MAX13001E, MAX13002E, MAX13003E, MAX13004E, MAX13005E 超低电压电平转换器 - 概述
参数搜索
应用帮助
概述
技术文档
定购信息
相关产品
概述
关键特性
应用/ 使用
关键指标
图表
注释、注解
数据资料
应用笔记
评估板
设计指南
可靠性报告
软件/ 模型
价格与供货
样品
在线订购
封装信息
无铅信息
类似功能器件
类似应用器件
评估板
类似型号器件
配合该器件使用的产品
参考文献： 19- 3692 Rev. 1; 2011- 05- 16
本页最后一次更新: 2011- 05- 16
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© 2011 Maxim Integrated Products版权所有
http://china.maxim-ic.com/datasheet/index.mvp/id/4759[2011-05-19 10:30:02]
19-3692; Rev 1; 5/11
Ultra-Low-Voltage Level Translators
The MAX13000E–MAX13005E 6-channel level translators provide the level shifting necessary to allow data
transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of
the device. Logic signals present on the VL side of the
device appear as higher voltage logic signals on the
VCC side of the device, and vice-versa.
The MAX13000E–MAX13005E feature a low VCC and VL
quiescent supply current less than 4µA. The
MAX13000E–MAX13005E also have ±15kV ESD protection on the I/O VCC side for greater protection in applications that route signals externally. The ESD protection is
specified using the Human Body Model (HBM). The
MAX13000E/MAX13001E/MAX13002E operate at a guaranteed 230kbps data rate. The MAX13003E/
MAX13004E/MAX13005E operate at a guaranteed
20Mbps data rate when VCC > +1.65V.
The MAX13000E/MAX13003E are bidirectional level
translators, allowing data translation in either direction
(VL ↔ VCC) on any single data line without a DIRECTION
input. The MAX13001E/MAX13002E/MAX13004E/
MAX13005E unidirectional level translators level shift
data in one direction (VL → VCC or VCC → VL) on any
single data line. The MAX13001E/MAX13002E/
MAX13004E/MAX13005E unidirectional translators’
inputs have the capability to interface with both CMOS
and open-drain (OD) outputs. For more information see
the Ordering Information, Selector Guide, and the InputDriver Requirements sections.
The MAX13000E–MAX13005E operate with +0.9V to
+3.6V VL voltages and +1.5V to +3.6V VCC voltages. The
MAX13000E–MAX13005E are available in 16-bump
UCSP™ and 16-pin TSSOP packages, and are specified
over the extended -40°C to +85°C operating temperature range.
Features
♦ Guaranteed Data-Rate Options
230kbps (MAX13000E/MAX13001E/MAX13002E)
20Mbps (MAX13003E/MAX13004E/MAX13005E)
♦ Bidirectional Level Translation Without a
DIRECTION Input
♦
♦
♦
♦
Operational Down to +0.9V on VL and +1.5V on VCC
±15kV ESD Protection on I/O VCC Lines per HBM
Low <4µA Quiescent Current
Enable/Shutdown Control
♦ 2mm x 2mm, 16-Bump UCSP and Lead Packaging
Options
♦ CMOS or Open-Drain Outputs Interface Capability
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
Ordering Information
PART
MAX13000EEUE+
SPI™ and MICROWIRE® Level Translation
Smart-Card Readers
Portable POS Systems
Portable Communication Devices
Low-Cost Serial Interfaces
Telecommunications Equipment
PINPACKAGE
-40°C to +85°C
16 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information continued at end of data sheet.
Pin Configurations
BOTTOM VIEW
MAX13000E/MAX13003E
I/OVCC3
VCC
GND
I/OVCC4
I/OVCC1
I/OVCC2
I/OVCC5
I/OVCC6
I/OVL1
I/OVL2
I/OVL5
I/OVL6
I/OVL3
VL
EN
I/OVL4
1
2
3
4
D
Applications
CMOS Logic-Level Translation
Open-Drain I/O Translation
OD-to-CMOS Signal Conversion
Low-Voltage ASIC Level Translation
Cell Phones
TEMP RANGE
C
B
A
4 X 4 UCSP
Pin Configurations continued at end of data sheet.
Typical Operating Circuits and Selector Guide appear at end
of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX13000E–MAX13005E
General Description
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to GND.
VCC ...........................................................................-0.3V to +4V
VL ..............................................................................-0.3V to +4V
I/OVCC_ .......................................................-0.3V to (VCC + 0.3V)
I/OVL_ ............................................................-0.3V to (VL + 0.3V)
EN .................................................................-0.3V to (VL + 0.3V)
Short-Circuit Duration I/OVL_, I/OVCC_ to GND ..........Continuous
Continuous Power Dissipation (TA = +70°C)
16-Pin TSSOP (derate 9.4mW/°C at +70°C) ................755mW
16-Bump UCSP (derate 8.2mW/°C at +70°C) .............659mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
VL Supply Range
VCC Supply Range
Supply Current from VCC
(Note 3)
SYMBOL
VL
VCC
IQVCC
MAX
UNITS
VL ≤ VCC (Note 2)
CONDITIONS
0.9
VCC
V
(Note 2)
1.5
3.6
V
4
TA = +85°C
40
IQVL
TA = +85°C
VCC Shutdown Supply Current
(Note 3)
ISHDN-VCC
TYP
TA = +25°C
TA = +25°C
Supply Current from VL (Note 3)
MIN
(Note 3)
1
VL < VCC - 0.2V
(Note 3)
5
2
4
VL < VCC - 0.2V
40
2
EN = GND, TA = +85°C
20
VL < VCC - 0.2V,
EN = GND
EN = GND
VL Shutdown Supply Current
(Note 3)
TA = +85°C
1
4
VL < VCC - 0.2V,
EN = GND
20
EN = GND
40
I/O VL_, I/O VCC_,
EN = GND
TA = +25°C
0.35
TA = +85°C
1
I/O Tri-Stated Output Leakage
Current
VL < VCC - 0.2V, I/O
VL_, I/O VCC_,
EN = GND
TA = +25°C
0.2
TA = +85°C
0.5
2
µA
2
I/O Tri-State Output Leakage
Current
EN Input Leakage Current
µA
20
EN = GND, TA = +25°C
TA = +25°C
µA
µA
µA
µA
TA = +25°C
0.35
TA = +85°C
1
_______________________________________________________________________________________
µA
Ultra-Low-Voltage Level Translators
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2/3 × VL
V
LOGIC-LEVEL THRESHOLDS
I/OVL_ Input-Voltage-High
Threshold
VIHL
I/OVL_ Input-Voltage-Low
Threshold
VILL
I/OVCC_ Input-Voltage-High
Threshold
VIHC
I/OVCC_ Input-Voltage-Low
Threshold
VILC
EN Input-Voltage-High Threshold
VIHEN
EN Input-Voltage-Low Threshold
VILEN
I/OVL_ Output-Voltage High
VOHL
I/OVL_ Output-Voltage Low
I/OVCC_ Output-Voltage High
I/OVCC_ Output-Voltage Low
VOLL
VOHC
VOLC
1/3 × VL
V
2/3 ×
VCC
1/3 ×
VCC
V
2/3 × VL
I/OVL_ source current = 20µA
V
1/3 × VL
V
VL 0.25
V
MAX13002E/MAX13005E,
OVL_ sink current = 1µA
0.3
MAX13000E/MAX13001E/MAX13003E/
MAX13004E, I/OVL_ sink current = 20µA
0.25
I/OVCC_ source current = 20µA
V
V
VCC 0.25
V
MAX13001E/MAX13004E,
OVCC_ sink current = 1µA
0.3
MAX13000E/MAX13002E/MAX13003E/
MAX13005E, I/OVCC_ sink current = 20µA
0.25
V
OUTPUT CURRENTS
Output Sink Current During
Transient (VCC Side)
Output Sink Current During
Transient (VL Side)
VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
25
mA
VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
VL = +1.2V, VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
30
VL = +1.2V, VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
mA
_______________________________________________________________________________________
3
MAX13000E–MAX13005E
ELECTRICAL CHARACTERISTICS (continued)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
SYMBOL
Output Source Current During
Transient (VCC Side)
CONDITIONS
MIN
TYP
VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
22
VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
VL = +1.2V, VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E
25
MAX
UNITS
mA
Output Source Current During
Transient (VL Side)
mA
VL = +1.2V, VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E
1
ESD PROTECTION
I/OVCC_
Human Body Model
±15
Air-Gap Discharge (IEC61000-4-2)
±10
Contact Discharge (IEC61000-4-2)
±8
kV
TIMING CHARACTERISTICS
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
I/OVCC_ Rise Time
SYMBOL
tRVCC
CONDITIONS
tFVCC
MAX
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 1a, 1b
15
400
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 1a, 1b
15
400
_______________________________________________________________________________________
UNITS
ns
1400
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 1a, 1b
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
4
TYP
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 1a, 1b
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
I/OVCC_ Fall Time
MIN
1400
ns
Ultra-Low-Voltage Level Translators
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
I/OVL_ Rise Time
SYMBOL
tRVL
CONDITIONS
tFVL
MAX
15
CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15
300
15
CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 1a, 1b
300
I/OVCC-VL
Propagation Delay from
I/OVL to I/OVCC_ after EN
(Note 5)
ns
ns
1200
20
ns
I/OVL-VCC
Propagation Delay
(Driving I/OVCC_)
UNITS
1200
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
Propagation Delay
(Driving I/OVL_)
TYP
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
I/OVL_ Fall Time
MIN
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
1000
VCC > +1.65V, CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20
VCC = 1.5V, CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
1000
CI/OVCC = 50pF, CMOS output, Figure 3
2
CI/OVCC = 50pF, OD output, Figure 3
6
ns
µs
tEN-VCC
_______________________________________________________________________________________
5
MAX13000E–MAX13005E
TIMING CHARACTERISTICS (continued)
TIMING CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4)
PARAMETER
SYMBOL
Propagation Delay from
I/OVCC to I/OVL after EN
(Note 5)
CONDITIONS
MIN
TYP
MAX
CI/OVL = 50pF, CMOS output, Figure 4
2
CI/OVL = 50pF, OD output, Figure 4
6
tSKEW
Part-to-Part Skew (Note 6)
UNITS
µs
tEN-VL
Channel-to-Channel Skew
Each translator equally loaded,
MAX13003E/MAX13004E/MAX13005E
±5
Each translator equally loaded,
MAX13000E/MAX13001E/MAX13002E
±250
CI/OVL = 15pF, CI/OVCC = 15pF,
VL = +1.8V, VCC = +2V, ΔT = +5°C,
MAX13003E/MAX13004E/MAX13005E
10
ns
tPPSKEW
Maximum Data Rate
ns
MAX13003E/MAX13004E/MAX13005E
VCC > +1.65V, CI/OVL = 50pF,
CI/OVCC = 50pF
20
Mbps
MAX13000E/MAX13001E/MAX13002E
CI/OVL = 50pF, CI/OVCC = 50pF
230
kbps
Note 1: All devices are 100% production tested at TA = +25°C. Limits are guaranteed by design over the entire temperature range.
Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 3: This consumption is referred to as no signal transmission.
Note 4: Guaranteed by design with an input signal full swing, rise/fall time ≤ 3ns, source resistance is 50Ω.
Note 5: Enable input signal full swing and rise/fall time ≤ 50ns.
Note 6: Guaranteed by design, not production tested.
Typical Operating Characteristics
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
10
DATA RATE = 230kbps
1
0.1
0.1
0.01
DATA RATE = 230kbps
1.8
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
3.3
3.6
DATA RATE = 20Mbps
1
0.1
DATA RATE = 230kbps
0.01
0.001
1.5
6
DATA RATE = 20Mbps
10
VCC SUPPLY CURRENT (mA)
100
MAX13000Etoc02
DATA RATE = 20Mbps
1
VL SUPPLY CURRENT (mA)
MAX13000Etoc01
1000
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VL = 0.9V)
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VCC, VL = 0.9V)
MAX13000Etoc03
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VL = 0.9V)
VL SUPPLY CURRENT (μA)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
1.5
1.8
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
3.3
3.6
1.5
1.8
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3.3
3.6
Ultra-Low-Voltage Level Translators
VL SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
0.1
DATA RATE = 230kbps
0.01
MAX13000E toc05
310
DATA RATE = 20Mbps
1.8
2.1
2.4
2.7
3.0
3.3
DATA RATE = 20Mbps
4.00
3.95
3.85
-40
3.6
4.05
3.90
290
1.5
-15
10
35
60
85
-40
-15
10
35
85
60
TEMPERATURE (°C)
TEMPERATURE (°C)
VL SUPPLY CURRENT vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
VCC SUPPLY CURRENT vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
RISE/FALL TIME vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
60
40
20
DATA RATE = 230kbps
7
6
5
4
3
8
7
DATA RATE = 230kbps
30
40
50
60
70
80
20
30
40
50
60
70
80
RISE/FALL TIME vs.
CAPACITIVE LOAD ON I/O VL
(DRIVING I/OVCC, = 3.3V, VL = +0.9V)
PROPAGATION DELAY vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC, = 3.3V, VL = +0.9V)
tF
5
4
3
tR
2
9.0
8.5
PROPAGATION DELAY (ns)
MAX31000Etoc10
6
8.0
7.5
7.0
6.5
6.0
1
5.5
0
5.0
10
20
30
40
50
60
70
CAPACITIVE LOAD (pF)
80
90 100
10
20
30
40
50
60
70
80
90 100
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
7
tF
3
90 100
CAPACITIVE LOAD (pF)
8
4
0
10
90 100
PROPAGATION DELAY vs.
CAPACITIVE LOAD ON I/O VL
(DRIVING I/OVCC, VCC = 3.3V, VL = +0.9V)
6.5
6.0
PROPAGATION DELAY (ns)
20
5
1
0
10
tR
6
2
2
1
0
MAX31000Etoc09
9
MAX31000Etoc08
DATA RATE = 20Mbps
MAX13000Etoc12
80
8
RISE/FALL TIME (ns)
DATA RATE = 20Mbps
100
9
VCC SUPPLY CURRENT (mA)
120
MAX31000Etoc07
SUPPLY VOLTAGE (V)
140
VL SUPPLY CURRENT (μA)
320
300
0.001
RISE/FALL TIME (ns)
330
4.10
MAX13000E toc06
1.0
MAX31000Etoc11
VCC SUPPLY CURRENT (mA)
DATA RATE = 20Mbps
340
VCC SUPPLY CURRENT (μA)
MAX13000Etoc04
10
VCC SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
VCC SUPPLY CURRENT (mA)
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/OVCC, VL = +0.9V)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
10
20
30
40
50
60
70
CAPACITIVE LOAD (pF)
80
90 100
10
20
30
40
50
60
70
80
90 100
CAPACITIVE LOAD (pF)
_______________________________________________________________________________________
7
MAX13000E–MAX13005E
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
OD RAIL-TO-RAIL DRIVING (MAX13002E)
(DRIVING I/OVL, VCC = +3.3V,
VL = +0.9V, CI/OVCC = 56pF,
DATA RATE = 230kbps, RPULLUP = 15kΩ)
I/OVL_
500mV/div
GND
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 230kbps)
MAX31000Etoc15
MAX31000Etoc14
I/OVL_
500mV/div
GND
I/OVCC
2V/div
GND
I/OVCC
2V/div
GND
I/OVCC
2V/div
GND
1μs/div
2μs/div
200ns/div
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 20Mbps)
I/OVL_
500mV/div
GND
I/OVCC
2V/div
GND
VCC + VL SUPPLY CURRENT vs. FREQUENCY
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V)
I/OVL_
500mV/div
GND
I/OVCC
2V/div
GND
40ns/div
VCC + VL SUPPLY CURRENT (mA)
MAX31000Etoc17
MAX31000Etoc16
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 4Mbps)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I/OVL IS DRIVEN WITH A
0.9V SQUARE WAVE
VCC + VL
VCC
VL
100
10ns/div
4250
8400 12,550 16,700 20,850 25,000
FREQUENCY (kHz)
VOHL vs. IOHL FOR VL SIDE
(VCC = 3.3V)
VL = +2.5V
2.5
0.25
0.20
VL = +2.5V
VOHL (V)
VCC
VL
VL = +1.8V
1.5
8400 12,550 16,700 20,850 25,000
FREQUENCY (kHz)
VL = +1.8V
0.15
VL = +0.9V
0.10
1.0
VL = +0.9V
0.05
0.5
0
4250
VOLL (V)
VCC + VL
2.0
MAX13000Etoc21
I/OVCC IS DRIVEN WITH A
3.3V SQUARE WAVE
100
8
3.0
MAX31000Etoc19
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VOLL vs. IOLL FOR VL SIDE
(VCC = 3.3V)
MAX13000Etoc20
VCC + VL SUPPLY CURRENT vs. FREQUENCY
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
0
0
5
10 15 20 25 30 35 40 45 50
IOHL (μA)
I/OVL_
500mV/div
GND
MAX31000Etoc18
MAX31000Etoc13
OD RAIL-TO-RAIL DRIVING (MAX13005E)
(DRIVING I/OVL, VCC = +3.3V,
VL = +0.9V, CI/OVCC = 56pF,
DATA RATE = 230Mbps, RPULLUP = 1kΩ)
VCC + VL SUPPLY CURRENT (mA)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
0
5
10 15 20 25 30 35 40 45 50
IOLL (μA)
_______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
VOLC (V)
0.20
VCC = +3.3V
VCC = +1.8V
0.10
VCC = +3.3V
3.0
VOHC (V)
VCC = +2.5V
0.15
3.5
MAX13000Etoc22
0.25
MAX13000Etoc23
VOHC vs.
IOHC FOR VCC SIDE
VOLC vs.
IOLC FOR VCC SIDE
VCC = +2.5V
2.5
2.0
VCC = +1.8V
1.5
0.05
1.0
0
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
IOHC (μA)
IOLC (μA)
Pin Descriptions
MAX13000E/MAX13003E
PIN
NAME
FUNCTION
TSSOP
1
UCSP
B1
I/OVL1
CMOS Input/Output 1, Referenced to VL
2
B2
I/OVL2
CMOS Input/Output 2, Referenced to VL
3
A1
I/OVL3
CMOS Input/Output 3, Referenced to VL
4
A2
VL
Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF
capacitor.
5
A3
EN
Enable Input. When EN is pulled low, I/O VCC1 to I/O VCC6 and I/O VL1 to I/O
VL6 are tri-stated. Drive EN high (VL) for normal operation.
6
A4
I/OVL4
CMOS Input/Output 4, Referenced to VL
7
B3
I/OVL5
CMOS Input/Output 5, Referenced to VL
8
B4
I/OVL6
9
C4
I/OVCC6
CMOS Input/Output 6, Referenced to VCC
10
C3
I/OVCC5
CMOS Input/Output 5, Referenced to VCC
11
D4
I/OVCC4
CMOS Input/Output 4, Referenced to VCC
12
D3
GND
Ground
13
D2
VCC
VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC.
14
D1
I/OVCC3
CMOS Input/Output 3, Referenced to VCC
15
C2
I/OVCC2
CMOS Input/Output 2, Referenced to VCC
16
C1
I/OVCC1
CMOS Input/Output 1, Referenced to VCC
CMOS Input/Output 6, Referenced to VL
_______________________________________________________________________________________
9
MAX13000E–MAX13005E
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
Pin Descriptions (continued)
MAX13001E/MAX13004E
PIN
10
NAME
FUNCTION
TSSOP
1
UCSP
B1
OVL1
CMOS Output 1, Referenced to VL
2
B2
OVL2
CMOS Output 2, Referenced to VL
3
A1
OVL3
CMOS Output 3, Referenced to VL
4
A2
VL
Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF
capacitor.
5
A3
EN
Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are
tri-stated. Drive EN high (VL) for normal operation.
6
A4
OVL4
CMOS Output 4, Referenced to VL
7
B3
OVL5
CMOS Output 5, Referenced to VL
8
B4
OVL6
CMOS Output 6, Referenced to VL
9
C4
IVCC6
Open-Drain-Compatible Input 6, Reference to VCC
10
C3
IVCC5
Open-Drain-Compatible Input 5, Referenced to VCC
11
D4
IVCC4
Open-Drain-Compatible Input 4, Referenced to VCC
12
D3
GND
Ground
13
D2
VCC
VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC.
14
D1
IVCC3
Open-Drain-Compatible Input 3, Referenced to VCC
15
C2
IVCC2
Open-Drain-Compatible Input 2, Referenced to VCC
16
C1
IVCC1
Open-Drain-Compatible Input 1, Referenced to VCC
______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
MAX13002E/MAX13005E
PIN
NAME
FUNCTION
TSSOP
1
UCSP
B1
IVL1
Open-Drain-Compatible Input 1, Referenced to VL
2
B2
IVL2
Open-Drain-Compatible Input 2, Referenced to VL
3
A1
IVL3
Open-Drain-Compatible Input 3, Referenced to VL
4
A2
VL
Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF
capacitor.
5
A3
EN
Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are
tri-stated. Drive EN high (VL) for normal operation.
6
A4
IVL4
Open-Drain-Compatible Input 4, Referenced to VL
7
B3
IVL5
Open-Drain-Compatible Input 5, Referenced to VL
8
B4
IVL6
Open-Drain-Compatible Input 6, Referenced to VL
9
C4
OVCC6
CMOS Output 6, Referenced to VCC
10
C3
OVCC5
CMOS Output 5, Referenced to VCC
11
D4
OVCC4
CMOS Output 4, Referenced to VCC
12
D3
GND
Ground
13
D2
VCC
VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC.
14
D1
OVCC3
CMOS Output 3, Referenced to VCC
15
C2
OVCC2
CMOS Output 2, Referenced to VCC
16
C1
OVCC1
CMOS Output 1, Referenced to VCC
______________________________________________________________________________________
11
MAX13000E–MAX13005E
Pin Descriptions (continued)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
Test Circuits/Timing Diagrams
I/OVL_
90%
VL
VCC
50%
MAX13000E
10%
EN
tRISE/FALL
I/OVL-VCC
I/OVCC
I/OVL_
SOURCE
I/OVCC_
90%
RS
CI/OVCC
50%
10%
tFVCC
tRVCC
I/OVL-VCC
UNUSED I/Os ARE GROUNDED.
tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E)
tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E)
Figure 1b. Timing for Driving I/OVL
Figure 1a. Driving I/OVL
tRISE/FALL
VL
VCC
I/OVCC_
MAX13000E
90%
50%
EN
10%
I/OVCC-VL
I/OVL_
I/OVCC
I/OVL_
I/OVCC-VL
90%
50%
CI/OVL
RS
SOURCE
10%
tFVL
tRVL
tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E)
UNUSED I/Os ARE GROUNDED.
Figure 2a. Driving I/OVCC
12
tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E)
Figure 2b. Timing for Driving I/OVCC
______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
VL
EN
EN
SOURCE
MAX13000E
t'EN-VCC
0
VL
I/OVCC
I/OVL_
I/OVL_
0
CI/OVCC
VL
VCC
VCC / 2
I/OVCC_
0
VL
t"EN-VCC
EN
SOURCE
MAX13000E
0
EN
I/OVL_
VL
I/OVCC_
0
VCC
I/OVCC
I/OVL_
CI/OVCC
VCC / 2
0
tEN-VCC IS WHICH EVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
Figure 3. Propagation Delay from I/OVL to I/OVCC After EN
VL
EN
VL
EN
SOURCE
MAX13000E
t'EN-VL
VCC
I/OVCC_
I/OVCC
I/OVL_
0
0
VL
CI/OVL
VCC
I/OVL_
VL / 2
0
VL
EN
VL
EN
SOURCE
t"EN-VL
MAX13000E
VCC
I/OVCC_
I/OVL_
0
VL
I/OVCC
CI/OVL
0
I/OVL_
VL / 2
0
tEN-VL IS WHICH EVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL.
Figure 4. Propagation Delay from I/OVCC to I/OVL After EN
______________________________________________________________________________________
13
MAX13000E–MAX13005E
Test Circuits/Timing Diagrams (continued)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
Detailed Description
The MAX13000E–MAX13005E logic-level translators
provide the level shifting necessary to allow data transfer in multivoltage systems. Externally applied voltages,
VCC and VL, set the logic levels on each side of the
device. Logic signals present on the VL side of the
device appear as higher voltage logic signals on the
VCC side of the device, and vice-versa.
The MAX13000E/MAX13003E are bidirectional level
translators allowing data translation in either direction
(VL ↔ VCC) on any single data line without the use of a
DIRECTION input. The MAX13001E/MAX13002E/
MAX13004E/MAX13005E unidirectional level translators
level shift data in one direction (VL → VCC or VCC →
V L ) on any single data line. The MAX13001E/
MAX13002E/MAX13004E/MAX13005E unidirectional
translators’ inputs have the capability to interface with
both CMOS and open-drain (OD) outputs. For more
information, see the Ordering Information section and
the Input Driver Requirements section.
The MAX13000E–MAX13005E accept VL from +0.9V to
+3.6V. All devices have VCC ranging from +1.5V to
+3.6V, making them ideal for data transfer between
low-voltage ASICs/PLDs and higher voltage systems.
The MAX13000E–MAX13005E feature low VCC quiescent supply current of less than 4µA, and VL quiescent
supply current of less than 2µA when in shutdown. The
MAX13000E–MAX13005E have ±15kV ESD protection
on the VCC side for greater protection in applications
that route signals externally. The ESD protection is
specified using the Human Body Model (HBM).The
MAX13000E/MAX13001E/MAX13002E operate at a
guaranteed 230kbps data rate. The MAX13003E/
MAX13004E/MAX13005E operate at a guaranteed
20Mbps data rate when VCC > +1.65V.
Level Translation
For normal operation, ensure that +1.5V ≤ VCC ≤ +3.6V,
and +0.9V ≤ VL ≤ VCC. During power-up sequencing,
VL ≥ VCC does not damage the device whenever VL is
within the absolute maximum ratings (see the Absolute
Maximum Ratings section). During power-supply
sequencing, when VCC is floating and VL is powered
up, 1mA of current can be sourced to each load on the
VL side, yet the device does not latch up.
The MAX13000E–MAX13005E are designed to have
VCC ≥ VL at all times; however, if VCC is turned off, the
part will not be damaged and will not latch up. To prevent excessive leakage currents in either the I/O or
supply lines, the I/O on the VL side must be left in the
high state.
14
The maximum data rate for the MAX13000E–
MAX13005E depends heavily on the load capacitance
(see the Typical Operating Characteristics), output
impedance of the driver, and the operational voltage
range (see the Timing Characteristics table).
Open-Drain Operation
The MAX13001E/MAX13002E/MAX13004E/MAX13005E
have input stages specifically designed to accommodate external open-drain drivers. When using opendrain drivers, the MAX13001E/MAX13002E/
MAX13004E/MAX13005E operate in a unidirectionalonly mode, translating from the OD side to the CMOS
side. For improved performance, the rise- and fall-time
accelerators are present on both the CMOS and the
OD side. See the Input-Driver Requirement section. Do
not use pullup resistors greater than 15kΩ for proper
operation, and smaller pullup resistance may be needed for higher speed operation.
Input-Driver Requirements
The MAX13000E–MAX13005E feature four different
architectures based on the speed of the part, as well as
on whether the translator is a CMOS-to-CMOS translator, or whether it is an OD-to-CMOS translator.
20Mbps CMOS-to-CMOS Bidirectional Translator
(MAX13003E)
The MAX13003E architecture is based on a one-shot
accelerator output stage (Figure 5). Accelerator output
stages are always in tri-state, except when there is a
transition on any of the translators on the input side,
either I/OVL or I/OVCC. A short pulse is generated during which the one-shot output stage becomes active
and charges/discharges the capacitances at the I/Os.
Due to its bidirectional nature, the accelerator stages on
both the I/OVCC and the I/OVL become active during an
I/O transition from low to high or high to low. This can
lead to some current feeding into the external source
that is driving the translator. However, this behavior
helps speed up the transition on the driven side.
The type of devices that drive the inputs of the
MAX13003E is usually specified with an output drivecurrent capability (IOUT). When driving the inputs of the
MAX13003E, the maximum achievable speed is constrained by the drive current of the external driver. To
insure the maximum possible throughput of 20Mbps, the
external driver should meet the following requirement:
IOUT ≥ 1.67 × 108 × V × (CIN + CP)
______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
MAX13000E–MAX13005E
VL
VCC
P
ONE-SHOT
5kΩ
I/OVL
I/OVCC
INVERTER 2
INVERTER 1
N
ONE-SHOT
P
ONE-SHOT
5kΩ
INVERTER 3
INVERTER 4
N
ONE-SHOT
Figure 5. Architecture of 20Mbps, CMOS-to-CMOS Bidirectional Translators
where, CP is the parasitic capacitance of the traces, V
is the supply voltage of the driven side (i.e., VL or VCC),
and CIN is the input capacitance of the driven side
(CIN = 10pF for VL side, CIN = 20pF for VCC side).
20Mbps OD-to-CMOS Unidirectional Translators
(MAX13004E/MAX13005E)
The MAX13004E/MAX13005E architecture is virtually the
same as that for the bidirectional CMOS-to-CMOS translators, the only difference being that the output inverter
(inverter 4) at the driving side accommodates the driving
capabilities of an open-drain output (Figure 6).
For proper operation, a pullup resistor needs to be connected from the open-drain output to the power supply of
the driving side. Use pullup resistors no larger than 15kΩ.
230kbps CMOS-to-CMOS Bidirectional Translator
(MAX13000E)
The architecture of the MAX13000E lacks the one-shot
accelerator output stages since the transitions that this
device handles are limited by its data rate, 230kbps
(Figure 7).
For proper operation, the driver must meet the following
conditions: 1kΩ maximum output impedance and 1mA
minimum output current.
230kbps OD-to-CMOS Unidirectional Translators
(MAX13001E/MAX13002E)
The architecture of the MAX13001E/MAX13002E is similar to that of the 230kbps CMOS-to-CMOS part, with the
difference that it accommodates the driving capability of
an open-drain output on the driving side, and also that it
has only a single one-shot output stage (Figure 8).
For proper operation, a pullup resistor needs to be connected from the open-drain output to the power supply of
the driving side. Use pullup resistors no larger than 15kΩ.
Figure 9 shows a graph of the typical input current versus input voltage for all of the above configurations.
Enable Output Mode (EN)
The MAX13000E–MAX13005E feature an enable (EN)
input. Drive EN low to set the MAX13000E–MAX13005E
I/Os in tri-state mode. Drive EN high (VL) for normal
operation.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electrostatic discharges encountered during handling and
assembly. The I/OV CC lines have extra protection
against static discharge. Maxim’s engineers have
developed state-of-the-art structures to protect these
pins against ESD of ±15kV without damage. The ESD
______________________________________________________________________________________
15
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
20Mbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR
VCC/VL
VL/VCC
P
ONE-SHOT
5kΩ
IVCC/IVL
OVL/OVCC
INVERTER 2
OPEN-DRAIN
COMPATIBLE INPUT
INVERTER 1
CMOSCOMPATIBLE INPUT
N
ONE-SHOT
P
ONE-SHOT
INVERTER 3
5kΩ
75kΩ
INVERTER
4
N
ONE-SHOT
Figure 6. Architecture of 20Mbps, OD-to-CMOS Unidirectional Translators
230kbps Bidirectional CMOS-TO-CMOS Level Translator
VL
VCC
5kΩ
I/OVL
I/OVCC
INVERTER 1
INVERTER 2
5kΩ
INVERTER 4
INVERTER 3
Figure 7. Architecture of 230kbps, CMOS-to-CMOS Bidirectional Translator
16
______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
MAX13000E–MAX13005E
230kbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR
VCC/VL
VL/VCC
5kΩ
IVCC/IVL
OVL/OVCC
INVERTER 1
OPEN-DRAIN
COMPATIBLE INPUT
INVERTER 2
CMOSCOMPATIBLE INPUT
INVERTER 3
5kΩ
75kΩ
INVERTER
4
5kΩ
N
ONE-SHOT
Figure 8. Architecture of 230kbps, OD-to-CMOS Unidirectional Translator
structures withstand high ESD in all states: normal
operation, tri-state output mode, and power-down. After
an ESD event, Maxim’s E-versions keep working without latchup, whereas competing products can latch
and must be powered-down to remove latchup.
ESD protection can be tested in various ways. The
I/OVCC lines of the MAX13000E–MAX13005E are characterized for protection to ±15kV using the Human
Body Model.
IIN
VTH_IN / RIN1
ESD Test Conditions
0
VTH_IN
VIN
VS
WHERE, VS = VCC OR VL
(VS - VTH_IN) /
RIN2
RIN1 = RIN2 = 5kΩ FOR CMOS-TO-CMOS TRANSLATORS
RIN1 = 75kΩ FOR OD-TO-CMOS TRANSLATORS
Figure 9. Typical IIN vs. VIN
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 10 shows the Human Body Model and Figure 11
shows the current waveform it generates when discharged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device
through a 1.5kΩ resistor.
______________________________________________________________________________________
17
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
RC 1MΩ
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
CS
100pF
RC
50Ω TO 100Ω
RD 1500Ω
DISCHARGE
RESISTANCE
CHARGE-CURRENTLIMIT RESISTOR
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
HIGHVOLTAGE
DC
SOURCE
Cs
150pF
RD
330Ω
DISCHARGE
RESISTANCE
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
Figure 10. Human Body ESD Test Model
Figure 12. IEC 61000-4-2 Contact Discharge Test Model
IP 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
UCSP Package Considerations
AMPERES
For general UCSP package information and PC layout
considerations, please refer to Maxim application note:
Wafer-Level Chip-Scale Package.
36.8%
10%
0
0
tRL
UCSP Reliability
TIME
tDL
CURRENT WAVEFORM
Figure 11. Human Body Current Waveform
IEC 61000-4-2 Standard ESD Protection
The IEC 61000-4-2 standard (Figure 12) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330Ω resistor. The
MAX13000E–MAX13005E’s I/O on the V CC side are
rated for IEC 61000-4-2 standard, (8kV Contact
Discharge and ±10kV Air-Gap Discharge).
The IEC 61000-4-2 model discharges higher peak current and more energy than the HBM due to the lower
series resistance and larger capacitor.
Applications Information
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be considered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s website at www.maxim-ic.com.
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incorrect data, bypass VL and VCC to ground with a 0.1µF
capacitor. To ensure full ±15kV ESD protection, bypass
VCC to ground with a 1µF capacitor. Place all capacitors as close to the power-supply inputs as possible.
18
______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
VL
VCC
EN
MAX13000E–MAX13005E
I/OVL1
I/OVCC1
I/OVL2
I/OVCC2
I/OVL3
I/OVCC3
I/OVL4
I/OVCC4
I/OVL5
I/OVCC5
I/OVL6
I/OVCC6
GND
______________________________________________________________________________________
19
MAX13000E–MAX13005E
Functional Diagram
Ultra-Low-Voltage Level Translators
MAX13000E–MAX13005E
Typical Operating Circuits
+0.9V
+2.8V
0.1μF
1μF
VCC
VL
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
MAX13001E
DATA1
DATA2
EN
MAX13004E
OVL_1
IVCC_1
OVL_2
IVCC_2
DATA3
OVL_3
IVCC_3
DATA3
DATA4
OVL_4
IVCC_4
DATA4
DATA5
OVL_5
IVCC_5
DATA5
DATA6
OVL_6
IVCC_6
DATA6
DATA1
DATA2
GND
+0.9V
+2.8V
0.1μF
1μF
VCC
VL
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
MAX13002E
DATA1
DATA2
EN
MAX13005E
IVL_1
OVCC_1
IVL_2
OVCC_2
DATA3
IVL_3
OVCC_3
DATA3
DATA4
IVL_4
OVCC_4
DATA4
DATA5
IVL_5
OVCC_5
DATA5
DATA6
IVL_6
OVCC_6
DATA6
DATA1
DATA2
GND
20
______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
+0.9V
+2.8V
0.1μF
1μF
VL
+0.9V
SYSTEM
CONTROLLER
VCC
+2.8V
SYSTEM
MAX13000E
DATA1
EN
MAX13003E
I/OVL_1
I/OVCC_1
DATA1
DATA2
I/OVL_2
I/OVCC_2
DATA2
DATA3
I/OVL_3
I/OVCC_3
DATA3
DATA4
I/OVL_4
I/OVCC_4
DATA4
DATA5
I/OVL_5
I/OVCC_5
DATA5
DATA6
I/OVL_6
I/OVCC_6
DATA6
GND
Selector Guide
PART
DATA
RATE
(bps)
NUMBER OF
BIDIRECTIONAL
TRANSLATORS
NUMBER OF
VL → VCC
TRANSLATORS
NUMBER OF
VCC → VL
TRANSLATORS
TRANSLATOR
CONFIGURATION
MAX13000E
230k
6
—
—
CMOS-to-CMOS
MAX13001E
230k
—
—
6
OD-to-CMOS
MAX13002E
230k
—
6
—
OD-to-CMOS
MAX13003E
20M
6
—
—
CMOS-to-CMOS
MAX13004E
20M
—
—
6
OD-to-CMOS
MAX13005E
20M
—
6
—
OD-to-CMOS
______________________________________________________________________________________
21
MAX13000E–MAX13005E
Typical Operating Circuits (continued)
Ultra-Low-Voltage Level Translators
MAX13000E–MAX13005E
Pin Configurations (continued)
BOTTOM VIEW
MAX13001E/MAX13004E
IVCC3
VCC
GND
MAX13002E/MAX13005E
IVCC4
D
OVCC3
VCC
GND
OVCC4
OVCC1
OVCC2
OVCC5
OVCC6
IVL1
IVL2
IVL5
IVL6
IVL3
VL
EN
IVL4
2
3
4
D
IVCC1
IVCC2
IVCC5
IVCC6
C
C
OVL1
OVL2
OVL5
OVL6
B
B
OVL3
VL
EN
OVL4
A
A
1
2
3
4
1
4 X 4 UCSP
4 X 4 UCSP
TOP VIEW
I/OVL1 1
16 I/OVCC1
OVL1 1
16 IVCC1
IVL1 1
16 OVCC1
I/OVL2 2
15 I/OVCC2
OVL2 2
15 IVCC2
IVL2 2
15 OVCC2
I/OVL3 3
14 I/OVCC3
OVL3 3
14 IVCC3
IVL3 3
14 OVCC3
VL 4
EN 5
13 VCC
MAX13000E
MAX13003E
EN 5
13 VCC
MAX13001E
MAX13004E
VL 4
12 GND
EN 5
13 VCC
MAX13002E
MAX13005E
12 GND
I/OVL4 6
11 I/OVCC4
OVL4 6
11 IVCC4
IVL4 6
11 OVCC4
I/OVL5 7
10 I/OVCC5
OVL5 7
10 IVCC5
IVL5 7
10 OVCC5
I/OVL6 8
9
I/OVCC6
OVL6 8
9
IVCC6
IVL6 8
9
TSSOP
22
12 GND
VL 4
TSSOP
TSSOP
______________________________________________________________________________________
OVCC6
Ultra-Low-Voltage Level Translators
PART
TEMP RANGE
PINPACKAGE
MAX13000EEBE+T*
-40°C to +85°C
16 UCSP
(4mm × 4mm)
MAX13001EEUE+
-40°C to +85°C
16 TSSOP
MAX13001EEBE+T*
-40°C to +85°C
16 UCSP
(4mm × 4mm)
MAX13002EEUE+
-40°C to +85°C
16 TSSOP
MAX13002EEBE+T*
-40°C to +85°C
16 UCSP
(4mm × 4mm)
MAX13003EEUE+
-40°C to +85°C
16 TSSOP
MAX13003EEBE+T*
-40°C to +85°C
16 UCSP
(4mm × 4mm)
MAX13004EEUE+
-40°C to +85°C
16 TSSOP
MAX13004EEBE+T*
-40°C to +85°C
16 UCSP
(4mm × 4mm)
MAX13005EEUE+
-40°C to +85°C
16 TSSOP
Chip Information
PROCESS: BiCMOS
16 UCSP
(4mm × 4mm)
*Future Product—contact factory for availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T =Tape and reel.
MAX13005EEBE+T*
-40°C to +85°C
______________________________________________________________________________________
23
MAX13000E–MAX13005E
Ordering Information (continued)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
24
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
16 TSSOP
U16+2
21-0066
90-0117
16 UCSP
B16+1
21-0101
Refer to Application Note 1891
______________________________________________________________________________________
Ultra-Low-Voltage Level Translators
REVISION
NUMBER
REVISION
DATE
0
6/05
Initial release
1
5/11
Added lead-free information to the Ordering Information
DESCRIPTION
PAGES
CHANGED
—
1, 23
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX13000E–MAX13005E
Revision History