Click to see this datasheet in Simplified Chinese! FSA2467 0.4Ω Low-Voltage Dual DPDT Analog Switch Features Description Typical 0.4Ω On Resistance (RON) for +2.7V supply 0.25Ω Maximum RON Flatness for +2.7V Supply The FSA2467 is a dual Double-Pole, Double-Throw (DPDT) analog switch. The FSA2467 operates from a single 1.65V to 4.3V supply. The FSA2467 features an ultra-low on resistance of 0.4Ω at a +2.7V supply and 25°C. This device is fabricated with sub-micron CMOS technology to achieve fast switching speeds and is designed for break-before-make operation. Features Less then12µA ICCT Current when Sn Input is Lower than VCC 3x3mm 16-Lead Pb-Free MLP Package 1.8x2.6mm 16-Lead Pb-Free UMLP Package Broad VCC Operating Range Low THD (0.02% Typical for 32Ω Load) FSA2467 features very low quiescent current even when the control voltage is lower than the VCC supply. This feature allows mobile handset applications direct interface with baseband processor general-purpose I/Os. Applications Cell Phone PDA Portable Media Player Ordering Information Part Number Package Description FSA2467MPX 16-lead Molded Leadless Package (MLP), JEDEC MO-220, 3x3mm Square FSA2467UMX 16-lead Ultrathin Molded Leadless Package (UMLP), 1.8x2.6mm All packages are lead free per JEDEC: J-STD-020B standard. Application Diagram Figure 1. Application Diagram © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch April 2008 Figure 2. Pin Assignments Truth Table Pin Descriptions Control Inputs Function Name Function LOW nB0 Connected to nA nA，nB0，nB1 Data Ports HIGH nB1 Connected to nA nS Control Input FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Pin Assignments Analog Symbol Figure 3. Analog Symbol © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 4.6 V VS Switch Voltage -0.5 VCC+0.3 V VIN Input Voltage -0.5 4.6 IIK Input Diode Current -50 ISW Switch Current 350 mA Peak Switch Current (Pulsed at 1ms duration, <10% Duty Cycle) 500 mA +150 ºC ISWPEAK TSTG Storage Temperature Range -65 V mA TJ Junction Temperature +150 ºC TL Lead Temperature, Soldering 10 Seconds +260 ºC 5.5 kV ESD Human Body Model Recommended Operating Conditions FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Absolute Maximum Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VCC Supply Voltage 1.65 4.30 V VIN Control Input Voltage(1) 0 VCC V VIN Switch Input Voltage 0 VCC V TA Operating Temperature -40 +85 ºC Note： 1. Unused inputs must be held HIGH or LOW. They may not float. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 3 Typical values are at 25ºC unless otherwise specified. TA = -40 to +85ºC TA = +25ºC Symbol Parameter Conditions VCC (V) Min. VIH VIL IIN INO(OFF) INC(OFF) IA(ON) RON ΔRON RFLAT(ON) Input Voltage High Input Voltage Low Control Input Leakage VIN=0V to VCC nB0 or nB1=0.3V, VCC-0.3V or floating Min 4.3 1.4 2.7 to 3.6 1.3 2.3 to 2.7 1.1 1.65 to 1.95 0.9 Max. V 4.3 0.7 2.7 to 3.6 0.5 2.3 to 2.7 0.4 1.65 to 1.95 0.4 1.65 to 4.30 V -0.5 0.5 μA 1.95 to 4.30 -10.0 10.0 -50.0 50.0 nA 1.95 to 4.30 -10.0 10.0 -50.0 50.0 nA nA=0.3V,VCC0.3V On Leakage Current of Port A nB0 or nB1=0.3V, VCC-0.3V or floating (2) On Resistance Matching (3) Between Channels On Resistance Flatness Max. nA=0.3V, VCC-0.3V Off Leakage Current of Port nB0 and nB1 Switch On Resistance Typ. Units (4) ICC Quiescent Supply Current ICCT Increase in ICC Current per Control Voltage IOUT=100mA 4.3 0.4 0.6 nB0 or nB1=0V,0.8V, 1.8V,2.7V 2.7 0.4 0.6 IOUT=100mA, nB0 or 1=0V,0.7V, 1.2V, 2.3V 2.3 0.55 0.95 IOUT=100mA, nB0 or nB1=1.0V 1.8 0.8 2.0 IOUT=100mA, nB0 or nB1=0.8V 2.7 0.04 0.10 IOUT=100mA, nB0 or nB1=0.7V 2.3 0.03 0.10 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch DC Electrical Characteristics Ω Ω IOUT=100mA, B0 or nB1=0V to VCC 2.7 0.25 2.3 0.3 VIN=0V to VCC IOUT=0V 4.3 VIN=1.8V 4.3 7.0 12.0 15.0 VIN=2.6V 4.3 3.0 6.0 7.0 -100 100 -500 500 Ω nA μA Notes: 2. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch. 3. ∆ RON=RON max – RON min measured at identical Vcc, temperature and voltage. 4. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 4 Typical values are at 25ºC unless otherwise specified. Symbol Parameter Conditions Min. tON tOFF tBBM Q OIRR Xtalk BW THD Turn-On Time Turn-Off Time Break-BeforeMake Time Charge Injection Off Isolation Crosstalk -3dB Bandwidth Total Harmonic Distortion TA = -40 to +85ºC TA = +25ºC VCC Typ. Max. Min. 3.6 to 4.3 50 60 RL=50Ω, CL=35pF 2.7 to 3.6 65 75 2.3 to 2.7 80 90 nB0 or nB1=1.5V 3.6 to 4.3 32 40 RL=50Ω, CL=35pF 2.7 to 3.6 42 50 2.3 to 2.7 52 60 3.6 to 4.3 12 RL=50Ω, CL=35pF 2.7 to 3.6 15 2.3 to 2.7 20 CL=100pF, VGEN=0V, RGEN=0Ω 3.6 to 4.3 15 CL=100pF, VGEN=0V, RGEN=0Ω 2.7 to 3.6 10 CL=100pF, VGEN=0V, RGEN=0Ω 2.3 to 2.7 8 3.6 to 4.3 -75 2.7 to 3.6 -75 2.3 to 2.7 -75 3.6 to 4.3 -75 2.7 to 3.6 -75 2.3 to 2.7 -75 RL=50Ω 2.3 to 4.3 85 RL=32Ω, VIN=2VPP, f=20 to 20kHZ 3.6 to 4.3 0.02 RL=32Ω, VIN=2VPP, f=20 to 20kHZ 2.7 to 3.6 0.02 RL=32Ω, VIN=2VPP, f=20 to 20kHZ 2.3. to 2.7 0.02 f=100KHz, RL=50Ω,CL=5pF f=100KHz, RL=50Ω, CL=5pF Figure ns Figure 7 ns Figure 7 ns Figure 8 pC Figure 10 dB Figure 9 dB Figure 9 MHZ Figure 12 % Figure 13 Max. nB0 or nB1=1.5V nB0 or nB1=1.5V Units FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch AC Electrical Characteristics Capacitance Symbol Parameter Conditions VCC TA = +25ºC Typical Units Figure Control Pin Input Capacitance f=1MHZ 0 1.5 pF Figure 7 COFF B Port Off Capacitance f=1MHZ 3.3 32 pF Figure 7 CON A Port On Capacitance f=1MHZ 3.3 118 pF Figure 7 CIN © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 5 Figure 4. RON at 2.7V VCC FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Typical Applications Figure 5. RON at 2.3V VCC Figure 6. RON at 1.8V VCC © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 6 Figure 7. Turn-On / Turn-Off Timing FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch AC Loadings and Waveforms Figure 8. Break-Before-Make Timing Figure 9. Off Isolation and Crosstalk © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 7 Figure 10. Figure 11. Charge Injection On / Off Capacitance Measurement Setup Figure 12. Figure 13. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch AC Loadings and Waveforms (Continued) Bandwidth Harmonic Distortion www.fairchildsemi.com 8 Tape Format for MLP Tape Section Number Cavities Cavity Status Leader (Start End) 125 (typical) Empty Sealed Carrier 2500/3000 Filled Sealed Trailer (Hub End) 75 (typical) Empty Sealed Package Designator MPX Tape Size (12mm) Cover Tape Status A B C D N W1 W2 13.000 0.059 0.512 0.795 7.008 0.488 0.724 (330.00) (1.50) (13.00) (20.20) (178.00) (12.40) (18.40) © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Tape and Reel Specifications www.fairchildsemi.com 9 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Package Dimensions Figure 14. 16-Lead, Molded Leadless Package (MLP), JEDEC MO-220 3x3mm Square Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 10 0.10 C 2.100 A 1.80 2X B 15X 0.563 0.663 1 PIN #1 IDENT 2.900 2.60 0.400 0.10 C 2X 16X 0.225 TOP VIEW 0.55 MAX. RECOMMENDED LAND PATTERN 0.10 C 0.08 C 0.152 SEATING PLANE 0.050 C SIDE VIEW TERMINAL SHAPE VARIANTS 0.40 0.60 5 0.15 0.25 9 0.100 0.100 15X PIN 1 0.40 0.30 15X 0.50 0.15 0.25 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Package Dimensions NON-PIN 1 Supplier 1 1 16 0.30 0.50 0.15 0.25 13 ALL TERMINALS 0.15 PIN 1 0.10 C A B 0.05 C 0.30 15X 0.50 15X 0.25 NON-PIN 1 Supplier 2 BOTTOM VIEW A. THIS PACKAGE IS NOT CURRENTLY REGISTERED WITH ANY STANDARDS COMMITTEE B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. TERMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL SHAPE VARIANTS E. LAND PATTERN IS A MINIMAL TOE DESIGN F. DRAWING FILE NAME : UMLP16AREV3 Figure 15. 16-Lead, Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 11 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 12