FSA2268L10X

FSA2268 / FSA2268T Low-Voltage Dual-SPDT
(0.4) Analog Switch with 16kV ESD
Features
Description




0.4Ω Typical On Resistance (RON) for +3.0V Supply
The FSA2268 is a high-performance, dual Single Pole
Double Throw (SPDT) analog switch that features ultralow RON of 0.4 (typical) at 3.0V VCC. The FSA2268
operates over a wide VCC range of 1.65V to 4.3V and is
designed for break-before-make operation. The select
input is TTL-level compatible.




Packaged in Pb-free 10-Lead µMLP (1.4 x 1.8mm)

0.25Ω Maximum RON Flatness for +3.0V Supply
-3db Bandwidth: > 50MHz
Low ICCT Current Over an Expanded Control Input
Range
Power-Off Protection on Common Ports
Broad VCC Operating Range: 1.65 to 4.3V
HBM JEDEC: JESD22-A114
- I/O to GND: 13.5kV
- Power to GND: 16.0kV
Noise Immunity Termination Resistors in FSA2268T
Applications


Cell Phone, PDA, Digital Camera, and Notebook
The FSA2268 features very low quiescent current even
when the control voltage is lower than the V CC supply.
This feature suits mobile handset applications by
allowing direct interface with baseband processor
general-purpose I/Os with minimal battery consumption.
The FSA2268T includes termination resistors that
improve noise immunity during overshoot excursions,
off-isolation coupling, or “pop-minimization.”
IMPORTANT NOTE:
For
additional
information,
[email protected].
please
contact
LCD Monitor, TV, and Set-Top Box
Ordering Information
Part Number
Top Mark
Package Description
FSA2268UMX
GF
10-Lead, Quad Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8mm,
0.4mm Pitch
FSA2268TUMX
GH
10-Lead, Quad Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8mm,
0.4mm Pitch
FSA2268L10X
GH
10-Lead, MicroPak™, 1.6mm Wide
Analog Symbols
Figure 1.
FSA2268
© 2007 Fairchild Semiconductor Corporation
FSA2268 / 2268T • Rev. 1.1.0
Figure 2.
FSA2268T (with Noise Termination Resistors)
www.fairchildsemi.com
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
March 2013
Vcc
10
2B0 1B1
2B1
GND
2A
3
2
1
6
1
9
1A
1B1
2
8
S1
2B0
3
7
S2
2B1
4
6
2A
10 1B0
4
5
1B0
7
9
VCC
8
1A
S2 S1
5
GND
Figure 3. Pin Assignment 10-Pin UMLP
(Top-Through View)
Figure 4.
10-Lead MicroPak™
Pin Descriptions
Pin # UMLP
Pin # MicroPak™
Name
Description
1
2
1B1
Data Ports
2
3
2B0
Data Ports
3
4
2B1
Data Ports
4
5
GND
Ground
5
6
2A
Data Ports
6
7
S2
Switch Select Pins
7
8
S1
Switch Select Pins
8
9
1A
Data Ports
9
10
VCC
Supply Voltage
10
1
1B0
Data Ports
Truth Table
Control Input, Sn
Function
LOW Logic Level
nB0 connected to nA (FSA2268/2268T); nB1 terminated to GND (FSA2268T only)
HIGH Logic Level
nB1 connected to nA (FSA2268/2268T); nB0 terminated to GND (FSA2268T only)
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
2
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter
VCC
Min.
Supply Voltage
1B0, 1B1, 2B0, 2B1, 1A, 2A Pins
(1)
Max.
Units
-0.5
5.5
V
-0.5
VCC + 0.3
0
1.4
VSW
Switch I/O Voltage
VIN
Control Input Voltage
5.5
V
IIK
Input Clamp Diode Current
-50
mA
ISW
Switch I/O Current (Continuous)
350
mA
Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle)
500
mA
ISWPEAK
TSTG
T Version nBn Pin Off
(1)
S1, S2
-0.5
+150
°C
TJ
Maximum Junction Temperature
+150
°C
TL
Lead Temperature (Soldering, 10 seconds)
+260
°C
1
Level
MSL
ESD
Storage Temperature Range
-65
V
Moisture Sensitivity Level (JEDEC J-STD-020A)
Human Body Model,
JEDEC: JESD22-A114
I/O to GND
13.5
Power to GND
16.0
All Other Pins
9.0
Charged Device Model, JEDEC: JESD22-C101
kV
2.0
kV
Note:
1. Input and output negative ratings may be exceeded if input and output diode current ratings are observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Units
VCC
Supply Voltage
1.65
4.30
V
VIN
Control Input Voltage
0
VCC
V
VSW
Switch I/O Voltage
0
VCC
V
-40
+85
°C
TA
Operating Temperature
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
3
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
Absolute Maximum Ratings
All typical values are at 25ºC unless otherwise specified.
Symbol
Parameter
Conditions
Min.
VIH
TA=-40 to
+85ºC
TA=+25ºC
VCC (V)
Typ.
Max.
3.6 to 4.3
2.7 to 3.6
2.3 to 2.7
1.65 to 1.95
Input Voltage High
Min.
Unit
Max.
1.7
1.5
1.4
0.9
V
3.6 to 4.3
0.7
V
2.7 to 3.6
2.3 to 2.7
1.65 to 1.95
0.5
0.4
0.4
V
-0.5
0.5
µA
VIL
Input Voltage Low
IIN
Control Input Leakage
(S1,S2)
VIN=0 to VCC
1.65 to 4.30
INO(0FF),
INC(OFF)
FSA2268
Off Leakage Current of
Port nB0 and nB1
nA=0.3V, VCC–0.3V
nB0 or nB1=VCC-0.3V,
0.3V, or Floating
Figure 6
1.95 to 4.30
-10
10
-50
50
nA
nA=0.3V, nB0 or
nB1=0V or Floating
Figure 6
1.95 to 4.30
-10
10
-50
50
µA
IA(ON)
On Leakage Current of
Port nA
nA=0.3V, VCC–0.3V
nB0 or nB1=VCC-0.3V,
0.3V, or Floating
Figure 7
1.95 to 4.30
-20
20
-100
100
nA
IOFF
FSA2268
Power-Off Leakage
Current (Common Port
Only 1A, 2A)
Common Port (1A, 2A),
VIN=0V to 4.3V, VCC=0V
nB0, nB1=Floating
0V
±1
µA
Power-Off Leakage
IOFF
Current (Common Port
FSA2268T
Only 1A, 2A)
Common Port (1A, 2A),
VIN=0V to 4.3V, VCC=0V
nB0, nB1=0V or
Floating
0V
±40
µA
Off Leakage Current of
INC(OFF)
Port nB0 and nB1 (with
FSA2268T
Termination Resistors)
RON
∆RON
ION=100mA, nB0 or
nB1=0.7V, 3.6V
Figure 5
4.30
0.30
0.50
ION=100mA, nB0 or
nB1=0.7V, 2.3V
Figure 5
3.00
0.40
0.55
Ω
Switch On Resistance(2)(5) ION=100mA, nB0 or
nB1=0V, 0.7V, 1.6V,
2.3V
Figure 5
2.30
0.52
ION=100mA, nB0 or
nB1=0V, 0.7V, 1.65V
Figure 5
1.65
1.00
ION=100mA, nB0 or
nB1=0.7V
4.30
3.00
2.30
1.65
0.04
0.06
0.12
1.00
On Resistance Matching
Between Channels(3)(5)
0.13
0.13
Ω
Continued on following page…
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
4
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
DC Electrical Characteristics
All typical values are at 25ºC unless otherwise specified.
TA=-40 to
+85ºC
TA=+25ºC
Symbol
Parameter
Conditions
VCC (V)
Min.
(4)(5)
RFLAT(ON)
On Resistance Flatness
RTERM
Internal Termination
Resistors(6)
ICC
Quiescent Supply Current
ICCT
Increase in ICC per Input
4.30
3.00
2.30
1.65
IOUT=100mA, nB0 or
nB1=0V to VCC
Typ.
Max.
Min.
Max.
0.25
0.25
0.5
0.6
4.30
Input at 2.6V
4.30
Input at 1.8V
-100
Ω
Ω
200
VIN=0 or VCC, IOUT=0
Unit
100
-500
500
3
7
7
15
nA
µA
Notes:
2. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch.
3. ∆RON=RON max – RON min measured at identical VCC, temperature, and voltage.
4. Flatness is defined as the difference between the maximum and minimum value of on resistance (RON) over the
specified range of conditions.
5. Guaranteed by characterization, not production tested, for VCC=1.65-3.00V.
6. Guaranteed by characterization, not production tested.
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
5
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
DC Electrical Characteristics (Continued)
All typical value are for VCC=3.3V at 25ºC unless otherwise specified.
Symbol Parameter
Conditions
TA=-40 to
+85°C
TA=+25ºC
VCC (V)
Min. Typ. Max. Min.
tON
tOFF
tBBM
Turn-On
Time
Turn-Off
Time
nB0 or
nB1=1.5V,
RL=50Ω,
CL=35pF
nB0 or
nB1=1.5V,
RL=50Ω,
CL=35pF
nB0 or
BreaknB1=1.5V,
Before-Make
RL=50Ω,
Time
CL=35pF
3.6 to 4.3
2.7 to 3.6
2.3 to 2.7
1.65 to 1.95
3.6 to 4.3
2.7 to 3.6
2.3 to 2.7
1.65 to 1.95
3.6 to 4.3
2.7 to 3.6
2.3 to 2.7
1.65 to 1.95
Unit
Max.
55
60
65
15
15
15
60
65
70
30
35
40
5
5
5
35
40
45
ns
70
40
15
15
15
16
Figure
2
2
2
2
Figure 8
Figure 9
ns
ns
Figure 10
Charge
Injection
CL=1.0nF,
VS=0V, RS=0Ω
1.65 to 4.30
25
pC
Figure 14
OIRR
Off Isolation
f=100kHz,
1.65 to 4.30
RL=50Ω, CL=0pF
-70
dB
Figure 12
Xtalk
Crosstalk
f=100kHz,
1.65 to 4.30
RL=50Ω, CL=0pF
-70
dB
Figure 13
BW
-3db
Bandwidth
RL=50Ω, CL=0pF 1.65 to 4.30
>50
MHz
Figure 11
THD
Total
Harmonic
Distortion
f=20Hz to 20kHz,
1.65 to 4.30
RL=32,
VIN=2Vpp
.06
%
Figure 17
Q
Capacitance
Symbol
Parameter
Conditions
VCC (V)
TA=+25ºC
Min. Typ.
Unit
Figure
Max.
CIN
Control Pin Input
Capacitance
f=1MHz
0
1.5
pF
Figure 15
COFF
B Port Off Capacitance
f=1MHz
3.3
30
pF
Figure 15
CON
A Port On Capacitance
f=1MHz
3.3
120
pF
Figure 16
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
6
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
AC Electrical Characteristics
VON
I A(OFF)
NC
A
nBn
nA
V IN
V IN
Select
I ON
GND
Select
V Sel =
R ON = VON / ION
Figure 5.
GND
VSel =
GND
0 or Vcc
**Each switch port is tested separately.
On Resistance
Figure 6.
Off Leakage (Ports tested separately)
nBn
I A(ON)
NC
0 orVcc
nA
V IN
A
GND
RS
V IN
CL
RL
V OUT
GND
Select
GND
VSel =
Figure 7.
V Sel
0 or Vcc
GND
On Leakage
Figure 8.
tRISE = 2.5ns
Test Circuit Load
tFALL = 2.5ns
VCC
90%
Input - VSel
10%
GND
90%
VCC /2
VCC /2
10%
VOH
90%
90%
Output - VOUT
VOL
Figure 9.
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
tON
tOFF
Turn-On / Turn-Off Waveforms
www.fairchildsemi.com
7
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
Test Diagrams
tRISE = 2.5ns
nB n
nA
Vcc
V IN
GND
V OUT
CL
V IN
90%
V cc/2
Input - VSel
RL
10%
0V
GND
GND
V OUT
RS
0.9*V out
0.9*V out
V Sel
GND
tD
RL and CL are functions of the application
environment (50, 75, or 100 ).
CL includes test fixture and stray capacitance.
Figure 10.
Break-Before-Make Interval Timing
Network Analyzer
RS
V IN
VS
GND
GND
VSel
GND
VOU T
GND
RT
R L and CL are functions of the application
environment (50, 75, or 100 ).
L
C L includes
test fixture and stray capacitance.
Figure 11.
GND
Bandwidth
Network Analyzer
RS
VSel
VS
GND
RT
GND
GND
VOUT
GND
GND
RS and RT are functions of the application
environment (50, 75, or 100 ).
RT
GND
Off-Isolation
= 20 Log (VOUT / VIN )
Figure 12.
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
Channel Off Isolation
www.fairchildsemi.com
8
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
Test Diagrams (Continued)
Network Analyzer
RS
VIN
VS
GND
GND
VSel
GND
GND
RT
V OUT
RT
GND
GND
RS and RT are functions of the application
CROSSTALK = 20 Log (VOUT / VIN )
environment (50, 75, or 100 ).
Figure 13.
Adjacent Channel Crosstalk
Figure 14.
Charge Injection Test
nSn
Capacitance
Meter
VSel =
f = 1MHz
Figure 15.
nBn
Capacitance
Meter
nBn
0 or Vcc
nSn
V Sel =
f = 1MHz
0 orV cc
nBn
nBn
Channel Off Capacitance
Figure 16.
Channel On Capacitance
Audio Analyzer
RS
V IN
VS
GND
GND
V CNTRL
GND
VSel =
GND
0 or Vcc
V OUT
RT
GND
RS and RT are functions of the application
environment (see AC Tables for specific values).
Figure 17.
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
Total Harmonic Distortion
www.fairchildsemi.com
9
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
Test Diagrams (Continued)
1.40
0.15 C
A
1.70
B
2X
(9X)
0.563
0.663
1
2.10
1.80
PIN#1 IDENT
0.40
0.15 C
TOP VIEW
0.10 C
0.55 MAX.
(10X) 0.225
2X
RECOMMENDED
LAND PATTERN
0.152
1.45
0.08 C
0.55
SEATING C
PLANE
0.05
SIDE VIEW
9X
0.45
0.40
1.85
0.35
(9X)
0.45
3
(10X) 0.225
6
DETAIL A
OPTIONAL MINIMIAL
TOE LAND PATTERN
0.40
1
NOTES:
PIN#1 IDENT
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP10Arev3.
0.15
(10X)
0.25
10
BOTTOM VIEW
0.55
0.45
0.10 C A B
0.05 C
0.10
0.10
0.10
DETAIL A
SCALE : 2X
PACKAGE
EDGE
LEAD
OPTION 1
SCALE : 2X
Figure 18.
LEAD
OPTION 2
SCALE : 2X
10-Lead Quad Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/products/analog/pdf/UMLP10_TNR.pdf.
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
10
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
Physical Dimensions
0.10 C
2.10
2X
A
1.62
B
KEEPOUT ZONE, NO TRACES
OR VIAS ALLOWED
(0.11)
0.56
1.12
1.60
PIN1 IDENT IS
2X LONGER THAN
OTHER LINES
0.10 C
2X
TOP VIEW
(0.35) 10X
(0.25) 10X
0.50
RECOMMENDED LAND PATTERN
0.55 MAX
0.05 C
0.05 C
0.05
0.00
(0.20)
C
0.35
0.25
SIDE VIEW
(0.15)
D
0.65
0.55
DETAIL A
0.35
0.25
(0.36)
0.35
0.25
DETAIL A 2X SCALE
4
1
0.56
5
10
(0.29)
0.35 9X
0.25
6
9
0.50
0.25 9X
0.15
1.62
0.10
0.05
C A B
C
ALL FEATURES
BOTTOM VIEW
Figure 19.
NOTES:
A. PACKAGE CONFORMS TO JEDEC
REGISTRATION MO-255, VARIATION UABD .
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. PRESENCE OF CENTER PAD IS PACKAGE
SUPPLIER DEPENDENT. IF PRESENT IT
IS NOT INTENDED TO BE SOLDERED AND
HAS A BLACK OXIDE FINISH.
E. DRAWING FILENAME: MKT-MAC10Arev5.
10-Lead, MicroPak™, 1.6mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
11
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
Physical Dimensions (Continued)
FSA2268 / FSA2268T — Low-Voltage Dual-SPDT (0.4) Analog Switch with 16kV ESD
© 2007 Fairchild Semiconductor Corporation
FSA2268 / FSA2268T • Rev. 1.1.0
www.fairchildsemi.com
12