TOSHIBA TMP86PS27FG

8 Bit Microcontroller
TLCS-870/C Series
TMP86PS27FG
TMP86PS27FG
The information contained herein is subject to change without notice. 021023 _ D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
The Toshiba products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B
The products described in this document shall not be used or embedded to any downstream products
of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of TOSHIBA or others. 021023_C
The products described in this document may include products subject to the foreign exchange and
foreign trade laws. 021023_F
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2006 TOSHIBA CORPORATION
All Rights Reserved
Page 2
Revision History
Date
Revision
2006/9/7
1
First Release
2006/12/19
2
Contents Revised
Table of Contents
TMP86PS27FG
1.1
1.2
1.3
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
4
5
2. Operational Description
2.1
CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
2.1.2
2.1.3
Memory Address Map............................................................................................................................... 9
Program Memory (OTP) ........................................................................................................................... 9
Data Memory (RAM) ................................................................................................................................. 9
2.2.1
2.2.2
Clock Generator...................................................................................................................................... 10
Timing Generator .................................................................................................................................... 12
2.2
System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2.1
2.2.2.2
Configuration of timing generator
Machine cycle
2.2.3.1
2.2.3.2
2.2.3.3
Single-clock mode
Dual-clock mode
STOP mode
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
STOP mode
IDLE1/2 mode and SLEEP1/2 mode
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
SLOW mode
2.2.3
2.2.4
2.3
Operation Mode Control Circuit .............................................................................................................. 13
Operating Mode Control ......................................................................................................................... 18
Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.1
2.3.2
2.3.3
2.3.4
External Reset Input ............................................................................................................................... 31
Address trap reset .................................................................................................................................. 32
Watchdog timer reset.............................................................................................................................. 32
System clock reset.................................................................................................................................. 32
3. Interrupt Control Circuit
3.1
3.2
Interrupt latches (IL19 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.1
3.2.2
Interrupt master enable flag (IMF) .......................................................................................................... 36
Individual interrupt enable flags (EF19 to EF4) ...................................................................................... 37
3.3.1
3.3.2
Interrupt acceptance processing is packaged as follows........................................................................ 39
Saving/restoring general-purpose registers ............................................................................................ 40
Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.2.1
3.3.2.2
Using PUSH and POP instructions
Using data transfer instructions
3.3.3
Interrupt return ........................................................................................................................................ 41
3.4.1
3.4.2
Address error detection .......................................................................................................................... 42
Debugging .............................................................................................................................................. 42
3.4
Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
i
3.5
3.6
3.7
Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4. Special Function Register (SFR)
4.1
4.2
SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5. I/O Ports
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P4 (P43 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
53
55
56
58
60
62
65
6. Time Base Timer (TBT)
6.1
Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.1
6.1.2
6.1.3
Configuration .......................................................................................................................................... 67
Control .................................................................................................................................................... 67
Function .................................................................................................................................................. 68
6.2.1
6.2.2
Configuration .......................................................................................................................................... 69
Control .................................................................................................................................................... 69
6.2
Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7. Watchdog Timer (WDT)
7.1
7.2
Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Malfunction Detection Methods Using the Watchdog Timer ...................................................................
Watchdog Timer Enable .........................................................................................................................
Watchdog Timer Disable ........................................................................................................................
Watchdog Timer Interrupt (INTWDT)......................................................................................................
Watchdog Timer Reset ...........................................................................................................................
72
73
74
74
75
7.3.1
7.3.2
7.3.3
7.3.4
Selection of Address Trap in Internal RAM (ATAS) ................................................................................
Selection of Operation at Address Trap (ATOUT) ..................................................................................
Address Trap Interrupt (INTATRAP).......................................................................................................
Address Trap Reset ................................................................................................................................
76
76
76
77
7.3
Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8. 10-Bit Timer/Counter (TC7)
8.1
8.2
ii
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.3
8.4
Configuring Control and Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.4.1
Programmable pulse generator output (PPG output) ............................................................................. 84
8.4.1.1
8.4.1.2
8.4.1.3
50% duty mode
Variable duty mode
PPG1/PPG2 independent mode
8.4.2.1
8.4.2.2
8.4.2.3
8.4.2.4
8.4.2.5
Command start and capture mode
Command start and trigger start mode
Trigger start mode
Trigger capture mode (CSTC = 00)
Trigger start/stop acceptance mode
8.4.3.1
8.4.3.2
8.4.3.3
Counting stopped with the outputs initialized
Counting stopped with the outputs maintained
Counting stopped with the outputs initialized at the end of the period
8.4.4.1
8.4.4.2
One-time output mode
Continuous output mode
8.4.5.1
8.4.5.2
8.4.5.3
Specifying initial values and output logic for PPG outputs
Enabling or disabling PPG outputs
Using the TC7 as a normal timer/counter
8.4.7.1
8.4.7.2
8.4.7.3
INTTC7T (Trigger start interrupt)
INTTC7P (Period interrupt)
INTEMG (Emergency output stop interrupt)
8.4.8.1
8.4.8.2
8.4.8.3
8.4.8.4
8.4.8.5
8.4.8.6
Enabling/disabling input on the EMG pin
Monitoring the emergency PPG output stop state
EMG interrupt
Canceling the emergency PPG output stop state
Restarting the timer after canceling the emergency PPG output stop state
Response time between EMG pin input and PPG outputs being initialized
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
Starting a count....................................................................................................................................... 88
Configuring how the timer stops ............................................................................................................. 95
One-time/continuous output mode.......................................................................................................... 95
PPG output control (Initial value/output logic, enabling/disabling output) ............................................... 97
Eliminating noise from the TC7 pin input ................................................................................................ 97
Interrupts................................................................................................................................................. 99
Emergency PPG output stop feature .................................................................................................... 100
TC7 operation and microcontroller operating mode ............................................................................. 102
9. 8-Bit TimerCounter (TC3, TC4)
9.1
9.2
9.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
8-Bit Timer Mode (TC3 and 4) ..............................................................................................................
8-Bit Event Counter Mode (TC3, 4) ......................................................................................................
8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)...................................................................
8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)................................................................
16-Bit Timer Mode (TC3 and 4) ............................................................................................................
16-Bit Event Counter Mode (TC3 and 4) ..............................................................................................
16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)........................................................
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) .............................................
Warm-Up Counter Mode.......................................................................................................................
9.3.9.1
9.3.9.2
109
110
110
113
115
116
116
119
121
Low-Frequency Warm-up Counter Mode
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
High-Frequency Warm-Up Counter Mode
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
10. Real-Time Clock
10.1
10.2
10.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Control of the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
iii
11. Asynchronous Serial interface (UART )
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8.1
11.8.2
Data Transmit Operation .................................................................................................................... 130
Data Receive Operation ..................................................................................................................... 130
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
11.9.6
Parity Error..........................................................................................................................................
Framing Error......................................................................................................................................
Overrun Error ......................................................................................................................................
Receive Data Buffer Full.....................................................................................................................
Transmit Data Buffer Empty ...............................................................................................................
Transmit End Flag ..............................................................................................................................
11.9
125
126
128
129
129
130
130
130
Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
131
131
131
132
132
133
12. Synchronous Serial Interface (SIO)
12.1
12.2
12.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.3.1
Internal clock
External clock
12.3.2.1
12.3.2.2
Leading edge
Trailing edge
12.3.2
12.4
12.5
12.6
Clock source ....................................................................................................................................... 138
12.3.1.1
12.3.1.2
Shift edge............................................................................................................................................ 139
Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.6.1
12.6.2
12.6.3
4-bit and 8-bit transfer modes ............................................................................................................. 140
4-bit and 8-bit receive modes ............................................................................................................. 142
8-bit transfer / receive mode ............................................................................................................... 143
13. 10-bit AD Converter (ADC)
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
Software Start Mode ........................................................................................................................... 151
Repeat Mode ...................................................................................................................................... 151
Register Setting ................................................................................................................................ 152
13.6.1
13.6.2
13.6.3
13.6.4
Restrictions for AD Conversion interrupt (INTADC) usage .................................................................
Analog input pin voltage range ...........................................................................................................
Analog input shared pins ....................................................................................................................
Noise Countermeasure .......................................................................................................................
13.4
13.5
13.6
iv
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 154
Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
155
155
155
155
14. Key-on Wakeup (KWU)
14.1
14.2
14.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15. LCD Driver
15.1
15.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.2.1
15.2.2
15.2.3
15.3
LCD driving methods .......................................................................................................................... 161
Frame frequency................................................................................................................................. 162
Driving method for LCD driver ............................................................................................................ 163
15.2.3.1
15.2.3.2
When using the booster circuit (LCDCR<BRES>="1")
When using an external resistor divider (LCDCR<BRES>="0")
LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.3.1
15.3.2
Display data setting ............................................................................................................................ 165
Blanking .............................................................................................................................................. 166
15.4.1
15.4.2
15.4.3
Initial setting ........................................................................................................................................ 167
Store of display data ........................................................................................................................... 167
Example of LCD drive output .............................................................................................................. 170
15.4
Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
16. OTP operation
16.1
Operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
16.1.1
MCU mode.......................................................................................................................................... 175
16.1.1.1
16.1.1.2
16.1.1.3
Program Memory
Data Memory
Input/Output Circuiry
16.1.2.1
16.1.2.2
Programming Flowchart (High-speed program writing)
Program Writing using a General-purpose PROM Programmer
16.1.2
PROM mode ....................................................................................................................................... 177
17. Input/Output Circuitry
17.1
17.2
Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
18. Electrical Characteristics
18.1
18.2
18.3
18.4
18.5
18.6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics, AC Characteristics (PROM mode). . . . . . . . . . . . . . . . . . .
18.6.1
18.6.2
18.7
18.8
185
186
187
188
189
190
Read operation in PROM mode.......................................................................................................... 190
Program operation (High-speed) ........................................................................................................ 191
Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
v
19. Package Dimensions
This is a technical document that describes the operating functions and electrical
specifications of the 8-bit microcontroller series TLCS-870/C (LSI).
vi
TMP86PS27FG
CMOS 8-Bit Microcontroller
TMP86PS27FG
The TMP86PS27FG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440
bytes of One-Time PROM. It is pin-compatible with the TMP86CM27FG/CP27AFG (Mask ROM version). The
TMP86PS27FG can realize operations equivalent to those of the TMP86CM27FG/CP27AFG by programming the
on-chip PROM.
Product No.
ROM
(EPROM)
RAM
Package
MaskROM MCU
Emulation Chip
TMP86PS27FG
61440
bytes
1024
bytes
P-QFP80-1420-0.80B
TMP86CM27FG/
CP27AFG
TMP86C927XB
1.1 Features
1. 8-bit single chip microcomputer TLCS-870/C series
- Instruction execution time :
0.25 µs (at 16 MHz)
122 µs (at 32.768 kHz)
- 132 types & 731 basic instructions
2. 20interrupt sources (External : 7 Internal : 13)
3. Input / Output ports (55 pins)
Large current output: 8pins (Typ. 20mA), LED direct drive
4. Prescaler
- Time base timer
- Divider output function
5. Watchdog Timer
6. 10-bit timer counter: 1ch (2 output pins)
2ports output PPG (Programmed Pulse Generator)
50%duty output mode
Variable Duty output mode
External-triggered start and stop
060116EBP
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C
• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions. 030619_S
Page 1
1.1 Features
TMP86PS27FG
Emargency stop pin
7. 8-bit timer counter : 2 ch
- Timer, Event counter, Programmable divider output (PDO),
Pulse width modulation (PWM) output,
Programmable pulse generation (PPG) modes
8. 8-bit UART : 1 ch
9. 8-bit SIO: 1 ch
10. 10-bit successive approximation type AD converter
- Analog input: 8 ch
11. Key-on wakeup : 4 ch
12. LCD driver/controller
Built-in voltage booster for LCD driver With display memory
LCD direct drive capability (MAX 40 seg × 4 com)
1/4,1/3,1/2duties or static drive are programmably selectable
13. Clock operation
Single clock mode
Dual clock mode
14. Low power consumption operation
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
stop.)
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
oscillate.)
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interruputs(CPU restarts).
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts).
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts).
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock.
interruput.
15. Wide operation voltage:
4.5 V to 5.5 V at 16MHz /32.768 kHz
2.7 V to 5.5 V at 8 MHz /32.768 kHz
Page 2
Release by
RESET
(INT5/STOP) P20
AVDD
VAREF
(STOP5/AIN0) P60
(AIN1) P61
(AIN2) P62
(INT0/AIN3) P63
(STOP2/AIN4) P64
(STOP3/AIN5) P65
(STOP4/AIN6) P66
(AIN7) P67
(RXD0/SEG39) P00
(TXD0/SEG38) P01
(INT1/SEG37) P02
(INT2/SEG36) P03
(INT3/SEG35) P04
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C1
V1
V2
V3
(SI1) P40
(SO1) P41
(SCK1) P42
(TXD1) P43
(DVO) P30
(TC3/PDO3/PWM3) P31
(TC4/PDO4/PWM4/PPG4) P32
(EMG) P33
(TC7) P34
(PPG1) P35
(PPG2) P36
(RXD1) P37
VSS
XIN
XOUT
TEST
VDD
(XTIN) P21
(XTOUT) P22
C0
COM3
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
P77 (SEG8)
P76 (SEG9)
P75 (SEG10)
P74 (SEG11)
P73 (SEG12)
P72 (SEG13)
P71 (SEG14)
P70 (SEG15)
P57 (SEG16)
P56 (SEG17)
P55 (SEG18)
TMP86PS27FG
1.2 Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Figure 1-1 Pin Assignment
Page 3
P54 (SEG19)
P53 (SEG20)
P52 (SEG21)
P51 (SEG22)
P50 (SEG23)
P17 (SEG24)
P16 (SEG25)
P15 (SEG26)
P14 (SEG27)
P13 (SEG28)
P12(SEG29)
P11(SEG30)
P10(SEG31)
P07(SEG32/SCK0)
P06(SEG33/SO0)
P05(SEG34/SI0)
1.3 Block Diagram
TMP86PS27FG
1.3 Block Diagram
Figure 1-2 Block Diagram
Page 4
TMP86PS27FG
1.4 Pin Names and Functions
The TMP86PS27FG has MCU mode and PROM mode. Table 1-1 shows the pin functions in MCU mode. The
PROM mode is explained later in a separate chapter.
Table 1-1 Pin Names and Functions(1/4)
Pin Name
Pin Number
Input/Output
Functions
27
IO
O
IO
PORT07
LCD segment output 32
Serial Clock I/O 0
P06
SEG33
SO0
26
IO
O
O
PORT06
LCD segment output 33
Serial Data Output 0
P05
SEG34
SI0
25
IO
O
I
PORT05
LCD segment output 34
Serial Data Input 0
P04
SEG35
INT3
24
IO
O
I
PORT04
LCD segment output 35
External interrupt 3 input
P03
SEG36
INT2
23
IO
O
I
PORT03
LCD segment output 36
External interrupt 2 input
P02
SEG37
INT1
22
IO
O
I
PORT02
LCD segment output 37
External interrupt 1 input
P01
SEG38
TXD0
21
IO
O
O
PORT01
LCD segment output 38
UART data output 0
P00
SEG39
RXD0
20
IO
O
I
PORT00
LCD segment output 39
UART data input 0
P17
SEG24
35
IO
O
PORT17
LCD segment output 24
P16
SEG25
34
IO
O
PORT16
LCD segment output 25
P15
SEG26
33
IO
O
PORT15
LCD segment output 26
P14
SEG27
32
IO
O
PORT14
LCD segment output 27
P13
SEG28
31
IO
O
PORT13
LCD segment output 28
P12
SEG29
30
IO
O
PORT12
LCD segment output 29
P11
SEG30
29
IO
O
PORT11
LCD segment output 30
P10
SEG31
28
IO
O
PORT10
LCD segment output 31
P22
XTOUT
7
IO
O
PORT22
Resonator connecting pins(32.768kHz) for inputting external
clock
P07
SEG32
SCK0
Page 5
1.4 Pin Names and Functions
TMP86PS27FG
Table 1-1 Pin Names and Functions(2/4)
Pin Name
Pin Number
Input/Output
Functions
6
IO
I
PORT21
Resonator connecting pins(32.768kHz) for inputting external
clock
9
IO
I
I
PORT20
STOP mode release signal input
External interrupt 5 input
P37
RXD1
80
IO
I
PORT37
UART data input 1
P36
PPG2
79
IO
O
PORT36
Timer counter 7 PPG2 output
P35
PPG1
78
IO
O
PORT35
Timer counter 7 PPG1 output
P34
TC7
77
IO
I
PORT34
Timer counter 7 input
76
IO
I
PORT33
Timer counter 7 Emergency stop input
75
IO
O
I
PORT32
PDO4/PWM4/PPG4 output
TC4 input
74
IO
O
I
PORT31
PDO3/PWM3 output
TC3 input
73
IO
O
PORT30
Divider Output
72
IO
O
PORT43
UART data output 1
71
IO
IO
PORT42
Serial Clock I/O 1
P41
SO1
70
IO
O
PORT41
Serial Data Output 1
P40
SI1
69
IO
I
PORT40
Serial Data Input 1
P57
SEG16
43
IO
O
PORT57
LCD segment output 16
P56
SEG17
42
IO
O
PORT56
LCD segment output 17
P55
SEG18
41
IO
O
PORT55
LCD segment output 18
P54
SEG19
40
IO
O
PORT54
LCD segment output 19
P53
SEG20
39
IO
O
PORT53
LCD segment output 20
P52
SEG21
38
IO
O
PORT52
LCD segment output 21
P51
SEG22
37
IO
O
PORT51
LCD segment output 22
P50
SEG23
36
IO
O
PORT50
LCD segment output 23
P21
XTIN
P20
STOP
INT5
P33
EMG
P32
PDO4/PWM4/PPG4
TC4
P31
PDO3/PWM3
TC3
P30
DVO
P43
TXD1
P42
SCK1
Page 6
TMP86PS27FG
Table 1-1 Pin Names and Functions(3/4)
Pin Name
Pin Number
Input/Output
Functions
P67
AIN7
19
IO
I
PORT67
Analog Input7
P66
AIN6
STOP4
18
IO
I
I
PORT66
Analog Input6
STOP4 input
P65
AIN5
STOP3
17
IO
I
I
PORT65
Analog Input5
STOP3 input
P64
AIN4
STOP2
16
IO
I
I
PORT64
Analog Input4
STOP2 input
15
IO
I
I
PORT63
Analog Input3
External interrupt 0 input
P62
AIN2
14
IO
I
PORT62
Analog Input2
P61
AIN1
13
IO
I
PORT61
Analog Input1
P60
AIN0
STOP5
12
IO
I
I
PORT60
Analog Input0
STOP5 input
P77
SEG8
51
IO
O
PORT77
LCD segment output 8
P76
SEG9
50
IO
O
PORT76
LCD segment output 9
P75
SEG10
49
IO
O
PORT75
LCD segment output 10
P74
SEG11
48
IO
O
PORT74
LCD segment output 11
P73
SEG12
47
IO
O
PORT73
LCD segment output 12
P72
SEG13
46
IO
O
PORT72
LCD segment output 13
P71
SEG14
45
IO
O
PORT71
LCD segment output 14
P70
SEG15
44
IO
O
PORT70
LCD segment output 15
SEG7
52
O
LCD segment output 7
SEG6
53
O
LCD segment output 6
SEG5
54
O
LCD segment output 5
SEG4
55
O
LCD segment output 4
SEG3
56
O
LCD segment output 3
SEG2
57
O
LCD segment output 2
SEG1
58
O
LCD segment output 1
SEG0
59
O
LCD segment output 0
COM3
63
O
LCD common output 3
P63
AIN3
INT0
Page 7
1.4 Pin Names and Functions
TMP86PS27FG
Table 1-1 Pin Names and Functions(4/4)
Pin Name
Pin Number
Input/Output
Functions
COM2
62
O
LCD common output 2
COM1
61
O
LCD common output 1
COM0
60
O
LCD common output 0
V3
68
I
LCD voltage booster pin
V2
67
I
LCD voltage booster pin
V1
66
I
LCD voltage booster pin
C1
65
I
LCD voltage booster pin
C0
64
I
LCD voltage booster pin
XIN
2
I
Resonator connecting pins for high-frequency clock
XOUT
3
O
Resonator connecting pins for high-frequency clock
RESET
8
I
Reset signal
TEST
4
I
Test pin for out-going test. Normally, be fixed to low.
VAREF
11
I
Analog Base Voltage Input Pin for A/D Conversion
AVDD
10
I
Analog Power Supply
VDD
5
I
+5V
VSS
1
I
0(GND)
Page 8
TMP86PS27FG
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1
Memory Address Map
The TMP86PS27FG memory is composed OTP, RAM, DBR(Data buffer register) and SFR(Special function
register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86PS27FG memory
address map.
0000H
SFR
SFR:
64 bytes
003FH
0040H
1024
bytes
RAM
RAM:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
043FH
0F80H
DBR:
Data buffer register includes:
Peripheral control registers
Peripheral status registers
LCD display memory
OTP:
Program memory
128
bytes
DBR
0FFFH
1000H
61440
bytes
OTP
FFB0H
Vector table for interrupts
(16 bytes)
FFBFH
FFC0H
Vector table for vector call instructions
(32 bytes)
FFDFH
FFE0H
Vector table for interrupts
FFFFH
(32 bytes)
Figure 2-1 Memory Address Map
2.1.2
Program Memory (OTP)
The TMP86PS27FG has a 61440 bytes (Address 1000H to FFFFH) of program memory (OTP ).
2.1.3
Data Memory (RAM)
The TMP86PS27FG has 1024bytes (Address 0040H to 043FH) of internal RAM. The first 192 bytes (0040H
to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available
against such an area.
Page 9
2. Operational Description
2.2 System Clock Controller
TMP86PS27FG
The data memory contents become unstable when the power supply is turned on; therefore, the data memory
should be initialized by an initialization routine.
Example :Clears RAM to “00H”. (TMP86PS27FG)
SRAMCLR:
LD
HL, 0040H
; Start address setup
LD
A, H
; Initial value (00H) setup
LD
BC, 03FFH
LD
(HL), A
INC
HL
DEC
BC
JRS
F, SRAMCLR
2.2 System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a standby controller.
Timing generator control register
TBTCR
0036H
Clock
generator
XIN
fc
High-frequency
clock oscillator
Timing
generator
XOUT
Standby controller
0038H
XTIN
Low-frequency
clock oscillator
SYSCR1
fs
System clocks
0039H
SYSCR2
System control registers
XTOUT
Clock generator control
Figure 2-2 System Colck Control
2.2.1
Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the
low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power
operation based on the low-frequency clock.
The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator
between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also
possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
Page 10
TMP86PS27FG
Low-frequency clock
High-frequency clock
XIN
XOUT
XIN
XOUT
XTIN
XTOUT
(Open)
(a) Crystal/Ceramic
resonator
XTIN
XTOUT
(Open)
(c) Crystal
(b) External oscillator
(d) External oscillator
Figure 2-3 Examples of Resonator Connection
Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse
which the fixed frequency is outputted to the port by the program.
The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance.
Page 11
2. Operational Description
2.2 System Clock Controller
2.2.2
TMP86PS27FG
Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock
2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
7. LCD
2.2.2.1
Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
fc or fs
Main system clock generator
Machine cycle counters
SYSCK
DV7CK
High-frequency
clock fc
Low-frequency
clock fs
1 2
fc/4
S
A
Divider
Y
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
B
Multiplexer
S
B0
B1
A0 Y0
A1 Y1
Multiplexer
Warm-up
controller
Watchdog
timer
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
Figure 2-4 Configuration of Timing Generator
Page 12
TMP86PS27FG
Timing Generator Control Register
TBTCR
(0036H)
7
6
(DVOEN)
5
(DVOCK)
DV7CK
4
3
DV7CK
(TBTEN)
Selection of input to the 7th stage
of the divider
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: fc/28 [Hz]
1: fs
R/W
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
2.2.2.2
Machine cycle
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc or 1/fs [s]
Main system clock
State
S0
S1
S2
S3
S0
S1
S2
S3
Machine cycle
Figure 2-5 Machine Cycle
2.2.3
Operation Mode Control Circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.
2.2.3.1
Single-clock mode
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
(1)
NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
The TMP86PS27FG is placed in this mode after reset.
Page 13
2. Operational Description
2.2 System Clock Controller
TMP86PS27FG
(2)
IDLE1 mode
In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are
halted; however on-chip peripherals remain active (Operate using the high-frequency clock).
IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1
mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF
(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance
of the interrupt, and the operation will return to normal after the interrupt service is completed. When
the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the
IDLE1 mode start instruction.
(3)
IDLE0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.
This mode is enabled by SYSCR2<TGHALT> = "1".
When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF7 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
2.2.3.2
Dual-clock mode
Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and
P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the
high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in
SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and
4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.
The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program.
(1)
NORMAL2 mode
In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate
using the high-frequency clock and/or low-frequency clock.
(2)
SLOW2 mode
In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency
clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes
into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1
mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.
(3)
SLOW1 mode
This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.
Page 14
TMP86PS27FG
Switching back and forth between SLOW1 and SLOW2 modes are performed by
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is
stopped; output from the 1st to 6th stages is also stopped.
(4)
IDLE2 mode
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are
halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or
the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode,
except that operation returns to NORMAL2 mode.
(5)
SLEEP1 mode
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode.
In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from
the 1st to 6th stages is also stopped.
(6)
SLEEP2 mode
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock.
(7)
SLEEP0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode
is enabled by setting “1” on bit SYSCR2<TGHALT>.
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF
= “1”, EF7 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.
2.2.3.3
STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a
inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After
the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.
Page 15
2. Operational Description
2.2 System Clock Controller
TMP86PS27FG
IDLE0
mode
RESET
Reset release
Note 2
SYSCR2<TGHALT> = "1"
SYSCR1<STOP> = "1"
SYSCR2<IDLE> = "1"
NORMAL1
mode
Interrupt
STOP pin input
IDLE1
mode
(a) Single-clock mode
SYSCR2<XTEN> = "0"
SYSCR2<XTEN> = "1"
SYSCR2<IDLE> = "1"
IDLE2
mode
NORMAL2
mode
Interrupt
SYSCR1<STOP> = "1"
STOP pin input
SYSCR2<SYSCK> = "0"
SYSCR2<SYSCK> = "1"
STOP
SYSCR2<IDLE> = "1"
SLEEP2
mode
SLOW2
mode
Interrupt
SYSCR2<XEN> = "0"
SYSCR2<XEN> = "1"
SYSCR2<IDLE> = "1"
SLEEP1
mode
Interrupt
(b) Dual-clock mode
SYSCR1<STOP> = "1"
SLOW1
mode
STOP pin input
SYSCR2<TGHALT> = "1"
Note 2
SLEEP0
mode
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Table 2-1 Operating Mode and Conditions
Oscillator
Operating Mode
High
Frequency
Low
Frequency
RESET
NORMAL1
Single clock
IDLE1
Oscillation
Reset
Operate
Halt
Operate
Halt
Operate with
high frequency
Machine Cycle
Time
4/fc [s]
–
4/fc [s]
Halt
Oscillation
Operate with
low frequency
Oscillation
Halt
Operate
Operate
Operate with
low frequency
SLOW1
4/fs [s]
Stop
SLEEP0
STOP
Reset
Stop
SLEEP2
SLEEP1
Reset
Halt
SLOW2
Dual clock
Other
Peripherals
Stop
NORMAL2
IDLE2
TBT
Operate
IDLE0
STOP
CPU Core
Halt
Stop
Halt
Page 16
Halt
–
TMP86PS27FG
System Control Register 1
SYSCR1
7
6
5
4
(0038H)
STOP
RELM
RETM
OUTEN
3
2
1
0
WUT
(Initial value: 0000 00**)
STOP
STOP mode start
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
R/W
RELM
Release method for STOP
mode
0: Edge-sensitive release
1: Level-sensitive release
R/W
RETM
Operating mode after STOP
mode
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
R/W
Port output during STOP mode
0: High impedance
1: Output kept
R/W
OUTEN
WUT
Warm-up time at releasing
STOP mode
Return to NORMAL mode
Return to SLOW mode
00
3 x 216/fc
3 x 213/fs
01
216/fc
213/fs
10
3 x 214/fc
3 x 26/fs
11
214/fc
26/fs
R/W
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
from SLOW mode to STOP mode.
Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.
System Control Register 2
SYSCR2
(0039H)
7
6
5
4
XEN
XTEN
SYSCK
IDLE
3
2
1
TGHALT
0
(Initial value: 1000 *0**)
XEN
High-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
XTEN
Low-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
SYSCK
Main system clock select
(Write)/main system clock monitor (Read)
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
IDLE
CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
TGHALT
TG control (IDLE0 and SLEEP0
modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)
R/W
R/W
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
to “0” when SYSCK = “1”.
Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
may be set after IDLE0 or SLEEP0 mode is released.
Page 17
2. Operational Description
2.2 System Clock Controller
2.2.4
TMP86PS27FG
Operating Mode Control
2.2.4.1
STOP mode
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
(STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR).
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
status in effect before STOP mode was entered.
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
which started STOP mode.
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releasing STOP mode in edge-sensitive mode.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2).
However, because the STOP pin is different from the key-on wakeup and can not inhibit the release
input, the STOP pin must be used for releasing STOP mode.
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
(1)
Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2
pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main
power supply is cut off and long term battery backup.
Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5
to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to
first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two
methods can be used for confirmation.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
SSTOPH:
LD
(SYSCR1), 01010000B
; Sets up the level-sensitive release mode
TEST
(P2PRD). 0
; Wait until the STOP pin input goes low level
JRS
F, SSTOPH
; IMF ← 0
DI
SET
(SYSCR1). 7
; Starts STOP mode
Page 18
TMP86PS27FG
Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.
PINT5:
TEST
(P2PRD). 0
; To reject noise, STOP mode does not start if
JRS
F, SINT5
LD
(SYSCR1), 01010000B
port P20 is at high
; Sets up the level-sensitive release mode.
; IMF ← 0
DI
SET
SINT5:
(SYSCR1). 7
; Starts STOP mode
RETI
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
Confirm by program that the
STOP pin input is low and start
STOP mode.
NORMAL
operation
STOP mode is released by the hardware.
Always released if the STOP
pin input is high.
Figure 2-7 Level-sensitive Release Mode
Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
(2)
Edge-sensitive release mode (RELM = “0”)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic
signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In
the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level.
Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode.
Example :Starting STOP mode from NORMAL mode
; IMF ← 0
DI
LD
(SYSCR1), 10010000B
; Starts after specified to the edge-sensitive release mode
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
NORMAL
operation
STOP mode started
by the program.
STOP
operation
STOP mode is released by the hardware at the rising
edge of STOP pin input.
Figure 2-8 Edge-sensitive Release Mode
Page 19
2. Operational Description
2.2 System Clock Controller
TMP86PS27FG
STOP mode is released by the following sequence.
1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency
clock oscillator is turned on.
2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all
internal operations remain halted. Four different warm-up times can be selected with the
SYSCR1<WUT> in accordance with the resonator characteristics.
3. When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction.
Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the
timing generator are cleared to "0".
Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately
performs the normal reset operation.
Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed.
The power supply voltage must be at the operating voltage level before releasing STOP mode.
The RESET pin input must also be “H” level, rising together with the power supply voltage. In this
case, if an external time constant circuit has been connected, the RESET pin input voltage will
increase at a slower pace than the power supply voltage. At this time, there is a danger that a
reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level
input voltage (Hysteresis input).
Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)
Warm-up Time [ms]
WUT
00
01
10
11
Return to NORMAL Mode
Return to SLOW Mode
12.288
4.096
3.072
1.024
750
250
5.85
1.95
Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up
time may include a certain amount of error if there is any fluctuation of the oscillation frequency
when STOP mode is released. Thus, the warm-up time must be considered as an approximate
value.
Page 20
Page 21
Figure 2-9 STOP Mode Start/Release
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
STOP pin
input
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
0
Halt
Turn off
Turn on
Turn on
n
Count up
a+3
Warm up
a+2
n+2
n+3
n+4
0
(b) STOP mode release
1
Instruction address a + 2
a+4
2
Instruction address a + 3
a+5
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
n+1
SET (SYSCR1). 7
a+3
3
Instruction address a + 4
a+6
0
Halt
Turn off
TMP86PS27FG
2. Operational Description
2.2 System Clock Controller
2.2.4.2
TMP86PS27FG
IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
interrupts. The following status is maintained during these modes.
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
operate.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before these modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
Starting IDLE1/2 and
SLEEP1/2 modes by
instruction
CPU and WDT are halted
Yes
Reset input
Reset
No
No
Interrupt request
Yes
“0”
IMF
“1” (Interrupt release mode)
Normal
release mode
Interrupt processing
Execution of the instruction which follows the
IDLE1/2 and SLEEP1/2
modes start instruction
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
Page 22
TMP86PS27FG
• Start the IDLE1/2 and SLEEP1/2 modes
After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2
and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”.
• Release the IDLE1/2 and SLEEP1/2 modes
IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and
SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode
is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes.
IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
(1)
Normal release mode (IMF = “0”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual
interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the
instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt
latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions.
(2)
Interrupt release mode (IMF = “1”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual
interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the
program operation is resumed from the instruction following the instruction, which starts IDLE1/2
and SLEEP1/2 modes.
Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2
modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2
modes will not be started.
Page 23
Page 24
Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Halt
Halt
Halt
Halt
Operate
Operate
Operate
Acceptance of interrupt
Instruction address a + 2
a+4
(b) IDLE1/2 and SLEEP1/2 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
(a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a)
Operate
SET (SYSCR2). 4
a+2
Halt
a+3
2.2 System Clock Controller
2. Operational Description
TMP86PS27FG
TMP86PS27FG
2.2.4.3
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before IDLE0 and SLEEP0 modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
SLEEP0 modes.
Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
Stopping peripherals
by instruction
Starting IDLE0, SLEEP0
modes by instruction
CPU and WDT are halted
Reset input
Yes
Reset
No
No
TBT
source clock
falling
edge
Yes
No
TBTCR<TBTEN>
= "1"
Yes
No
TBT interrupt
enable
Yes
(Normal release mode)
No
IMF = "1"
Yes (Interrupt release mode)
Interrupt processing
Execution of the instruction
which follows the IDLE0,
SLEEP0 modes start
instruction
Figure 2-12 IDLE0 and SLEEP0 Modes
Page 25
2. Operational Description
2.2 System Clock Controller
TMP86PS27FG
• Start the IDLE0 and SLEEP0 modes
Stop (Disable) peripherals such as a timer counter.
To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”.
• Release the IDLE0 and SLEEP0 modes
IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag
of TBT and TBTCR<TBTEN>.
After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is automatically
cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0
modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”,
INTTBT interrupt latch is set to “1”.
IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR<TBTEN> setting.
(1)
Normal release mode (IMF•EF7•TBTCR<TBTEN> = “0”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the
instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or
SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”.
(2)
Interrupt release mode (IMF•EF7•TBTCR<TBTEN> = “1”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK> and INTTBT interrupt processing is started.
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR<TBTCK>.
Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is
started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be
started.
Page 26
Page 27
Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
TBT clock
Halt
Halt
Halt
Watchdog
timer
Main
system
clock
Halt
Instruction
execution
Program
counter
TBT clock
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
a+3
Halt
Operate
Operate
(b) IDLE and SLEEP0 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
Acceptance of interrupt
Instruction address a + 2
a+4
(a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a
Operate
SET (SYSCR2). 2
a+2
TMP86PS27FG
2. Operational Description
2.2 System Clock Controller
2.2.4.4
TMP86PS27FG
SLOW mode
SLOW mode is controlled by the system control register 2 (SYSCR2).
The following is the methods to switch the mode with the warm-up counter.
(1)
Switching from NORMAL2 mode to SLOW1 mode
First, set SYSCR2<SYSCK> to switch the main system clock to the low-frequency clock for
SLOW2 mode. Next, clear SYSCR2<XEN> to turn off high-frequency oscillation.
Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from
SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from
SLOW mode to stop mode.
Example 1 :Switching from NORMAL2 mode to SLOW1 mode.
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
(Switches the main system clock to the low-frequency
clock for SLOW2)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized.
SET
(SYSCR2). 6
; SYSCR2<XTEN> ← 1
LD
(TC3CR), 43H
; Sets mode for TC4, 3 (16-bit mode, fs for source)
LD
(TC4CR), 05H
; Sets warming-up counter mode
LDW
(TTREG3), 8000H
; Sets warm-up time (Depend on oscillator accompanied)
; IMF ← 0
DI
SET
(EIRH). 5
; IMF ← 1
EI
SET
; Enables INTTC4
(TC4CR). 3
; Starts TC4, 3
CLR
(TC4CR). 3
; Stops TC4, 3
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
:
PINTTC4:
(Switches the main system clock to the low-frequency clock)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
RETI
:
VINTTC4:
DW
PINTTC4
; INTTC4 vector table
Page 28
TMP86PS27FG
(2)
Switching from SLOW1 mode to NORMAL2 mode
First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization
(Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the
main system clock to the high-frequency clock.
SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the
operation mode is started from NORMAL1 mode.
Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock
for the period synchronized with low-frequency and high-frequency clocks.
High-frequency clock
Low-frequency clock
Main system clock
SYSCK
Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms).
SET
(SYSCR2). 7
; SYSCR2<XEN> ← 1 (Starts high-frequency oscillation)
LD
(TC3CR), 63H
; Sets mode for TC4, 3 (16-bit mode, fc for source)
LD
(TC4CR), 05H
; Sets warming-up counter mode
LD
(TTREG4), 0F8H
; Sets warm-up time
; IMF ← 0
DI
SET
(EIRH). 5
; IMF ← 1
EI
SET
; Enables INTTC4
(TC4CR). 3
; Starts TC4, 3
CLR
(TC4CR). 3
; Stops TC4, 3
CLR
(SYSCR2). 5
; SYSCR2<SYSCK> ← 0
:
PINTTC4:
(Switches the main system clock to the high-frequency clock)
RETI
:
VINTTC4:
DW
PINTTC4
; INTTC4 vector table
Page 29
Page 30
Figure 2-14 Switching between the NORMAL2 and SLOW Modes
SET (SYSCR2). 7
SET (SYSCR2). 5
SLOW1 mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
NORMAL2
mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
(b) Switching to the NORMAL2 mode
Warm up during SLOW2 mode
CLR (SYSCR2). 5
(a) Switching to the SLOW mode
SLOW2 mode
CLR (SYSCR2). 7
NORMAL2
mode
SLOW1 mode
Turn off
2.2 System Clock Controller
2. Operational Description
TMP86PS27FG
TMP86PS27FG
2.3 Reset Circuit
The TMP86PS27FG has four types of reset generation procedures: An external reset input, an address trap reset, a
watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s].
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when
power is turned on.
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware
Initial Value
Program counter
(PC)
(FFFEH)
Stack pointer
(SP)
Not initialized
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
(JF)
Not initialized
Zero flag
(ZF)
Not initialized
Carry flag
(CF)
Not initialized
Half carry flag
(HF)
Not initialized
Sign flag
(SF)
Not initialized
Overflow flag
(VF)
Not initialized
(IMF)
0
(EF)
0
(IL)
0
Interrupt individual enable flags
Interrupt latches
2.3.1
Initial Value
Prescaler and divider of timing generator
0
Not initialized
Jump status flag
Interrupt master enable flag
On-chip Hardware
Watchdog timer
Enable
Output latches of I/O ports
Refer to I/O port circuitry
Control registers
Refer to each of control
register
LCD data buffer
Not initialized
RAM
Not initialized
External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized.
When the RESET pin input goes high, the reset operation is released and the program execution starts at the
vector address stored at addresses FFFEH to FFFFH.
VDD
RESET
Internal reset
Watchdog timer reset
Malfunction
reset output
circuit
Address trap reset
System clock reset
Figure 2-15 Reset Circuit
Page 31
2. Operational Description
2.3 Reset Circuit
TMP86PS27FG
2.3.2
Address trap reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be
generated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz).
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative.
Instruction
execution
Reset release
JP a
Instruction at address r
Address trap is occurred
Internal reset
maximum 24/fc [s]
4/fc to 12/fc [s]
16/fc [s]
Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Figure 2-16 Address Trap Reset
2.3.3
Watchdog timer reset
Refer to Section “Watchdog Timer”.
2.3.4
System clock reset
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
CPU. (The oscillation is continued without stopping.)
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
The reset time is maximum 24/fc (1.5 µs at 16.0 MHz).
Page 32
TMP86PS27FG
Page 33
2. Operational Description
2.3 Reset Circuit
TMP86PS27FG
Page 34
TMP86PS27FG
3. Interrupt Control Circuit
The TMP86PS27FG has a total of 20 interrupt sources excluding reset. Interrupts can be nested with priorities.
Four of the internal interrupt sources are non-maskable while the rest are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Interrupt Factors
Internal/External
Enable Condition
Interrupt
Latch
Vector
Address
Priority
(Reset)
Non-maskable
–
FFFE
1
Internal
INTSWI (Software interrupt)
Non-maskable
–
FFFC
2
Internal
INTUNDEF (Executed the undefined instruction
interrupt)
Non-maskable
–
FFFC
2
Internal
INTATRAP (Address trap interrupt)
Non-maskable
IL2
FFFA
2
Internal
INTWDT (Watchdog timer interrupt)
Non-maskable
IL3
FFF8
2
External
INTEMG
IMF• EF4 = 1
IL4
FFF6
5
External
INT0
IMF• EF5 = 1, INT0EN = 1
IL5
FFF4
6
External
INT1
IMF• EF6 = 1
IL6
FFF2
7
Internal
INTTBT
IMF• EF7 = 1
IL7
FFF0
8
External
INT2
IMF• EF8 = 1
IL8
FFEE
9
External
INTTC7T
IMF• EF9 = 1
IL9
FFEC
10
Internal
INTRXD
IMF• EF10 = 1
IL10
FFEA
11
Internal
INTSIO
IMF• EF11 = 1
IL11
FFE8
12
Internal
INTTXD
IMF• EF12 = 1
IL12
FFE6
13
Internal
INTTC4
IMF• EF13 = 1
IL13
FFE4
14
Internal
INTTC7P
IMF• EF14 = 1
IL14
FFE2
15
Internal
INTADC
IMF• EF15 = 1
IL15
FFE0
16
External
INT3
IMF• EF16 = 1
IL16
FFBE
17
Internal
INTTC3
IMF• EF17 = 1
IL17
FFBC
18
Internal
INTRTC
IMF• EF18 = 1
IL18
FFBA
19
External
INT5
IMF• EF19 = 1
IL19
FFB8
20
-
Reserved
IMF• EF20 = 1
IL20
FFB6
21
-
Reserved
IMF• EF21 = 1
IL21
FFB4
22
-
Reserved
IMF• EF22 = 1
IL22
FFB2
23
-
Reserved
IMF• EF23 = 1
IL23
FFB0
24
Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
cancelled). For details, see “Address Trap”.
Note 2: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
Note 3: If an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 (INTADC) is
being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being processed. For details,
refer to the corresponding notes in the chapter on the AD converter.
3.1 Interrupt latches (IL19 to IL2)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to “0” during reset.
Page 35
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86PS27FG
The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Each latch can be cleared to
"0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the
interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write
instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed.
Interrupt latches are not set to “1” by an instruction.
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
Example 1 :Clears interrupt latches
; IMF ← 0
DI
LDW
(ILL), 1110100000111111B
; IL12, IL10 to IL6 ← 0
; IMF ← 1
EI
Example 2 :Reads interrupt latchess
WA, (ILL)
; W ← ILH, A ← ILL
TEST
(ILL). 7
; if IL7 = 1 then jump
JR
F, SSET
LD
Example 3 :Tests interrupt latches
3.2 Interrupt enable register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR.
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
registers are located on address 002CH, 003AH and 003BH in SFR area, and they can be read and written by an
instructions (Including read-modify-write instructions such as bit manipulation or operation instructions).
3.2.1
Interrupt master enable flag (IMF)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to “0”.
Page 36
TMP86PS27FG
3.2.2
Individual interrupt enable flags (EF19 to EF4)
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” disables acceptance. During reset, all the individual interrupt enable flags (EF19 to EF4) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Example 1 :Enables interrupts individually and sets IMF
; IMF ← 0
DI
LDW
:
(EIRL), 1110100010100000B
; EF15 to EF13, EF11, EF7, EF5 ← 1
Note: IMF should not be set.
:
; IMF ← 1
EI
Example 2 :C compiler description example
unsigned int _io (3AH) EIRL;
/* 3AH shows EIRL address */
_DI();
EIRL = 10100000B;
:
_EI();
Page 37
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86PS27FG
Interrupt Latches
(Initial value: 00000000 000000**)
ILH,ILL
(003DH, 003CH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
ILH (003DH)
1
0
ILL (003CH)
(Initial value: ****0000)
ILE
(002EH)
7
6
5
4
3
2
1
0
−
−
−
−
IL19
IL18
IL17
IL16
ILE (002EH)
IL19 to IL2
at RD
0: No interrupt request
Interrupt latches
at WR
0: Clears the interrupt request
1: (Interrupt latch is not set.)
1: Interrupt request
R/W
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Interrupt Enable Registers
(Initial value: 00000000 0000***0)
EIRH,EIRL
(003BH, 003AH)
15
14
13
EF15
EF14
EF13
12
11
10
9
8
7
6
5
EF12
EF11
EF10
EF9
EF8
EF7
EF6
EF5
EIRH (003BH)
4
3
2
1
EF4
0
IMF
EIRL (003AH)
(Initial value: ****0000)
EIRE
(002CH)
7
6
5
−
−
−
4
3
2
1
0
−
EF19
EF18
EF17
EF16
EIRE (002CH)
EF19 to EF4
IMF
Individual-interrupt enable flag
(Specified for each bit)
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Interrupt master enable flag
0:
1:
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
R/W
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Page 38
TMP86PS27FG
3.3 Interrupt Sequence
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the
completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
3.3.1
Interrupt acceptance processing is packaged as follows.
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any following interrupt.
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3.
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter.
e. The instruction stored at the entry address of the interrupt service program is executed.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
Interrupt service task
1-machine cycle
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
PC
SP
Execute
instruction
a−1
a
Execute
instruction
Interrupt acceptance
a+1
b
a
b+1 b+2 b + 3
n−1 n−2
n
Execute RETI instruction
c+2
c+1
a
n−2 n−1
n-3
a+1 a+2
n
Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first
machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
service program
Vector table address
FFF0H
03H
FFF1H
D2H
Entry address
Vector
D203H
0FH
D204H
06H
Figure 3-2 Vector table address,Entry address
Page 39
Interrupt
service
program
3. Interrupt Control Circuit
3.3 Interrupt Sequence
TMP86PS27FG
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the
level of current servicing interrupt is requested.
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,
acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length
between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply
nested.
3.3.2
Saving/restoring general-purpose registers
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,
includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are
saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using
the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers.
3.3.2.1
Using PUSH and POP instructions
If only a specific register is saved or interrupts of the same source are nested, general-purpose registers
can be saved/restored using the PUSH/POP instructions.
Example :Save/store register using PUSH and POP instructions
PINTxx:
PUSH
WA
; Save WA register
(interrupt processing)
POP
WA
; Restore WA register
RETI
; RETURN
Address
(Example)
SP
b-5
A
SP
b-4
SP
b-3
PCL
W
PCL
PCH
PCH
PCH
PSW
PSW
PSW
At acceptance of
an interrupt
At execution of
PUSH instruction
PCL
At execution of
POP instruction
b-2
b-1
SP
b
At execution of
RETI instruction
Figure 3-3 Save/store register using PUSH and POP instructions
3.3.2.2
Using data transfer instructions
To save only a specific register without nested interrupts, data transfer instructions are available.
Page 40
TMP86PS27FG
Example :Save/store register using data transfer instructions
PINTxx:
LD
(GSAVA), A
; Save A register
(interrupt processing)
LD
A, (GSAVA)
; Restore A register
RETI
; RETURN
Main task
Interrupt
service task
Interrupt
acceptance
Saving
registers
Restoring
registers
Interrupt return
Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction
Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing
3.3.3
Interrupt return
Interrupt return instructions [RETI]/[RETN] perform as follows.
[RETI]/[RETN] Interrupt Return
1. Program counter (PC) and program status word
(PSW, includes IMF) are restored from the stack.
2. Stack pointer (SP) is incremented by 3.
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
restarting address, during interrupt service program.
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and
PCH are located on address (SP + 1) and (SP + 2) respectively.
Example 1 :Returning from address trap interrupt (INTATRAP) service program
PINTxx:
POP
WA
; Recover SP by 2
LD
WA, Return Address
;
PUSH
WA
; Alter stacked data
(interrupt processing)
RETN
; RETURN
Page 41
3. Interrupt Control Circuit
3.4 Software Interrupt (INTSW)
TMP86PS27FG
Example 2 :Restarting without returning interrupt
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
PINTxx:
INC
SP
; Recover SP by 3
INC
SP
;
INC
SP
;
(interrupt processing)
LD
EIRL, data
; Set IMF to “1” or clear it to “0”
JP
Restart Address
; Jump into restarting address
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed.
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
task is performed but not the main task.
3.4 Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
is highest prioritized interrupt).
Use the SWI instruction only for detection of the address error or for debugging.
3.4.1
Address error detection
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
3.4.2
Debugging
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
address.
3.5 Undefined Instruction Interrupt (INTUNDEF)
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
(SWI) does.
3.6 Address Trap Interrupt (INTATRAP)
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested.
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
watchdog timer control register (WDTCR).
Page 42
TMP86PS27FG
3.7 External Interrupts
The TMP86PS27FG has 7 external interrupt inputs. These inputs are equipped with digital noise reject circuits
(Pulse inputs of less than a certain time are eliminated as noise).
Edge selection is also possible with INT1 to INT3. The INT0/P63 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset.
Edge selection, noise reject control and INT0/P63 pin function selection are performed by the external interrupt
control register (EINTCR).
Source
INT0
INT1
INT2
INT3
INT5
Pin
INT0
INT1
INT2
INT3
INT5
Enable Conditions
Release Edge
Digital Noise Reject
IMF ΠEF5 ΠINT0EN=1
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF6 = 1
Falling edge
or
Rising edge
Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or
more are considered to be signals. In the SLOW
or the SLEEP mode, pulses of less than 1/fs [s]
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
IMF ΠEF8 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF16 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF19 = 1
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
Note 2: When INT0EN = "0", IL5 is not set even if a falling edge is detected on the INT0 pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
Page 43
3. Interrupt Control Circuit
3.7 External Interrupts
TMP86PS27FG
External Interrupt Control Register
EINTCR
7
6
5
4
3
2
1
(0037H)
INT1NC
INT0EN
-
-
INT3ES
INT2ES
INT1ES
0
(Initial value: 00** 000*)
INT1NC
Noise reject time select
0: Pulses of less than 63/fc [s] are eliminated as noise
1: Pulses of less than 15/fc [s] are eliminated as noise
R/W
INT0EN
P63/INT0 pin configuration
0: P63 input/output port
1: INT0 pin (Port P63 should be set to an input mode)
R/W
INT3 ES
INT3 edge select
0: Rising edge
1: Falling edge
R/W
INT2 ES
INT2 edge select
0: Rising edge
1: Falling edge
R/W
INT1 ES
INT1 edge select
0: Rising edge
1: Falling edge
R/W
Note 1: fc: High-frequency clock [Hz], *: Don’t care
Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register
(EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR).
Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.
Page 44
TMP86PS27FG
4. Special Function Register (SFR)
The TMP86PS27FG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address
0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
TMP86PS27FG.
4.1 SFR
Address
Read
Write
0000H
P0DR
0001H
P1DR
0002H
P2DR
0003H
P3DR
0004H
P4DR
0005H
P5DR
0006H
P6DR
0007H
P7DR
0008H
TC7DRAL
0009H
TC7DRAH
000AH
TC7DRBL
000BH
TC7DRBH
000CH
TC7DRCL
000DH
TC7DRCH
000EH
ADCCR1
000FH
ADCCR2
0010H
P0CR
0011H
P1CR
0012H
P3OUTCR
0013H
P4OUTCR
0014H
P6CR1
0015H
P6CR2
0016H
P2PRD
0017H
P3PRD
0018H
TC3CR
0019H
TC4CR
001AH
PWREG3
001BH
PWREG4
001CH
TTREG3
001DH
TTREG4
001EH
Reserved
001FH
Reserved
0020H
ADCDR2
0021H
ADCDR1
-
0022H
P4PRD
-
0023H
P5PRD
-
0024H
P7PRD
-
0025H
UARTSR
UARTCR1
Page 45
-
4. Special Function Register (SFR)
4.1 SFR
TMP86PS27FG
Address
Read
0026H
-
0027H
Write
UARTCR2
Reserved
0028H
LCDCR
0029H
TC7CR1
002AH
TC7CR2
002BH
TC7CR3
002CH
EIRE
002DH
RTCCR
002EH
ILE
002FH
Reserved
0030H
Reserved
0031H
Reserved
0032H
Reserved
0033H
Reserved
0034H
-
WDTCR1
0035H
-
WDTCR2
0036H
TBTCR
0037H
EINTCR
0038H
SYSCR1
0039H
SYSCR2
003AH
EIRL
003BH
EIRH
003CH
ILL
003DH
ILH
003EH
Reserved
003FH
PSW
Note 1: Do not access reserved areas by the program.
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 46
TMP86PS27FG
4.2 DBR
Address
Read
Write
0F80H
SEG1/0
0F81H
SEG3/2
0F82H
SEG5/4
0F83H
SEG7/6
0F84H
SEG9/8
0F85H
SEG11/10
0F86H
SEG13/12
0F87H
SEG15/14
0F88H
SEG17/16
0F89H
SEG19/18
0F8AH
SEG21/20
0F8BH
SEG23/22
0F8CH
SEG25/24
0F8DH
SEG27/26
0F8EH
SEG29/28
0F8FH
SEG31/30
0F90H
SEG33/32
0F91H
SEG35/34
0F92H
SEG37/36
0F93H
SEG39/38
0F94H
Reserved
0F95H
Reserved
0F96H
Reserved
0F97H
Reserved
0F98H
Reserved
0F99H
Reserved
0F9AH
Reserved
0F9BH
Reserved
0F9CH
Reserved
0F9DH
Reserved
0F9EH
Reserved
0F9FH
Reserved
Page 47
4. Special Function Register (SFR)
4.2 DBR
TMP86PS27FG
Address
Read
Write
0FA0H
SIOBR0
0FA1H
SIOBR1
0FA2H
SIOBR2
0FA3H
SIOBR3
0FA4H
SIOBR4
0FA5H
SIOBR5
0FA6H
SIOBR6
0FA7H
SIOBR7
0FA8H
-
SIOCR1
0FA9H
SIOSR
SIOCR2
0FAAH
-
STOPCR
0FABH
RDBUF
TDBUF
0FACH
P0LCR
0FADH
P1LCR
0FAEH
P5LCR
0FAFH
P7LCR
0FB0H
TC7DRDL
0FB1H
TC7DRDH
0FB2H
TC7DREL
0FB3H
TC7DREH
0FB4H
TC7CAPAL
-
0FB5H
TC7CAPAH
-
0FB6H
TC7CAPBL
-
0FB7H
TC7CAPBH
-
0FB8H
Reserved
0FB9H
Reserved
0FBAH
Reserved
0FBBH
MULSEL
0FBCH
Reserved
0FBDH
Reserved
0FBEH
Reserved
0FBFH
Reserved
Address
Read
0FC0H
Write
Reserved
: :
: :
0FDFH
Reserved
Address
Read
0FE0H
Write
Reserved
: :
: :
0FFFH
Reserved
Note 1: Do not access reserved areas by the program.
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 48
TMP86PS27FG
5. I/O Ports
The TMP86PS27FG have 8 parallel input/output ports (55 pins) as follows.
Primary Function
Secondary Functions
Port P0
8-bit I/O port
LCD segment output. External interrupt, serial interface input/output and UART
input/output.
Port P1
8-bit I/O port
LCD segment output.
Port P2
3-bit I/O port
Low-frequency resonator connections, external interrupt input, STOP mode
release signal input.
Port P3
8-bit I/O port
Timer/counter input/output, UART input and divider output.
Port P4
4-bit I/O port
Serial interface input/output and UART output.
Port P5
8-bit I/O port
LCD segment output.
Port P6
8-bit I/O port
Analog input, external interrupt input and STOP mode release signal input.
Port P7
8-bit I/O port
LCD segment output.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
port.
Fetch cycle
S0
Instruction execution cycle
S1
S2 S3
Example: LD
Fetch cycle
S0
S1 S2
S3
Read cycle
S0 S1
S2
S3
A, (x)
Input strobe
Data input
(a) Input timing
Fetch cycle
S0
Instruction execution cycle
S1
S2 S3
Example: LD
Fetch cycle
S0
S1 S2
S3
Write cycle
S0 S1
S2
S3
(x), A
Output strobe
Old
Data output
(b) Output timing
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 5-1 Input/Output Timing (Example)
Page 49
New
5. I/O Ports
5.1 Port P0 (P07 to P00)
TMP86PS27FG
5.1 Port P0 (P07 to P00)
Port P0 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P0 is also
used as a UART input/output, an external interrupt input, serial interface input/output and segment output of LCD.
Input/output mode is specified by the P0 control register (P0CR).
When used as an input port or a secondary function input pins (UART input, external interrupt input or serial interface input), the corresponding bit of P0CR and P0LCR should be cleared to “0”.
When used as an output port, the corresponding bit of P0CR should be set to “1”, and the respective P0LCR bit
should be cleared to “0”. When used as an UART output pin, or serial interface output pin, the corresponding bit of
P0CR and the output latch (P0DR) should be set to “1”, and the respective P0LCR bit should be cleared to “0”.
When used as a segment pins of LCD, the respective bit of P0LCR should be set to “1”.
During reset, the P0DR, P0CR and P0LCR are initialized to “0”.
When the bit of P0CR and P0LCR is “0”, the corresponding bit data by read instruction is a terminal input data.
When the bit of P0CR is “0” and that of P0LCR is “1”, the corresponding bit data by read instruction is always
“0”.
When the bit of P0CR is “1”, the corresponding bit data by read instruction is the value of P0DR.
Table 5-1 Register Programming for Multi-function Ports
Programmed Value
Function
P0DR
P0CR
P0LCR
*
“0”
“0”
Port “0” output
“0”
“1”
“0”
Port “1” output, UART output and serial interface output
“1”
“1”
“0”
*
*
“1”
Port input, UART input, serial interface input, and
external interrupt input
LCD segment output
Note: Asterisk (*) indicates “1” or “0” either of which can be selected.
Table 5-2 Values Read from P0DR and Register Programming
Conditions
Values Read from P0DR
P0CR
P0LCR
“0”
“0”
Terminal input data
“0”
“1”
“0”
“0”
“1”
Output latch contents
“1”
Page 50
TMP86PS27FG
STOP
OUTEN
P0LCRi input
P0LCRi
D
Q
D
Q
D
Q
P0CRi input
P0CRi
Data input (P0DRi)
Data output (P0DRi)
P0i
Output latch
LCD data output
Note: i = 7 to 0
Figure 5-2 Port 0
P0DR
(0000H)
R/W
7
6
5
4
3
2
1
0
P07
SEG32
P06
SEG33
SO0
P05
SEG34
SI0
P04
SEG35
INT3
P03
SEG36
INT2
P02
SEG37
INT1
P01
SEG38
TXD0
P00
SEG39
RXD0
SCK0
(Initial value: 0000 0000)
(Initial value: 0000 0000)
P0LCR
(0FACH)
P0LCR
Port P0/segment output control (Set for each bit individually)
0:P0 input/output port or secondary function
(excect for segment)
1: LCD segment output
R/W
(Initial value: 0000 0000)
P0CR
(0010H)
P0CR
P0 port input/output control (Set for each bit individually)
0: Input mode
1: Output mode
R/W
Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the
output latch contents for the port in input mode might be changed by executing a bit manipulation instruction.
Multi function register
7
6
5
4
3
2
MULSEL
(0FBBH)
SIOSEL
UARTSEL
1
0
SIOSEL
UARTSEL
SIO function pins select
0: P05(SI0), P06(SO0), P07(SCK0)
1: P40(SI1), P41(SO1), P42(SCK1)
UART function pins select
0: P01(TXD0), P00(RXD0)
1: P43(TXD1), P37(RXD1)
Note 1: Do not change a terminal during operation.
Page 51
(Initial value: **** **00)
R/W
5. I/O Ports
5.1 Port P0 (P07 to P00)
TMP86PS27FG
Note 2: Perform the setting terminal of a port after performing a setup by MULSEL, when changing a terminal.
Page 52
TMP86PS27FG
5.2 Port P1 (P17 to P10)
Port P1 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P1 is also
used as a segment output of LCD. Input/output mode is specified by the P1 control register (P1CR).
When used as an input port, the corresponding bit of P1CR and P1LCR should be cleared to “0”.
When used as an output port, the corresponding bit of P1CR should be set to “1”, and the respective P1LCR bit
should be cleared to “0”.
When used as a segment pins of LCD, the respective bit of P1LCR should be set to “1”.
During reset, the output latch (P1DR), P1CR and P1LCR are initialized to “0”.
When the bit of P1CR and P1LCR is “0”, the corresponding bit data by read instruction is a terminal input data.
When the bit of P1CR is “0” and that of P1LCR is “1”, the corresponding bit data by read instruction is always
“0”.
When the bit of P1CR is “1”, the corresponding bit data by read instruction is the value of P1DR.
Table 5-3 Register Programming for Multi-function Ports
Programmed Value
Function
P1DR
P1CR
P1LCR
*
“0”
“0”
Port “0” output
“0”
“1”
“0”
Port “1” output
“1”
“1”
“0”
*
*
“1”
Port input
LCD segment output
Note: Asterisk (*) indicates “1” or “0” either of which can be selected.
Table 5-4 Values Read from P1DR and Register Programming
Conditions
Values Read from P1DR
P1CR
P1LCR
“0”
“0”
Terminal input data
“0”
“1”
“0”
“0”
“1”
Output latch contents
“1”
Page 53
5. I/O Ports
5.2 Port P1 (P17 to P10)
TMP86PS27FG
STOP
OUTEN
P1LCRi input
P1LCRi
D
Q
D
Q
D
Q
P1CRi input
P1CRi
Data input (P1DRi)
Data output (P1DRi)
P1i
Output latch
LCD data output
Note: i = 7 to 0
Figure 5-3 Port 1
P1DR
(0001H)
R/W
7
6
5
4
3
2
1
0
P17
SEG24
P16
SEG25
P15
SEG26
P14
SEG27
P13
SEG28
P12
SEG29
P11
SEG30
P10
SEG31
(Initial value: 0000 0000)
(Initial value: 0000 0000)
P1LCR
(0FADH)
P1LCR
Port P1/segment output control (Set for each bit individually)
0: P1 input/output port
1: LCD segment output
R/W
(Initial value: 0000 0000)
P1CR
(0011H)
P1CR
P1 port input/output control
(Set for each bit individually)
0: Input mode
1: Output mode
R/W
Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the
output latch contents for the port in input mode might be changed by executing a bit manipulation instruction.
Page 54
TMP86PS27FG
5.3 Port P2 (P22 to P20)
Port P2 is a 3-bit input/output port.
It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set
to “1”.
During reset, the P2DR is initialized to “1”.
A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dualclock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports.
It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or
an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse.
P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address.
When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable.
Data input (P20PRD)
Data input (P20)
Data output (P20)
D
P20 (INT5, STOP)
Q
Output latch
Contorl input
Data input (P21PRD)
Osc. enable
Output latch read (P21)
Data output (P21)
D
P21 (XTIN)
Q
Output latch
Data input (P22PRD)
Output latch read (P22)
Data output (P22)
D
P22 (XTOUT)
Q
Output latch
STOP
OUTEN
XTEN
fs
Figure 5-4 Port 2
P2DR
(0002H)
R/W
7
6
5
4
3
2
1
0
P22
XTOUT
P21
XTIN
P20
INT5
(Initial value: **** *111)
STOP
P2PRD
(0F9CH)
Read only
P22
P21
P20
Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
high-Z mode.
Page 55
5. I/O Ports
5.4 Port P3 (P37 to P30)
TMP86PS27FG
5.4 Port P3 (P37 to P30)
Port P3 is a 8-bit input/output port.
It is also used as a timer/counter input/output or divider output.
When used as a timer/counter output or divider output, respective output latch (P3DR) should be set to “1”.
It can be selected whether output circuit of port P3 is C-MOS output or a sink open drain individually, by setting
P3OUTCR. When a corresponding bit of P3OUTCR is “0”, the output circuit is selected to a sink open drain and
when a corresponding bit of P3OUTCR is “1”, the output circuit is selected to a C-MOS output. When used as an
input port or timer/counter input, respective output control (P3OUTCR) should be set to “0” after P3DR is set to “1”.
When using this port as a PPG1 and/or PPG2 output, set the output latch (P3DR) and then set the P3OUTCR to “1”.
Next, set the PPG output initial value in the PPG1INI and/or PPG2INI, and set the PPG1OE and/or PPG2OE to “1”
to enable PPG output. At this time, the output latch (P3DR) should be set to the same value as the PPG output initial
value (PPG1INI, PPG2INI). During reset, the P3DR is initialized to “1”, and the P3OUTCR is initialized to “0”.
P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address.
When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD register should be read.
STOP
OUTEN
P3OUTCRi
D
Q
P3OUTCRi input
Data input (P3PRD)
Output latch read (P3DR)
Data output (P3DR)
Control output
D
Q
P3i
Output latch
Control input
a) P37, P34, P33, P32, P31, P30
Note: i = 4 to 0 and 7
STOP
OUTEN
P3OUTCRj
D
Q
P3OUTCRj
Data input (P3PRD)
Data latch read (P3DR)
Data output (P3DR)
D
A
Q
P3i
Output latch
PPGk
B
PPGkINI
S
PPGkOE
b) P36, P35
Note: j = 6, 5 k = 2, 1
Figure 5-5 Port 3
Page 56
TMP86PS27FG
P3DR
(0003H)
R/W
7
6
5
4
3
2
1
0
P37
RXD1
P36
PPG2
P35
PPG1
P34
TC7
P33
P32
P31
P30
EMG
PWM4
PWM3
DVO
PDO4
PDO3
PPG4
TC3
(Initial value: 1111 1111)
TC4
(Initial value: 0000 0000)
P3OUTCR
(0012H)
P3OUTCR
P3PRD
(0017H)
Read only
P37
Port P3 output circuit control (Set for each bit individually)
P36
P35
P34
P33
P32
P31
0: Sink open-drain output
1: C-MOS output
P30
Multi function register
7
6
5
4
3
2
MULSEL
(0FBBH)
SIOSEL
UARTSEL
1
0
SIOSEL
UARTSEL
SIO function pins select
0: P05(SI0), P06(SO0), P07(SCK0)
1: P40(SI1), P41(SO1), P42(SCK1)
UART function pins select
0: P01(TXD0), P00(RXD0)
1: P43(TXD1), P37(RXD1)
(Initial value: **** **00)
R/W
Note 1: Do not change a terminal during operation.
Note 2: Perform the setting terminal of a port after performing a setup by MULSEL, when changing a terminal.
Page 57
R/W
5. I/O Ports
5.5 Port P4 (P43 to P40)
TMP86PS27FG
5.5 Port P4 (P43 to P40)
Port P4 is a 4-bit input/output port.
It is also used as a UART output or serial interface input/output.
When used as a UART output or serial interface output, respective output latch (P4DR) should be set to “1”.
It can be selected whether output circuit of port P4 is C-MOS output or a sink open drain individually, by setting
P4OUTCR. When a corresponding bit of P4OUTCR is “0”, the output circuit is selected to a sink open drain and
when a corresponding bit of P4OUTCR is “1”, the output circuit is selected to a C-MOS output. When used as an
input port or serial interface input, respective output control (P4OUTCR) should be set to “0” after P4DR is set to
“1”. During reset, the P4DR is initialized to “1”, and the P4OUTCR is initialized to “0”.
P4 port output latch (P4DR) and P4 port terminal input (P4PRD) are located on their respective address.
When read the output latch data, the P4DR should be read and when read the terminal input data, the P4PRD register should be read. If a read instruction is executed for the P4PRD, P4DR and the P4OUTCR, read data of bits 7 to
5 are unstable.
Table 5-5 Register Programming for Multi-function Ports (P43 to P40)
Programmed Value
Function
P4DR
P4OUTCR
Port input or timer counter input
“1”
“0”
Port “0” output
“0”
Port “1” output or timer counter output
“1”
Programming
for each applications
STOP
OUTEN
P4OUTCRi
D
Q
P4OUTCRi input
Data input (P4PRD)
Output latch read (P4DR)
Data output (P4DR)
Control output
D
Q
P4i
Output latch
Control input
Note: i = 4 to 0
Figure 5-6 Port 4
Page 58
TMP86PS27FG
P4DR
(0004H)
R/W
7
6
5
4
3
2
1
0
P43
TXD1
P42
SCK1
P41
SO1
P40
SI1
(Initial value: **** 1111)
(Initial value: **** 0000)
P4OUTCR
(0013H)
P4OUTCR
Port P4 output circuit control (Set for each bit individually)
P4PRD
(0022H)
Read only
P43
P42
P41
0: Sink open-drain output
1: C-MOS output
P40
Multi function register
7
6
5
4
3
2
MULSEL
(0FBBH)
SIOSEL
UARTSEL
1
0
SIOSEL
UARTSEL
SIO function pins select
0: P05(SI0), P06(SO0), P07(SCK0)
1: P40(SI1), P41(SO1), P42(SCK1)
UART function pins select
0: P01(TXD0), P00(RXD0)
1: P43(TXD1), P37(RXD1)
(Initial value: **** **00)
R/W
Note 1: Do not change a terminal during operation.
Note 2: Perform the setting terminal of a port after performing a setup by MULSEL, when changing a terminal.
Page 59
R/W
5. I/O Ports
5.6 Port P5 (P57 to P50)
TMP86PS27FG
5.6 Port P5 (P57 to P50)
Port P5 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P5 is also
used as a segment output of LCD.
When used as an input port, the corresponding bit of P5LCR should be cleared to “0”, and the respective P5DR bit
should be set to “1”.
When used as an output port, the respective P5LCR bit should be cleared to “0”.
When used as a segment pins of LCD, the respective bit of P5LCR should be set to “1”.
During reset, the output latch (P5DR) are intialized to “1”, and P5LCR are initialized to “0”.
P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address.
When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD register should be read.
If the terminal input data which is configured as LCD segment output is read, unstable data is read.
Table 5-6 Register Programming for Multi-function Ports
Programmed Value
Function
P5DR
P5LCR
Port input
“1”
“0”
Port “0” output
“0”
“0”
*
“1”
LCD segment output
Note: Asterisk (*) indicates “1” or “0” either of which can be selected.
STOP
OUTEN
P5LCRi
D
Q
D
Q
P5CRi input
Terminal input (P5PRD)
Output latch data (P5DRi)
Data output (P5DR)
P5i
Output latch
LCD data output
Note: i = 7 to 0
Figure 5-7 Port 5
Page 60
TMP86PS27FG
P5DR
(0005H)
R/W
7
6
5
4
3
2
1
0
P57
SEG16
P56
SEG17
P55
SEG18
P54
SEG19
P53
SEG20
P52
SEG21
P51
SEG22
P50
SEG23
(Initial value: 0000 0000)
P5LCR
(0FAEH)
P5LCR
P5PRD
(0023H)
Read only
(Initial value: 1111 1111)
P57
Port P5/segment output control (Set for each bit individually)
P56
P55
P54
P53
P52
Page 61
P51
0: P5 input/output port
1: LCD segment output
P50
R/W
5. I/O Ports
5.7 Port P6 (P67 to P60)
TMP86PS27FG
5.7 Port P6 (P67 to P60)
Port P6 is an 8-bit input/output port which can be configured as an input or an output in 1-bit unit. Port P6 is also
used as an analog input, key-on wakeup input and external interrupt input. Input/output mode is specified by the P6
control register (P6CR1) and input control register (P6CR2).
When used as an output port, the corresponding bit of P6CR1 should be set to “1”.
When used as an input port, key-on wakeup input or an external interrupt input, the corresponding bit of P6CR1
should be cleared to “0”, and then, the corresponding bit of P6CR2 should be set to “1”.
When used as an analog input, the corresponding bit of P6CR1 should be cleared to “0”, and then, the corresponding bit of P6CR2 should be cleared to “0”.
During reset, the output latch (P6DR) and P6CR1 are initialized to “0”, P6CR2 is initialized to “1”.
When the bit of P6CR1 and P6CR2 is “0”, the corresponding bit data by read instruction is always “0”.
When the bit of P6CR1 is “0” and that of P6CR2 is “1”, the corresponding bit data by read instruction is a terminal
input data.
When the bit of P6CR1 is “1”, the corresponding bit data by read instruction is the value of P6DR.
Table 5-7 Register Programming for Multi-function Ports
Programmed Value
Function
P6DR
P6CR1
P6CR2
Port input external interrupt input or key-on wakeup
input
*
“0”
“1”
Analog input
*
“0”
“0”
Port “0” output
“0”
“1”
*
Port “1” output
“1”
“1”
*
Note: Asterisk (*) indicates “1” or “0” either of which can be selected.
Table 5-8 Values Read from P6DR and Register Programming
Conditions
Values Read from P6DR
P6CR1
P6CR2
“0”
“0”
“0”
“0”
“1”
Terminal input data
“0”
“1”
Output latch contents
“1”
Page 62
TMP86PS27FG
P6CR2i
D
Q
D
Q
D
Q
P6CR2i input
P6CR1i
P6CR1i input
Control input
Data input (P6DRi)
Data output (P6DRi)
P6i
STOP
OUTTEN
Analog input
AINDS
SAIN
a) P67, P63, P62, P61
Key-on wakeup
STOPk
P6CR2j
D
Q
D
Q
D
Q
P6CR2j input
P6CR1j
P6CR1j input
Data input (P6DRj)
Data output (P6DRj)
P6i
STOP
OUTTEN
Analog input
AINDS
SAIN
b) P66, P65, P64, P60
Note 1: i = 1 to 3 and 7, j = 4 to 6 and 0, k = 2 to 5
Note 2: STOP is bit7 in SYSCR1.
Note 3: SAIN is AD input select signal.
Note 4: STOPk is input select signal in a key-on wakeup.
Figure 5-8 Port 6
Note 1: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used
together, the output latch contents for the port in input mode might be changed by executing a bit manipulation
instruction.
Note 2: When used as an analog inport, be sure to clear the corresponding bit of P6CR2 to disable the port input.
Note 3: Do not set the output mode (P6CR1 = “1”) for the pin used as an analog input pin.
Note 4: Pins not used for analog input can be used as I/O ports. During AD conversion, output instructions should not be
executed to keep a precision. In addition, a variable signal should not be input to a port adjacent to the analog
input during AD conversion.
Page 63
5. I/O Ports
5.7 Port P6 (P67 to P60)
P6DR
(0006H)
R/W
P6CR1
(0014H)
P6CR2
(0015H)
TMP86PS27FG
7
6
5
4
3
2
1
0
P67
AIN7
P66
AIN6
STOP4
P65
AIN5
STOP3
P64
AIN4
STOP2
P63
AIN3
P62
AIN2
P61
AIN1
P60
AIN0
STOP5
6
5
4
3
2
1
0
7
INT0
(Initial value: 0000 0000)
(Initial value: 0000 0000)
P6CR1
I/O control for port P6 (Specified for each bit)
7
6
5
4
3
0: Input mode
1: Output mode
2
1
R/W
0
(Initial value: 1111 1111)
P6CR2
P6 port input control (Specified for each bit)
Page 64
0: Analog input
1: Port input, external interrupt input or key-on wakeup
input
R/W
TMP86PS27FG
5.8 Port P7 (P77 to P70)
Port P7 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P7 is also
used as a segment output of LCD.
When used as an input port, the corresponding bit of P7LCR should be cleared to “0”, and the respective P7DR bit
should be set to “1”.
When used as an output port, the respective P7LCR bit should be cleared to “0”.
When used as a segment pins of LCD, the respective bit of P7LCR should be set to “1”.
During reset, the output latch (P7DR) are initialized to “1”, and P7LCR are initialized to “0”.
P7 port output latch (P7DR) and P7 port terminal input (P7PRD) are located on their respective address.
When read the output latch data, the P7DR should be read and when read the terminal input data, the P7PRD register should be read.
If the terminal input data which is configured as LCD segment output is read, unstable data is read.
Table 5-9 Register Programming for Multi-function Ports
Programmed Value
Function
P7DR
P7LCR
Port input
“1”
“0”
Port “0” output
“0”
“0”
*
“1”
LCD segment outputt
Note: Asterisk (*) indicates “1” or “0” either of which can be selected.
STOP
OUTEN
P7LCRi
D
Q
D
Q
P7CRi input
Terminal input (P7PRD)
Output latch data (P7DR)
Data output (P7DR)
P7i
Output latch
LCD data output
Note: i = 7 to 0
Figure 5-9 Port 7
Page 65
5. I/O Ports
5.8 Port P7 (P77 to P70)
P7DR
(0007H)
R/W
TMP86PS27FG
7
6
5
4
3
2
1
0
P77
SEG8
P76
SEG9
P75
SEG10
P74
SEG11
P73
SEG12
P72
SEG13
P71
SEG14
P70
SEG15
(Initial value: 0000 0000)
P7LCR
(0FAFH)
P7LCR
P7PRD
(0024H)
Read only
(Initial value: 1111 1111)
P77
Port P7/segment output control (Set for each bit individually)
P76
P75
P74
P73
P72
Page 66
P71
0: P7 input/output port
1: Segment output
P70
(Initial value: 0000 0000)
R/W
TMP86PS27FG
6. Time Base Timer (TBT)
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base
timer interrupt (INTTBT).
6.1 Time Base Timer
6.1.1
Configuration
MPX
fc/223 or fs/215
fc/221 or fs/213
fc/216 or fs/28
fc/214 or fs/26
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/29 or fs/2
Source clock
IDLE0, SLEEP0
release request
Falling edge
detector
INTTBT
interrupt request
3
TBTCK
TBTEN
TBTCR
Time base timer control register
Figure 6-1 Time Base Timer configuration
6.1.2
Control
Time Base Timer is controled by Time Base Timer control register (TBTCR).
Time Base Timer Control Register
7
TBTCR
(0036H)
6
(DVOEN)
TBTEN
5
(DVOCK)
Time Base Timer
enable / disable
4
3
(DV7CK)
TBTEN
2
1
0
TBTCK
(Initial Value: 0000 0000)
0: Disable
1: Enable
NORMAL1/2, IDLE1/2 Mode
TBTCK
Time Base Timer interrupt
Frequency select : [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
000
fc/223
fs/215
fs/215
001
fc/221
fs/213
fs/213
010
fc/216
fs/28
–
011
fc/2
14
6
–
100
fc/213
fs/25
–
101
fc/2
12
4
–
110
fc/211
fs/23
–
111
9
fs/2
–
fc/2
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care
Page 67
fs/2
fs/2
R/W
6. Time Base Timer (TBT)
6.1 Time Base Timer
TMP86PS27FG
Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously.
Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt.
LD
(TBTCR) , 00000010B
; TBTCK ← 010
LD
(TBTCR) , 00001010B
; TBTEN ← 1
; IMF ← 0
DI
SET
(EIRL) . 7
Table 6-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Time Base Timer Interrupt Frequency [Hz]
TBTCK
6.1.3
NORMAL1/2, IDLE1/2 Mode
NORMAL1/2, IDLE1/2 Mode
SLOW1/2, SLEEP1/2 Mode
DV7CK = 0
DV7CK = 1
000
1.91
1
1
001
7.63
4
4
010
244.14
128
–
011
976.56
512
–
100
1953.13
1024
–
101
3906.25
2048
–
110
7812.5
4096
–
111
31250
16384
–
Function
An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider
output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled.
The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set
interrupt period ( Figure 6-2 ).
Source clock
TBTCR<TBTEN>
INTTBT
Interrupt period
Enable TBT
Figure 6-2 Time Base Timer Interrupt
Page 68
TMP86PS27FG
6.2 Divider Output (DVO)
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
buzzer drive. Divider output is from DVO pin.
6.2.1
Configuration
Output latch
D
Data output
Q
DVO pin
MPX
A
B
C Y
D
S
2
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/210 or fs/22
Port output latch
TBTCR<DVOEN>
DVOCK
DVOEN
TBTCR
DVO pin output
Divider output control register
(a) configuration
(b) Timing chart
Figure 6-3 Divider Output
6.2.2
Control
The Divider Output is controlled by the Time Base Timer Control Register.
Time Base Timer Control Register
7
TBTCR
(0036H)
DVOEN
DVOEN
6
5
DVOCK
4
3
(DV7CK)
(TBTEN)
Divider output
enable / disable
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: Disable
1: Enable
R/W
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
00
fc/213
fs/25
fs/25
01
fc/212
fs/24
fs/24
10
fc/211
fs/23
fs/23
11
fc/210
fs/22
fs/22
NORMAL1/2, IDLE1/2 Mode
DVOCK
Divider Output (DVO)
frequency selection: [Hz]
R/W
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
Page 69
6. Time Base Timer (TBT)
6.2 Divider Output (DVO)
TMP86PS27FG
Example :1.95 kHz pulse output (fc = 16.0 MHz)
LD
(TBTCR) , 00000000B
; DVOCK ← "00"
LD
(TBTCR) , 10000000B
; DVOEN ← "1"
Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Divider Output Frequency [Hz]
DVOCK
NORMAL1/2, IDLE1/2 Mode
DV7CK = 0
DV7CK = 1
SLOW1/2, SLEEP1/2
Mode
00
1.953 k
1.024 k
1.024 k
01
3.906 k
2.048 k
2.048 k
10
7.813 k
4.096 k
4.096 k
11
15.625 k
8.192 k
8.192 k
Page 70
TMP86PS27FG
7. Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine.
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “interrupt request”. Upon the reset release, this signal is initialized to “reset request”.
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt.
Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to
effect of disturbing noise.
7.1 Watchdog Timer Configuration
Reset release
23
15
Binary counters
Selector
fc/2 or fs/2
fc/221 or fs/213
fc/219 or fs/211
fc/217 or fs/29
Clock
Clear
R
Overflow
1
WDT output
2
S
2
Q
Interrupt request
Internal reset
Q
S R
WDTEN
WDTT
Writing
disable code
Writing
clear code
WDTOUT
Controller
0034H
WDTCR1
0035H
WDTCR2
Watchdog timer control registers
Figure 7-1 Watchdog Timer Configuration
Page 71
Reset
request
INTWDT
interrupt
request
7. Watchdog Timer (WDT)
7.2 Watchdog Timer Control
TMP86PS27FG
7.2 Watchdog Timer Control
The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release.
7.2.1
Malfunction Detection Methods Using the Watchdog Timer
The CPU malfunction is detected, as shown below.
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and then internal hardware is
initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated.
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP
mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH
is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow
time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/
4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the
time set to WDTCR1<WDTT>.
Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection
Within 3/4 of WDT
detection time
LD
(WDTCR2), 4EH
: Clears the binary counters.
LD
(WDTCR1), 00001101B
: WDTT ← 10, WDTOUT ← 1
LD
(WDTCR2), 4EH
: Clears the binary counters (always clears immediately before and
after changing WDTT).
(WDTCR2), 4EH
: Clears the binary counters.
(WDTCR2), 4EH
: Clears the binary counters.
:
:
LD
Within 3/4 of WDT
detection time
:
:
LD
Page 72
TMP86PS27FG
Watchdog Timer Control Register 1
WDTCR1
(0034H)
7
WDTEN
6
5
4
3
(ATAS)
(ATOUT)
WDTEN
Watchdog timer enable/disable
2
1
0
WDTT
WDTOUT
(Initial value: **11 1001)
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
NORMAL1/2 mode
WDTT
WDTOUT
Watchdog timer detection time
[s]
Watchdog timer output select
DV7CK = 0
DV7CK = 1
SLOW1/2
mode
00
225/fc
217/fs
217/fs
01
223/fc
215/fs
215fs
10
221fc
213/fs
213fs
11
219/fc
211/fs
211/fs
0: Interrupt request
1: Reset request
Write
only
Write
only
Write
only
Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
don’t care is read.
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “1.2.3 Watchdog Timer Disable”.
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
6
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
Write
Watchdog timer control code
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
D2H: Enable assigning address trap area
Others: Invalid
Write
only
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
7.2.2
Watchdog Timer Enable
Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
to “1” during reset, the watchdog timer is enabled automatically after the reset release.
Page 73
7. Watchdog Timer (WDT)
7.2 Watchdog Timer Control
7.2.3
TMP86PS27FG
Watchdog Timer Disable
To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller.
1. Set the interrupt master flag (IMF) to “0”.
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to “0”.
4. Set WDTCR2 to the disable code (B1H).
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Example :Disabling the watchdog timer
: IMF ← 0
DI
LD
(WDTCR2), 04EH
: Clears the binary coutner
LDW
(WDTCR1), 0B101H
: WDTEN ← 0, WDTCR2 ← Disable code
Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)
Watchdog Timer Detection Time[s]
WDTT
7.2.4
NORMAL1/2 mode
DV7CK = 0
DV7CK = 1
SLOW
mode
00
2.097
4
4
01
524.288 m
1
1
10
131.072 m
250 m
250 m
11
32.768 m
62.5 m
62.5 m
Watchdog Timer Interrupt (INTWDT)
When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated
by the binary-counter overflow.
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
master flag (IMF).
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is
held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the
RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Example :Setting watchdog timer interrupt
LD
SP, 043FH
: Sets the stack pointer
LD
(WDTCR1), 00001000B
: WDTOUT ← 0
Page 74
TMP86PS27FG
7.2.5
Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset
time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
219/fc [s]
217/fc
Clock
Binary counter
(WDTT=11)
1
2
3
0
1
2
3
0
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
A reset occurs
(WDTCR1<WDTOUT>= "1")
Write 4EH to WDTCR2
Figure 7-2 Watchdog Timer Interrupt
Page 75
7. Watchdog Timer (WDT)
7.3 Address Trap
TMP86PS27FG
7.3 Address Trap
The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address
traps.
Watchdog Timer Control Register 1
7
WDTCR1
(0034H)
6
ATAS
ATOUT
5
4
3
ATAS
ATOUT
(WDTEN)
2
1
(WDTT)
0
(WDTOUT)
(Initial value: **11 1001)
Select address trap generation in
the internal RAM area
0: Generate no address trap
1: Generate address traps (After setting ATAS to “1”, writing the control code
D2H to WDTCR2 is reguired)
Select opertion at address trap
0: Interrupt request
1: Reset request
Write
only
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
7.3.1
6
Write
Watchdog timer control code
and address trap area control
code
D2H: Enable address trap area selection (ATRAP control code)
4EH: Clear the watchdog timer binary counter (WDT clear code)
B1H: Disable the watchdog timer (WDT disable code)
Others: Invalid
Write
only
Selection of Address Trap in Internal RAM (ATAS)
WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To execute
an instruction in the internal RAM area, clear WDTCR1<ATAS> to “0”. To enable the WDTCR1<ATAS> setting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the
setting in WDTCR1<ATAS>.
7.3.2
Selection of Operation at Address Trap (ATOUT)
When an address trap is generated, either the interrupt request or the reset request can be selected by
WDTCR1<ATOUT>.
7.3.3
Address Trap Interrupt (INTATRAP)
While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt master flag (IMF).
When an address trap interrupt is generated while the other interrupt including a watchdog timer interrupt is
already accepted, the new address trap is processed immediately and the previous interrupt is held pending.
Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
To generate address trap interrupts, set the stack pointer beforehand.
Page 76
TMP86PS27FG
7.3.4
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum
24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 77
7. Watchdog Timer (WDT)
7.3 Address Trap
TMP86PS27FG
Page 78
TMP86PS27FG
8. 10-Bit Timer/Counter (TC7)
8.1 Configuration
CSIDIS
TC7CR3
TC7ST
EMGF
CSTC
A
B
C
D
fc
fc/2
fc/22
fc/23
STM
Y
INTTC7T interrupt request
10-bit up counter
Start/
clear
S
TC7CK
PPG2INI
PPG1INI
CNTBF
TGRAM
TC7CR1
Noise
canceller
TC7 pin
TC7CAPA
TRGSEL
NCRSEL
TC7CAPB
Capture
control
Edge
detection
INTTC7P interrupt request
CSIDIS
PPG1
Comparator
Compare
register A
Compare
register B
Compare
register C
PPG output control
Compare
register D
PPG2
TC7OUT PPG1OE/ PPG1INI/
PPG2OE PPG2INI
Compare
register E
Transfer control
TC7DRA
TC7DRB
TC7DRC
TC7DRD
TC7DRE
Emergency stop
EMGF
Emergency output
EMG pin
INTEMG interrupt request
stop control
EMGIE
EMGR
CSTC
PPG2OE
PPG1OE
TC7CR2
TC7OUT
Figure 8-1 10-Bit Timer/Counter 7
8.2 Control
Timer/counter 7 is controlled by timer/counter control register 1 (TC7CR1), timer/counter control register 2
(TC7CR2), timer/counter control register 3 (TC7CR3), 10-bit dead time 1 setup register (TC7DRA), pulse width 1
setup register (TC7DRB), period setup register (TC7DRC), dead time 2 setup register (TC7DRD), pulse width 2
setup register (TC7DRE), and two capture value registers (TC7CAPA and TC7CAPB).
Timer/Counter 7 Control Register 1
TC7CR1
(0029H)
7
6
5
4
TRGAM
TRGSEL
PPG2INI
PPG1INI
3
2
NCRSEL
Page 79
1
0
TC7CK
(Initial value: 0000 0000)
8. 10-Bit Timer/Counter (TC7)
8.2 Control
TMP86PS27FG
TC7CK
Select a source clock
(Supplied to the up counter).
00: fc
01: fc/2
[Hz]
[Hz]
10 fc/22
[Hz]
11: fc/23 [Hz]
NCRSEL
Select the duration of noise elimination for
TC7 input
(after passing through the flip-flop).
00: Eliminate pulses shorter than 16/fc [s] as noise.
01: Eliminate pulses shorter than 8/fc [s] as noise.
10: Eliminate pulses shorter than 4/fc [s] as noise.
11: Do not eliminate noise. (Note)
PPG1INI
Specify the initial
value of PPG1 output.
0: Low (Positive logic)
1: High (Negative logic)
Select positive or
negative logic.
PPG2INI
Specify the initial
value of PPG2 output.
TRGSEL
Select a trigger start edge.
R/W
0: Low (Positive logic)
1: High (Negative logic)
0: Start on trigger falling edge.
1: Start on trigger rising edge.
TRGAM
0: Always accept trigger edges.
1: Do not accept trigger edges during active output.
Trigger edge acceptance mode
Note: Due to the circuit configuration, a pulse shorter than 1/fc may be eliminated as noise or accepted as a trigger.
Timer/Counter 7 Control Register 2
TC7CR2
(002AH)
7
6
5
4
EMGR
EMGIE
PPG2OE
PPG1OE
3
2
1
CSTC
0
TC7OUT
Select an output waveform mode.
00: PPG1/PPG2 independent output
01: –
10: Output with variable duty ratio
11: Output with 50% duty ratio
CSTC
Select a count start mode.
00: Command start and capture mode
01: Command start and trigger start mode.
10: Trigger start mode
11: -
PPG1OE
Enable/disable PPG1 output.
0: Disable
1: Enable
PPG2OE
Enable/disable PPG2 output.
0: Disable
1: Enable
EMGIE
Enable/disable input on the EMG pin.
0: Disable input.
1: Enable input.
Cancel the emergency output stop state.
0: 1: Cancel the emergency output stop state.
(Upon canceling the state,
this bit is automatically cleared to 0.)
TC7OUT
EMGR
(Initial value: 0000 0000)
R/W
Timer/Counter 7 Control Register 3
TC7CR3
(002BH)
7
6
5
4
3
EMGF
CNTBF
CSIDIS
Page 80
2
1
STM
0
TC7ST
(Initial value: **00 0000)
TMP86PS27FG
TC7ST
0: Stop
1: Start
Start/stop the timer.
TC7ST = 0
STM
Select the state when stopped.
Select continuous or one-time output.
TC7ST = 1
00: Immediately stop and clear the counter with the
output initialized.
Continuous output
01: Immediately stop and clear the counter with the
output maintained.
Continuous output
10: Stop the counter after completing output in the
current period.
One-time output
11: -
–
CSIDIS
Disable the first interrupt at upon a command start.
0: Allow a periodic interrupt (INTTC7P) to occur in the first period upon a
command start.
1: Do not allow a periodic interrupt (INTTC7P) to occur in the first period
upon a command start.
CNTBF
Counting status flag
0: Counting stopped
1: Counting in progress
Emergency output stop flag
0: Operating normally
1: Output stopped in emergency
EMGF
R/W
Read
only
Note 1: The TC7CR1 and TC7CR2 registers should not be rewritten after a timer start (when TC7ST, bit0 of the TC7CR3, is set to
1).
Note 2: Before attempting to modify the TC7CR1 or TC7CR2, clear TC7ST and then check that CNTBF = 0 to determine that the
timer is stopped.
Note 3: The TC7ST bit only causes the timer to start or stop; it does not indicate the current operating state of the counter. Its
value does not change automatically when counting starts or stops
Note 4: In command start and capture mode or command start and trigger start mode, writing 1 to TC7ST causes the timer to
restart immediately. It means that rewriting any bit other than TC7ST in the TC7CR3 after a command start causes the
rewriting of TC7ST, resulting in the timer being restarted (PPG output is started from the initial state). When TC7ST is set
to 1, rewriting the TC7CR3 (Using a bit manipulation or LD instruction) clears the counter and restarts the timer.
Note 5: TC7CR2<EMGR> is always read as 0 even after 1 is written.
Note 6: Data registers are not updated by merely modifying the output mode with TC7CR2<TC7OUT>. After modifying the output
mode, reconfigure data registers TC7DRA to TC7DRE. Ensure that the data registers are written in an appropriate order
because they are not enabled until the upper byte of the TC7DRC is written.
Dead Time 1 Setup Register
15
14
13
12
11
10
9
8
7
6
5
TC7DRAH
(0009H)
TC7DRA
4
3
2
1
0
2
1
0
2
1
0
TC7DRAL
(0008H)
(0009H, 0008H) Read/Write (Initial value: **** **00 0000 0000)
Pulse Width 1 Setup Register
15
14
13
12
11
10
9
8
7
6
5
TC7DRBH
(000BH)
TC7DRB
4
3
TC7DRBL
(000AH)
(000BH, 000AH) Read/Write (Initial value: **** **00 0000 0000)
Period Setup Register
15
14
13
12
11
10
9
8
TC7DRCH
(000DH)
TC7DRC
(000DH, 000CH) Read/Write (Initial value: **** **00 0000 0000)
Page 81
7
6
5
4
3
TC7DRCL
(000CH)
8. 10-Bit Timer/Counter (TC7)
8.2 Control
TMP86PS27FG
Dead Time 2 Setup Register
15
14
13
12
11
10
9
8
7
6
5
TC7DRDH
(0FB1H)
TC7DRD
4
3
2
1
0
2
1
0
TC7DRDL
(0FB0H)
(0FB1H, 0FB0H) Read/Write (Initial value: **** **00 0000 0000)
Pulse Width 2 Setup Register
15
14
13
12
11
10
9
8
7
6
5
TC7DREH
(0FB3H)
TC7DRE
4
3
TC7DREL
(0FB2H)
(0FB3H, 0FB2H) Read/Write (Initial value: **** **00 0000 0000)
Note 1: Data registers TC7DRA to TC7DRE have double-stage configuration, consisting of a data register that stores data written
by an instruction and a compare register to be compared with the counter.
Note 2: When writing data to data registers TC7DRA to TC7DRE, first write the lower byte and then the upper byte.
Note 3: Unused bits (Bits 10 to 15) in the upper bytes of data registers TC7DRA to TC7DRE are not assigned specific register
functions. These bits are always read as 0 even when a 1 is written.
Note 4: Values read from data registers TC7DRA to TC7DRE may differ from the actual PPG output waveforms due to their double-stage configuration.
Note 5: Data registers are not updated by merely modifying the output mode with TC7CR2<TC7OUT>. After modifying the output
mode, reconfigure data registers TC7DRA to TC7DRE. Ensure that the data registers are written in an appropriate order
because they are not enabled until the upper byte of the TC7DRC is written.
Rising-edge Capture Value Register
15
14
13
12
11
10
9
8
7
6
5
TC7CAPAH
(0FB5H)
TC7CAPA
4
3
2
1
0
2
1
0
TC7CAPAL
(0FB4H)
(0FB5H, 0FB4H) Read only (Initial value: 0000 00** **** ****)
Falling-edge Capture Value Register
15
14
13
12
11
10
TC7CAPB
9
8
7
TC7CAPBH
(0FB7H)
6
5
4
3
TC7CAPBL
(0FB6H)
(0FB7H, 0FB6H) Read only (Initial value: 0000 00** **** ****)
Note 1: Capture registers (TC7CAPA and TC7CAPB) must be read in the following order: Lower byte of the TC7CAPA, upper byte
of the TC7CAPA, lower byte of the TC7CAPB, upper byte of the TC7CAPB.
Note 2: The next captured data is not updated by reading the TC7CAPA only. The TC7CAPB must also be read.
Note 3: It is possible to read the TC7CAPB only. Read the lower byte first.
Note 4: If a capture edge is not detected within a period, the previous capture value is maintained in the next period.
Note 5: If more than one capture edge is detected within a period, the capture value for the edge detected last is valid in the next
period.
Note 6: Bits 10 to 15 of the TC7CAPA and TC7CAPB are always read as 0.
Page 82
TMP86PS27FG
8.3 Configuring Control and Data Registers
Configure control and data registers in the following order:
1. Configure mode settings: TC7CR1, TC7CR2
2. Configure data registers (Dead time, pulse width):
TC7DRA, TC7DRB, TC7DRD, TC7DRE (only those required for selected mode)
3. Configure data registers (Period): TC7DRC
4. Configure timer start/stop:TC7CR3
• Data registers have double-stage configuration, consisting of a data register that stores data written by
an instruction and a compare register to be compared with the counter.
• Data stored in a data register is processed according to the output mode specified in the TC7OUT,
transferred to the compare register, and then used for comparison with the up counter.
• Data registers required for the specified output mode are used for data register processing and transfer
to the compare register. Ensure that the output mode is specified in the TC7OUT (Bits 0 and 1 of the
TC7CR2) before configuring data registers.
• Writing data to the upper byte of the TC7DRC causes a data transfer request to be issued for data in
data registers TC7DRA to TC7DRE. If a counter match or clear occurs while that request is valid, the
data is transferred to the compare register and becomes valid for comparison.
• If a data register is written more than once within a period, the data in the data register that was set
when the upper byte of the TC7DRC was written is valid as data for the next period. The data in the
data register written last in the first period will be valid for the period that follows the next period.
Execute write
instruction.
Execute write
instruction.
A1
B1
C1
TC7DRA
TC7DRB
TC7DRC
A2
B2
C2
Period (2)
Period (3)
Period (4)
Previous data is
maintained if data is not
rewritten within the period.
Execute more than one
data write instruction.
A1
B1
C1
A2
Data valid
in each
period
A1
B1
C1
TC7DRA
TC7DRB
TC7DRC
A3
B3
C3
Period (1)
Valid in next
period
Execute write
instruction.
Execute write
instruction.
C2
C3
B2
C4
Execute write instruction.
A3
A4
A5
C5
C6
C7
A2
B1
C2
Period (1)
If data is rewritten more
than once within a
period, the data written
first is valid in the next
period.
No data write
Execute write instruction.
A6
B3
C8
A3
B2
C5
Period (2)
A7
B4
C9
A5
B2
C7
Period (3)
Period (4)
If data is rewritten more than
once within a period, the data
written last is valid in the
period following the next
period.
Figure 8-2 Example Configuration of Control/data Registers (1)
Page 83
A6
B3
C8
Period (5)
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
More than one data write
TC7DRA
TC7DRB
TC7DRC
A1
B1
C1
Data valid
in each
period
a1
b1
c1
A2
B2
C2
No data write
A3
B3
More than one data write
C3
A1
B1
C1
A1
B1
C1
A3
B3
C3
Period (1)
Period (2)
A2
B2
C2
A3
B3
C3
A4
B4
C3
A1
B1
C1
Period (3)
Period (4)
A3
B3
C3
Period (5)
A4
B4
C3
Period (6)
If TC7DRC is written in
the next period
Figure 8-3 Example Configuration of Control/data Registers (2)
8.4 Features
8.4.1
Programmable pulse generator output (PPG output)
The PPG1 and PPG2 pins provide PPG outputs. The output waveform mode for PPG outputs is specified
with TC7CR2<TC7OUT> and their waveforms are controlled by comparing the contents of the 10-bit up
counter with the data set in data registers (TC7DRA to TC7DRE). Three output waveform modes are available:
50% duty mode, variable duty mode, and PPG1/PPG2 independent mode.
8.4.1.1
50% duty mode
(1)
Description
With a period specified in the TC7DRC, the PPG1 and PPG2 pins provide waveforms having a
pulse width (Active duration) that equals a half the period.
The PPG1 output is active at the beginning of a period and becomes inactive at half the period. The
PPG2 output is inactive at the beginning of a period, becomes active at half the period, and remains
active until the end of the period.
If a dead time is specified in the TC7DRA, the pulse width (Active duration) is shortened by the
dead time.
(2)
Register settings
TC7OUT = “11”, TC7DRA = “dead time”, TC7DRC = “period”
(3)
Valid range for data register values
(a) Period:
002H ≤ TC7DRC ≤ 400H (Writing 400H to TC7DRC results in 000H being read from it.)
Page 84
TMP86PS27FG
When the value set in the TC7DRC is an odd number, the PPG2 pulse width is one count
longer than the PPG1 pulse width.
(b) Dead time TC7DRA:
000H ≤ TC7DRA < TC7DRC/2
To specify no dead time, set the TC7DRA to 000H.
Source clock
S, 0
Counter
1
M
S/2
S/2+1
S, 0
S/2+M
1
2
Dead time
M
M'
Period
S
S
PPG1 output
M: Dead time
3
Active duration
M: Dead time
PPG2 output
Active duration
S: Period
INTTC7T
INTTC7P
Dead time
(TC7DRA)
Dead time
(TC7DRA)
Pulse width (TC7DRC/2)
Pulse width (TC7DRC/2)
Period (TC7DRC)
Figure 8-4 Example operation in 50% duty mode:
Command and capture start, positive logic, continuous output
8.4.1.2
Variable duty mode
(1)
Description
With a period specified in the TC7DRC and a pulse width in the TC7DRB, the PPG1 pin provides
a waveform having the specified pulse width while the PPG2 pin provides a waveform having a
pulse width that equals (TC7DRC – TC7DRB).
The PPG1 output is active at the beginning of a period, remains active during the pulse width specified in the TC7DRB, after which it is inactive until the end of the period. The PPG2 output is inactive at the beginning of a period, remains inactive during the pulse width specified in the TC7DRB,
after which it is active until the end of the period, that is, during the pulse width of (TC7DRC –
TC7DRB).
If a dead time is specified in the TC7DRA, the pulse width (Active duration) is shortened by the
dead time.
(2)
Register settings
TC7OUT = “10”, TC7DRA = “dead time”, TC7DRB = “pulse width”, TC7DRC = “period”
Page 85
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
(3)
Valid range for data register values
(a) Period:
002H ≤ TC7DRB + TC7DRA < TC7DRC ≤ 400H
(Writing 400H to TC7DRC results in 000H being read from it.)
(b) Pulse width:
001H ≤ TC7DRB < TC7DRC
(c) Dead time:
000H ≤ TC7DRA < TC7DRB, 000H ≤ TC7DRA < (TC7DRC – TC7DRB)
(To specify no dead time, set the TC7DRA to 000H.)
Source clock
S, 0
Counter
1
M
N N+1
S, 0
N+M
1
2
Dead time
M
M'
Pulse width
N
N'
Period
S
S
PPG1 output
3
M: Dead time
Active duration
N: Pulse width
PPG2 output
M: Dead time
Active duration
S: Period
INTTC7T
INTTC7P
Dead time
(TC7DRA)
Dead time
(TC7DRA)
Pulse width (TC7DRC − TC7DRB)
Pulse width (TC7DRB)
Period (TC7DRC)
Figure 8-5 Example Operation in Variable Duty Mode:
Command and Capture Start, Positive Logic, Continuous Output
8.4.1.3
PPG1/PPG2 independent mode
(1)
Description
For the PPG1 output, specify the dead time in the TC7DRA and pulse width in the TC7DRB. For
the PPG2 output, specify the dead time in the TC7DRD and pulse width in the TC7DRE. With a
common period specified in the TC7DRC, the PPG1 and PPG2 pins provide waveforms having the
specified pulse widths.
Page 86
TMP86PS27FG
The PPG1 output is active at the beginning of a period, remains active during the pulse width specified in the TC7DRB, after which it is inactive until the end of the period.
The PPG2 output is active at the beginning of a period, remains active during the pulse width specified in the TC7DRE, after which it is inactive until the end of the period.
If a dead time is specified in the TC7DRA for the PPG1 output or in the TC7DRD for the PPG2
output, the pulse width (Active duration) is shortened by the dead time.
(2)
Register settings
TC7OUT = “00”, TC7DRC = “period”
TC7DRA = “PPG1 dead time”, TC7DRB = “PPG1 pulse width”
TC7DRD = “PPG2 dead time”, TC7DRE = “PPG2 pulse width”
(3)
Valid range for data register values
(a) Period:
002H ≤ TC7DRC ≤ 400H
(Writing 400H to TC7DRC results in 000H being read from it.)
(b) Pulse width:
001H ≤ TC7DRB ≤ 400H
(Writing 400H to TC7DRB results in 000H being read from it.)
001H ≤ TC7DRE ≤ 400H
(Writing 400H to TC7DRE results in 000H being read from it.)
(c) Dead time:
000H ≤ TC7DRA ≤ 3FFH, where TC7DRA < TC7DRB ≤ TC7DRC
000H ≤ TC7DRD ≤ 3FFH, where TC7DRD < TC7DRE ≤ TC7DRC
(To specify no dead time, write 000H.)
• Settings for a duty ratio of 0%
002H ≤ TC7DRC ≤ TC7DRA ≤ 3FFH (PPG1 output)
002H ≤ TC7DRC ≤ TC7DRD ≤ 3FFH (PPG2 output)
• Settings for a duty ratio greater than 0%, up to 100%
000H ≤ TC7DRA < TC7DRB ≤ TC7DRC ≤ 400H (PPG1 output)
000H ≤ TC7DRD < TC7DRE ≤ TC7DRC ≤ 400H (PPG2 output)
Period
Period
0% duty
100% duty
Page 87
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
Source clock
0
Counter
1
M
N
T
U
S, 0
1
2
Dead time
M
M'
Pulse width
N
N'
Period
S
S
Dead time
T
T'
Pulse width
U
U'
PPG1 output
M: Dead time
3
Active duration
N: Pulse width
PPG2 output
T: Dead time
Active duration
U: Pulse width
INTTC7T
S: Period
INTTC7P
PPG1 dead time
(TC7DRA)
PPG1 pulse width (TC7DRB)
PPG2 dead time (TC7DRD)
PPG2 pulse width (TC7DRE)
Period (TC7DRC)
Figure 8-6 Example Operation in PPG1/PPG2 Independent Mode:
Command and Capture Start, Positive Logic, Continuous Output
8.4.2
Starting a count
A count can be started by using a command or TC7 pin input.
8.4.2.1
Command start and capture mode
(1)
Description
Writing a 1 to TC7ST causes the current count to be cleared and the counter to start counting. Once
the count has reached a specified period, the counter is cleared. The counter subsequently restarts
counting if STM specifies continuous mode; it stops counting if STM specifies one-time mode.
Writing a 1 to TC7ST before the count reaches a period causes the counter to be cleared, after
which it operates as specified with STM.
The count values at the rising and falling edges on the TC7 pin can be stored in capture registers
(Details for the capture are given in a separate section).
Page 88
TMP86PS27FG
(2)
Register settings
CSTC = “00”: Command start and capture mode
STM: Continuous/one-time output
TC7ST = “1”: Starts counting
PPG1
Count start
(Command)
Count cleared
Start
Count cleared
Start
Count cleared
Restart
TC7ST = 1
PPG output with a
period specified
with TC7DRC
PPG output with a
period specified
with TC7DRC
PPG output with a
period specified
with TC7DRC
Figure 8-7 Example Operation in Command Start and Capture Mode
8.4.2.2
Command start and trigger start mode
(1)
Description
Writing a 1 to TC7ST causes the current count to be cleared and the counter to start counting. The
operation is the same as that in command start and capture mode if there is no trigger input on the
TC7 pin. If an edge specified with the start edge selection field (TRGSEL) appears on the TC7 pin,
however, the timer starts counting. The counter is cleared and stopped while the TC7 pin is driven to
the specified clear/stop level. If the TC7 pin is at the clear/stop level when a count start command is
issued (1 is written to TC7ST), counting does not start (INTTC7P does not occur) until a trigger start
edge appears, causing INTTC7T to occur (A trigger input takes precedence over a command start).
Note: For more information on the acceptance of a trigger, see 8.4.2.5 “Trigger start/stop acceptance
mode”.
(2)
Register settings
CSTC = “01”: Command start and trigger start mode
STM: Continuous/one-time output
TC7ST = “1”: Starts counting
TRGSEL: Trigger selection
Count stopped
Period (TC7DRC)
TC7 input
(Signal after
noise elimination)
PPG1
Count start
(Command)
PPG output with a period
When TRGSEL = 0
(Start on falling edge) specified with TC7DRC if
there is no trigger
Count cleared
Start
Count
cleared
Count stops with a
trigger (High level).
Count
start
Count starts with a
trigger (Falling edge).
Figure 8-8 Example Operation in Command Start and Trigger Start Mode
Page 89
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
8.4.2.3
Trigger start mode
(1)
Description
If an edge specified with the start edge selection field (TRGSEL) appears on the TC7 pin, the timer
starts counting. The counter is cleared and stopped while the TC7 pin is driven to the specified clear/
stop level.
In trigger start mode, writing a 1 to TC7ST is ignored and does not initialize the PPG output.
Note: For more information on the acceptance of a trigger, see 8.4.2.5 “Trigger start/stop acceptance
mode”.
(2)
Register settings
CSTC = “10”: Trigger start mode
STM: Continuous/one-time output
TC7ST = “1”: Starts waiting for a trigger on the TC7 pin
TRGSEL: Trigger selection
TC7 input
(Signal after
noise elimination)
Count
stopped
Count
stopped
PPG1 output
(Example)
Command set
Count
start
Count
cleared
Count
start
Count
cleared
After a command is
set, counting does not
start until a specified
trigger appears.
TC7 input
(Signal after
noise elimination)
Count
stopped
PPG1 output
(Example)
Command set
Count
start
Count
cleared
Count
start
After a command is
set, counting does not
start until a specified
trigger appears.
Figure 8-9 Example Operation in Trigger Start Mode
8.4.2.4
Trigger capture mode (CSTC = 00)
(1)
Description
When counting starts in command start and capture mode, the count values at the rising and falling
edges of the TC7 pin input are captured and stored in capture registers TC7CAPA and TC7CAPB,
respectively.
Page 90
TMP86PS27FG
The captured data is first stored in the capture buffer. At the end of the period, the data is transferred from the capture buffer to the capture register. If a trigger input does not appear within a
period, the data captured in the previous period remains in the capture buffer and is transferred to the
capture register at the end of the period. If more than one trigger edge is detected within a period, the
data captured last is written to the capture register.
Captured data must be read in the following order: Lower byte of capture register A (TC7CAPAL),
upper byte of capture register A (TC7CAPAH), lower byte of capture register B (TC7CAPBL), and
upper byte of capture register B (TC7CAPBH). Note that reading only the rising-edge captured data
(TC7CAPA) does not update the next captured data. The falling-edge captured data (TC7CAPB)
must also be read.
An attempt to read a captured value from a register other than the upper byte of the TC7CAPB
causes the capture registers to enter protected state, in which captured data cannot be updated. Reading a value from the upper byte of the TC7CAPB cancels that state, re-enabling the updating of captured data (The TC7CAPA and TC7CAPB are read as a single set of operation).
Note that the protected state may be still effective immediately after the counter starts. Ensure that
a dummy read of capture registers is performed in the first period to cancel the protected state.
The capture feature of the TC7 assumes that a capture trigger (Rising or falling edge) appears
within a period. Captured data is updated (An edge is detected) only when the timer is operating
(TC7ST = 1). If a timer stop command (TC7ST = 0) is written within a period, captured data will be
undefined. Captured data is not updated after a one-time stop command is written. In one-time stop
mode, no trigger is accepted after a STOP command is given.
(2)
Register settings
CSTC = “00”: Command start and capture mode
STM: Continuous/one-time output
TC7ST = “1”: Starts counting
Page 91
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
1 period
Rising edge
1 period
Falling edge
Rising edge
Falling edge
TC7 input
(Signal after
noise elimination)
a
b
c
a
d
c
Capture
buffers
b
d
x
a
c
y
b
d
Capture
registers
Captured values read
(Data read skipped)
Captured values read
(c and d read)
Captured values read
(a and b read)
1 period
1 period
1 period
1 period
a1
b1
a2
TC7 input
(Signal after
noise elimination)
a
b
c
a
d
c
c1
a1
c2
c1
c2
Capture
buffers
b
d
b1
a2
x
c
a1
c1
c2
y
d
d
b1
a2
Capture
registers
Captured values read
(Data read skipped)
Captured values read
(c and d read)
Started reading
other than upper
CAPB in this
period
Captured values read
(a1 and d read)
Figure 8-10 Example Operation in Trigger Capture Mode
8.4.2.5
Trigger start/stop acceptance mode
(1)
Selecting an input signal logic for the TC7 pin (Trigger input)
The logic for an input trigger signal on the TC7 pin can be specified using TC7CR1<TRGSEL> .
• TRGSEL = 0:
Counting starts on the falling edge. The counter is cleared and stopped while the TC7 pin is
high.
• TRGSEL = 1:
Counting starts on the rising edge. The counter is cleared and stopped while the TC7 pin is
low.
Page 92
TMP86PS27FG
TRGSEL = 0
TRGSEL = 1
Counter
operating
Counter
operating
Counter
operating
Counter
stopped
TC7 pin input
Counter
operating
Counter
stopped
TC7 pin input
Count
started
Count
cleared
Count
started
Count
started
Count
cleared
Count
started
Figure 8-11 Trigger Input Signal
When TRGSEL is set to 0 to select a falling-edge trigger, a falling edge detected on the TC7 pin
causes the counter to start counting and a high level on the TC7 pin causes the counter to be cleared
and the PPG output to be initialized. The counter is stopped while the TC7 pin input is high.
When TRGSEL is set to 1 to select a rising-edge trigger, a rising edge detected on the TC7 pin
causes the counter to start counting and a low level on the TC7 pin causes the counter to be cleared
and the PPG output to be initialized. The counter is stopped while the TC7 pin input is low.
In one-time stop mode, the counter accepts a stop trigger but does not accept a start trigger (when a
stop trigger is accepted within a period, the output is immediately initialized and the counter is
stopped).
Counter stopped
TC7 pin input
PPG output
Counting stop mode
with the outputs at
the end of the period
Initial value
One-time
mode
Count
cleared
All triggers (Start and stop) are ignored when the timer is stopped (TC7ST = 0).
(2)
Specifying whether triggers are always accepted or ignored when PPG outputs are
active
The TC7CR1<TRGAM> specifies whether triggers from the TC7 pin are always accepted or
ignored when the PPG output is active.
• TRGAM = 0:
Triggers from the TC7 pin are always accepted regardless of whether PPG1 and PPG2 outputs are active or inactive. A trigger starts or clears/stops the timer and deactivates PPG1 and
PPG2 outputs.
• TRGAM = 1:
Triggers from the TC7 pin are accepted only when PPG1 and PPG2 outputs are inactive. A
trigger starts or clears/stops the timer. Triggers are ignored when PPG1 and PPG2 outputs are
active.
The active/inactive state of the PPG1 or PPG2 pin has meaning only when output on the pin is
enabled with PPG1OE or PPG2OE.
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8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
TC7 pin input
PPG1 output
(Positive logic)
PPG2 output
(Positive logic)
INTTC7T
INTTC7P
Counter
operating
Count
started
Counter
operating
Counter
stopped
Count
cleared
Count
started
Counter
stopped
Count
cleared
Counter Counter
operating stopped
Count
started
Count
cleared
Count
started
Counter
operating
End of
a period
Figure 8-12 Start and Clear/stop Triggers on the TC7 Pin:
Falling-edge Trigger (Counting stopped at high level), Triggers Always Accepted
(3)
Ignoring triggers when PPG outputs are active
Setting TRGAM to 1 specifies that triggers are ignored when PPG outputs are active; trigger edges
detected when PPG1 and PPG2 outputs are inactive are accepted and cause the counter to be cleared
and stopped. If a trigger is detected when PPG1 and PPG2 outputs are active, the counter does not
stop immediately but continues counting until the outputs become inactive. If the trigger signal level
is a stop level when the outputs become inactive, the counter is cleared/stopped and waits for a next
start trigger. If output is enabled for both PPG1 and PPG2, triggers are accepted only when both
PPG1 and PPG2 outputs are inactive.
Triggers not accepted
TC7 pin input
(Signal after
noise elimination)
IGBT1
(Positive logic)
IGBT2
(Positive logic)
INTTC7
INTTCR
Counter
operating
A trigger detected when
PPG1 and PPG2 are
inactive causes the
counter to stop or start.
Counter
stopped
Counter
operating
A trigger detected when
PPG1 or PPG2 is active
does not cause the
counter to stop.
Counter
stopped
Counter
operating
A high level of the trigger
input causes the counter
to stop when PPG1 and
PPG2 become inactive.
A trigger detected when
PPG1 or PPG2 is active
does not cause the
counter to stop or restart.
Figure 8-13 Start Triggers on the TC7 Pin:
Falling-edge Trigger (Counting stopped at high level), Triggers Ignored when PPG Outputs
are Active
Page 94
TMP86PS27FG
8.4.3
Configuring how the timer stops
Setting TC7ST to 0 causes the timer to stop with the specified output state according to the setting of STM.
8.4.3.1
Counting stopped with the outputs initialized
When STM is set to 00, the counter stops immediately with the PPG1 and PPG2 outputs initialized to
the values specified with PPG1INI and PPG2INI.
8.4.3.2
Counting stopped with the outputs maintained
When STM is set to 01, the counter stops immediately with the current PPG1 and PPG2 output states
maintained.
To restart the counter from the maintained state (STM = 01), set TC7ST to 1. The counter is restarted with
the initial output values, specified with PPG1INI and PPG2INI.
8.4.3.3
Counting stopped with the outputs initialized at the end of the period
When STM is set to 10, the counter continues counting until the end of the current period and then
stops. If a stop trigger is detected before the end of the period, however, the counter stops immediately.
TC7CR1 and TC7CR2 must not be rewritten before the counter stops completely.
The CNTBF flag (TC7CR3<CNTBF>) can be read to determine whether the counter has stopped.
8.4.4
One-time/continuous output mode
8.4.4.1
One-time output mode
Starting the timer (TC7ST = 1) with STM set to 10 specifies one-time output mode. In this mode, the
timer stops counting at the end of a period.
For a trigger start, the counter is stopped until a trigger is detected. A specified trigger restarts counting
and the counter stops at the end of the period or when a stop trigger is detected, after which it waits for a
trigger again.
For a command start, the counter is stopped until TC7ST is reset to 1.
TC7CR1 and TC7CR2 must not be rewritten before the counter stops completely.
The CNTBF flag (TC7CR3<CNTBF>) can be read to determine whether the counter has stopped.
TC7ST remains set to 1 after the counter is stopped.
When TC7ST is set to 1, setting STM to 10 clears the counter, which then restarts counting from the
beginning in one-time output mode.
8.4.4.2
Continuous output mode
Starting the timer (TC7ST = 1) with STM set to 00 or 01 specifies continuous output mode. In this
mode, the timer outputs specified waveforms continuously.
Page 95
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
PPG1
(Positive logic)
PPG1INI = 0
PPG2
(Negative logic)
PPG1INI = 1
The counter is forcibly
stopped and cleared,
with the outputs initialized.
Output enabled
Count started
PPG1E/PPG2E = 1 TC7ST = 1
STM = 00
STOP command
TC7ST = 0
Figure 8-14 Immediately Stopping and Clearing the Counter with the Outputs Initialized
(STM = 00)
PPG1
(Positive logic)
PPG1INI = 0
PPG2
(Negative logic)
PPG1INI = 1
Output enabled
Count started
PPG1E/PPG2E = 1 TC7ST = 1
STM = 01
STOP command
TC7ST = 0
The counter is forcibly
stopped and cleared,
with the outputs maintained.
Figure 8-15 Immediately Stopping and Clearing the Counter with the Outputs Maintained
(STM = 01)
1 period
1 period
PPG1
(Positive logic)
PPG1INI = 0
PPG2
(Negative logic)
PPG1INI = 1
After a stop command is executed,
the counter continues counting until
the end of the period.
It stops at the end of the period.
Output enabled
Count started
PPG1E/PPG2E = 1 TC7ST = 1
STM = 00 or 01
STOP command Count
TC7ST = 0
stopped
STM = 10
Figure 8-16 Stopping the Counter at the End of the Period (STM = 10)
1 period
PPG1
(Positive logic)
PPG1INI = 0
PPG2
(Negative logic)
PPG1INI = 1
The counter stops at the end of the period
and then waits for a command start or a start trigger.
Output enabled
PPG1E/PPG2E = 1
Count started
TC7ST = 1
STM = 10
Count stopped
at the end of the period
Figure 8-17 Stopping the Counter at the End of the Period (STM = 10): TC7ST = 1, One-time
Output Mode
Page 96
TMP86PS27FG
8.4.5
PPG output control (Initial value/output logic, enabling/disabling output)
8.4.5.1
Specifying initial values and output logic for PPG outputs
The PPG1INI and PPG2INI bits (TC7CR1<PPG1INI> and TC7CR1<PPG2INI>) specify the initial values of PPG1 and PPG2 outputs as well as their output logic.
(1)
Positive logic output
Setting the bit to 0 specifies that the output is initially low and driven high upon a match between
the counter value and specified dead time.
(2)
Negative logic output
Setting the bit to 1 specifies that the output is initially high and driven low upon a match between
the counter value and specified dead time.
8.4.5.2
Enabling or disabling PPG outputs
The PPG1OE and PPG2OE bits (TC7CR2<PPG1OE> and TC7CR2<PPG2OE>) specify whether PPG
outputs are enabled or disabled. When outputs are disabled, no PPG waveforms appear while the counter
is operating, allowing the PPG1 and PPG2 pins to be used as normal input/output pins.
The states of the pins when outputs are disabled depend on the settings in port registers.
8.4.5.3
Using the TC7 as a normal timer/counter
The TC7 can be used as a normal timer/counter when PPG outputs are disabled using PPG1E and
PPG2E. In that case, use an INTTC7P interrupt, which occurs upon a match with the value specified in the
data register (TC7DRC). To start the counter, use start control (TC7S) in command start and capture
mode.
Start
Source clock
0
Counter
TC7DRC
INTTC7P
1
2
3
4
N/0
1
2
3
4
5
6
7
n
Match detected
Figure 8-18 Using the TC7 as a Normal Timer/Counter
8.4.6
Eliminating noise from the TC7 pin input
A digital noise canceller eliminates noise from the input signal on the TC7 pin.
The digital noise canceller uses a sampling clock of fc/4, fc/2 or fc, as specified with NCRSEL, and samples
the signal five times. It accepts a level input which is continuous at least over the period of time required for
five samplings. Any level input which does not continue over the period of time required for five samplings is
canceled as noise.
Page 97
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
Table 8-1 Noise Canceller Settings
NCRSEL
Sampling Frequency
(Number of Samplings)
00
fc/4 (5)
01
Pulse Width Always Assumed as Noise
Pulse Width Always Assumed as Signal
At 8 MHz
At 16 MHz
16/fc [s]
2 [ms]
1 [ms]
20/fc [s]
2.5 [ms]
1.25 [ms]
fc/2 (5)
8/fc [s]
1 [ms]
500 [ns]
10/fc [s]
1.25 [ms]
0.625 [ms]
10
fc (5)
4/fc [s]
0.5 [ms]
250 [ns]
5/fc [s]
0.625 [ms]
0.3125 [ms]
11
(None)
None
–
–
(1/fc)
TC7 input
B
A
Noise canceller
F/F
Z
At 8 MHz
At 16 MHz
PPG output control
circuit
Edge detection
PPG output
S
fc
fc/4
fc/2
Sampling
clock
A
B
C
fc
Z
NCRSEL = 11
NCRSEL
1 2 3 4 5
1 2 3 4 5
fc
1
2
3
4
5
1
2
3
4
5
fc/2
1
2
3
4
1
2
3
4
5
fc/4
TC7 pin input
(after passing
through F/F)
After
noise
elimination
When NCRSEL = 00
Pulses of 16/fc or shorter are canceled.
When NCRSEL = 01
Pulses of 8/fc or shorter are canceled.
Pulses of 20/fc
or longer are assumed
as a signal.
Pulses of 10/fc or longer are assumed as a signal.
Pulses of 5/fc or longer are assumed as a signal.
When NCRSEL = 10
Pulses of 4/fc or shorter are canceled.
Figure 8-19 Noise Canceller Operation
• When NCRSEL = 00, a TC7 input level after passing through the F/F is always canceled if its duration
is 16/fc [s] or less and always assumed as a signal if its duration is 20/fc [s] or greater. After the input
signal supplied on the TC7 pin passes through the F/F, there is a delay between 21/fc [s] and 24/fc [s]
before the PPG outputs vary.
• When NCRSEL = 01, a TC7 input level after passing through the F/F is always canceled if its duration
is 8/fc [s] or less and always assumed as a signal if its duration is 10/fc [s] or greater. After the input
signal supplied on the TC7 pin passes through the F/F, there is a delay between 13/fc [s] and 14/fc [s]
before the PPG outputs vary.
• When NCRSEL = 10, a TC7 input level after passing through the F/F is always canceled if its duration
is 4/fc [s] or less and always assumed as a signal if its duration is 5/fc [s] or greater. After the input signal supplied on the TC7 pin passes through the F/F, there is a delay of 5/fc [s] before the PPG outputs
vary.
• When NCRSEL = 11, a pulse shorter than 1/fc may be assumed as a signal or canceled as noise in the
first-stage F/F. Ensure that input signal pulses are longer than 1/fc. After the input signal supplied on
the TC7 pin passes through the F/F, there is a delay of 4/fc [s] before the PPG outputs vary.
Page 98
TMP86PS27FG
Note 1: If the pin input level changes while the specified noise elimination threshold is being modified, the noise
canceller may assume noise as a pulse or cancel a pulse as noise.
Note 2: If noise occurs in synchronization with the internal sampling timing consecutively, it may be assumed as a
signal.
Note 3: The signal supplied on the TC7 pin requires 1/fc [s] or less to pass through the F/F.
8.4.7
Interrupts
The TC7 supports three interrupt sources.
8.4.7.1
INTTC7T (Trigger start interrupt)
A trigger interrupt (INTTC7T) occurs when the counter starts upon the detection of a trigger edge specified with TC7CR1<TRGST>. This interrupt does not occur with a trigger edge for clearing the count. A
trigger edge detected in trigger capture mode does not cause an interrupt. A start trigger causes an interrupt even when the counter is stopped in emergency.
1 period
Cleared
TC7 trigger
x
Counter
Count started
0
1
Cleared
2
M-2
M-1
0
1
2
0
1
2
Cleared upon match
TC7DRC
INTTC7T
INTTC7P
PPG output
Figure 8-20 Trigger Start Interrupt
8.4.7.2
INTTC7P (Period interrupt)
A period interrupt (INTTC7P) occurs when the counter starts with a command and when the counter is
cleared with the specified counter period (TC7DRC) reached, that is, at the end of a period. A match with
the set period causes an interrupt even when the counter is stopped in emergency.
Command stop
Stop at the end of period
Command start
Timer stopped
Counter
x
1
2
M-2
M-1
M, 0
1
2
M-2
Clear upon match
TC7DRC
INTTC7T
INTTC7P
PPG output
CSIDIS specifies
whether the first
INTTC7P occurs.
1 period
1 period
Figure 8-21 Period Interrupt
Page 99
M-1
M, 0
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
If a command start is specified (1 is written in TC7ST) when the TC7 pin is at a stop level, the counter
does not start (INTTC7P does not occur); a subsequent trigger start edge causes the counter to start and
INTTC7T to occur.
8.4.7.3
INTEMG (Emergency output stop interrupt)
An emergency output stop interrupt (INTEMG) occurs when the emergency output stop circuit operates
to stop PPG outputs in emergency.
8.4.8
Emergency PPG output stop feature
Setting TC7CR2<EMGIE> to 1 enables the emergency PPG output stop feature (Enables the EMG pin
input).
A low level input detected on the EMG pin causes an EMG interrupt (INTEMG) to occur with the PPG waveforms initialized (as specified with PPG1INI and PPG2INI). (Emergency PPG output stop)
This feature only disables PPG outputs without stopping the counter. Use the EMG interrupt handler routine
to stop the timer.
Note:Ensure that a low level on the EMG pin continues for at least 4/fc [s]. The emergency PPG output stop feature
may not operate normally with a low level shorter than 4/fc [s].
EMG interrupt (INTEMG)
Sampling
circuit
EMG
pin
S
Q
F/F
EMGF (Status flag)
R
Port output latch
F/F
PPG1OE
PPG2OE
EMGIE
EMGR
TC7 control register 2
F/F
PPG circuit output
TC7ST
STM
TC7 control register 3
A
B
Z
S
PPG1
PPG2
PPG1INI
PPG1OE
PPG2INI
PPG2OE
TC7 control register 1
Figure 8-22 EMG Pin
8.4.8.1
Enabling/disabling input on the EMG pin
Setting TC7CR2<EMGIE> to 1 enables input on the EMG pin and setting the bit to 0 disables input on
the pin. (Initially, EMGIE is set to 0, disabling an emergency output stop (EMG pin) input.)
The input signal on the EMG pin is valid only when its shared port pin is placed in input mode. Ensure
that the shared port pin is placed in input mode before attempting to enable the EMG pin input.
The EMG pin input is sampled using a high-frequency clock. The emergency PPG output stop feature
does not operate normally if the high-frequency clock is stopped.
8.4.8.2
Monitoring the emergency PPG output stop state
When the emergency PPG output stop feature activates, the TC7CR3<EMGF> is set to 1. 1 read from
EMGF indicates that PPG outputs are disabled by the emergency PPG output stop feature. To restart the
timer in that state, first make necessary settings for stopping the timer before canceling the emergency
PPG output stop state (by writing 1 to EMGR, bit7 of the TC7CR2) and then reconfiguring the control and
data registers to restart the timer.
Page 100
TMP86PS27FG
8.4.8.3
EMG interrupt
An EMG interrupt (INTEMG) occurs when an emergency PPG output stop input is accepted. To use an
INTEMG interrupt for some processing, ensure that the interrupt is enabled beforehand.
When the EMG pin is low with EMGIE set to 1 (EMG pin input enabled), an attempt to cancel the emergency PPG output stop state results in an interrupt being generated again, with the emergency PPG output
stop state reestablished.
An INTEMG interrupt occurs whenever a stop input is accepted when EMGIE = 1, regardless of
whether the timer is operating.
8.4.8.4
Canceling the emergency PPG output stop state
To cancel the emergency PPG output stop state, ensure that the input on the EMG pin is high, set
TC7CR3<TC7ST> to 0 and TC7CR3<STM> to 00 to stop the timer, and then set TC7CR2<EMGR> to 1.
Setting EMGR to 1 cancels the stop state only when TC7ST = 0 and STM = 00; ensure that TC7ST = 0
and STM = 00 before setting EMGR to 1.
If the input on the EMG pin is low and EMGIE = 1 when the emergency PPG output stop state is canceled, the timer re-enters the emergency PPG output stop state and an INTEMG interrupt occurs.
8.4.8.5
Restarting the timer after canceling the emergency PPG output stop state
To restart the timer after canceling the emergency PPG output stop state, reconfigure the control registers (TC7CR1, TC7CR2, TC7CR3) before restarting the timer.
The timer cannot restart in the emergency PPG output stop state. Monitor the emergency PPG output
stop state and cancel the state before reconfiguring the control registers to restart the timer. Ensure that the
control registers are reconfigured according to the appropriate procedure for configuring timer operation
control.
8.4.8.6
Response time between EMG pin input and PPG outputs being initialized
The time between a low level input being detected on the EMG pin and the PPG outputs being initialized
is up to 10/fc [s].
Page 101
8. 10-Bit Timer/Counter (TC7)
8.4 Features
TMP86PS27FG
Emergency stop
input
PPG pin output
EMG pin input
EMGIE
10/fc [s]
1.25 µs (at 8 MHz)
Output initialized
forcibly
Initial output state
Share port
in input mode
Emergency stop input
EMGR = 1,
protection feature
enabled
EMGF
(State monitor)
EMGR = 1,
cancel emergency output stop state
EMGF = 1,
emergency output
stop state
INTEMG
(EMG interrupt)
EMG interrupt
TC7ST
TC7ST = 1,
timer operating
STM
STM = 01,
timer operating
(Continuous mode)
TG7ST = 0
Specified with
an instruction
STM = 00
Emergency output
stop state
Figure 8-23 Timing between EMG Pin Input being Detected and PPG Outputs being Disabled
8.4.9
TC7 operation and microcontroller operating mode
The TC7 operates when the microcontroller is placed in NORMAL1, NORMAL2, IDLE1, or IDLE2 mode.
If the mode changes from NORMAL or IDLE to STOP, SLOW, or SLEEP while the TC7 is operating, the TC7
is initialized and stops operating.
To change the microcontroller operating mode from NORMAL or IDLE to STOP, SLOW, or SLEEP, ensure
that the TC7 timer is stopped before attempting to execute a mode change instruction.
To change the mode from STOP, SLOW, or SLEEP to NORMAL to restart the TC7, reconfigure all registers
according to the appropriate TC7 operation procedure.
Page 102
TMP86PS27FG
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
PWM mode
Overflow
fc/211 or fs/23
7
fc/2
5
fc/2
fc/23
fs
fc/2
fc
TC4 pin
A
B
C
D
E
F
G
H
Y
A
B
INTTC4
interrupt request
Clear
Y
8-bit up-counter
TC4S
S
PDO, PPG mode
A
B
S
16-bit
mode
S
TC4M
TC4S
TFF4
Toggle
Q
Set
Clear
Y
16-bit mode
Timer, Event
Counter mode
S
TC4CK
PDO4/PWM4/
PPG4 pin
Timer F/F4
A
Y
TC4CR
B
TTREG4
PWREG4
PWM, PPG mode
DecodeEN
PDO, PWM,
PPG mode
TFF4
16-bit
mode
TC3S
PWM mode
fc/211 or fs/23
fc/27
5
fc/2
3
fc/2
fs
fc/2
fc
TC3 pin
Y
8-bit up-counter
Overflow
16-bit mode
PDO mode
16-bit mode
Timer,
Event Couter mode
S
TC3M
TC3S
TFF3
INTTC3
interrupt request
Clear
A
B
C
D
E
F
G
H
Toggle
Q
Set
Clear
PDO3/PWM3/
pin
Timer F/F3
TC3CK
TC3CR
PWM mode
TTREG3
PWREG3
DecodeEN
TFF3
Figure 9-1 8-Bit TimerCouter 3, 4
Page 103
PDO, PWM mode
16-bit mode
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86PS27FG
9.2 TimerCounter Control
The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers
(TTREG3, PWREG3).
TimerCounter 3 Timer Register
TTREG3
(001CH)
R/W
7
PWREG3
(001AH)
R/W
7
6
5
4
3
2
1
0
(Initial value: 1111 1111)
6
5
4
3
2
1
0
(Initial value: 1111 1111)
Note 1: Do not change the timer register (TTREG3) setting while the timer is running.
Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while
the timer is running.
TimerCounter 3 Control Register
TC3CR
(0018H)
TFF3
7
TFF3
6
5
4
TC3CK
Time F/F3 control
3
2
TC3S
0:
1:
1
0
TC3M
(Initial value: 0000 0000)
Clear
Set
R/W
NORMAL1/2, IDLE1/2 mode
TC3CK
Operating clock selection [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/211
fs/23
fs/23
001
fc/27
fc/27
–
010
fc/25
fc/25
–
011
fc/23
fc/23
–
100
fs
fs
fs
101
fc/2
fc/2
–
110
fc
fc
fc (Note 8)
111
TC3S
TC3 start control
0:
1:
000:
001:
TC3M
TC3M operating mode select
010:
011:
1**:
R/W
TC3 pin input
Operation stop and counter clear
Operation start
R/W
8-bit timer/event counter mode
8-bit programmable divider output (PDO) mode
8-bit pulse width modulation (PWM) output mode
16-bit mode
(Each mode is selectable with TC4M.)
Reserved
R/W
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz]
Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running.
Note 3: To stop the timer operation (TC3S= 1 → 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 → 1), TC3M, TC3CK and TFF3 can be programmed.
Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR<TC4M>, where TC3M must
be fixed to 011.
Note 5: To use the TimerCounter in the 16-bit mode, select the source clock by programming TC3CK. Set the timer start control
and timer F/F control by programming TC4CR<TC4S> and TC4CR<TFF4>, respectively.
Note 6: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table
9-1 and Table 9-2.
Page 104
TMP86PS27FG
Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93.
Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode.
Page 105
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86PS27FG
The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers
(TTREG4 and PWREG4).
TimerCounter 4 Timer Register
TTREG4
(001DH)
R/W
7
PWREG4
(001BH)
R/W
7
6
5
4
3
2
1
0
(Initial value: 1111 1111)
6
5
4
3
2
1
0
(Initial value: 1111 1111)
Note 1: Do not change the timer register (TTREG4) setting while the timer is running.
Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while
the timer is running.
TimerCounter 4 Control Register
TC4CR
(0019H)
TFF4
7
TFF4
6
5
4
TC4CK
Timer F/F4 control
3
2
TC4S
0:
1:
1
0
TC4M
(Initial value: 0000 0000)
Clear
Set
R/W
NORMAL1/2, IDLE1/2 mode
TC4CK
Operating clock selection [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/211
fs/23
fs/23
001
fc/27
fc/27
–
010
fc/25
fc/25
–
011
fc/2
3
3
–
100
fs
fs
fs
101
fc/2
fc/2
–
110
fc
fc
–
111
TC4S
TC4 start control
0:
1:
000:
001:
010:
TC4M
TC4M operating mode select
011:
100:
101:
110:
111:
fc/2
R/W
TC4 pin input
Operation stop and counter clear
Operation start
R/W
8-bit timer/event counter mode
8-bit programmable divider output (PDO) mode
8-bit pulse width modulation (PWM) output mode
Reserved
16-bit timer/event counter mode
Warm-up counter mode
16-bit pulse width modulation (PWM) output mode
16-bit PPG mode
R/W
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz]
Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running.
Note 3: To stop the timer operation (TC4S= 1 → 0), do not change the TC4M, TC4CK and TFF4 settings.
To start the timer operation (TC4S= 0 → 1), TC4M, TC4CK and TFF4 can be programmed.
Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC4 overflow signal regardless of the
TC3CK setting.
Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR<TC3 M>
must be set to 011.
Page 106
TMP86PS27FG
Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start
control and timer F/F control by programming TC4S and TFF4, respectively.
Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table
9-1 and Table 9-2.
Note 8: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93.
Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes)
Operating mode
fc/211
or
fc/27
fc/25
fc/23
fs
fc/2
fc
TC3
pin input
TC4
pin input
fs/23
8-bit timer
Ο
Ο
Ο
Ο
–
–
–
–
–
8-bit event counter
–
–
–
–
–
–
–
Ο
Ο
8-bit PDO
Ο
Ο
Ο
Ο
–
–
–
–
–
8-bit PWM
Ο
Ο
Ο
Ο
Ο
Ο
Ο
–
–
16-bit timer
Ο
Ο
Ο
Ο
–
–
–
–
–
16-bit event counter
–
–
–
–
–
–
–
Ο
–
Warm-up counter
–
–
–
–
Ο
–
–
–
–
16-bit PWM
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
–
16-bit PPG
Ο
Ο
Ο
Ο
–
–
–
Ο
–
Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC3CK).
Note 2: Ο : Available source clock
Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes)
Operating mode
fc/211
or
fc/27
fc/25
fc/23
fs
fc/2
fc
TC3
pin input
TC4
pin input
fs/23
8-bit timer
Ο
–
–
–
–
–
–
–
–
8-bit event counter
–
–
–
–
–
–
–
Ο
Ο
8-bit PDO
Ο
–
–
–
–
–
–
–
–
8-bit PWM
Ο
–
–
–
Ο
–
–
–
–
16-bit timer
Ο
–
–
–
–
–
–
–
–
16-bit event counter
–
–
–
–
–
–
–
Ο
–
Warm-up counter
–
–
–
–
–
–
Ο
–
–
16-bit PWM
Ο
–
–
–
Ο
–
–
Ο
–
16-bit PPG
Ο
–
–
–
–
–
–
Ο
–
Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC3CK).
Note2: Ο : Available source clock
Page 107
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86PS27FG
Table 9-3 Constraints on Register Values Being Compared
Operating mode
Register Value
8-bit timer/event counter
1≤ (TTREGn) ≤255
8-bit PDO
1≤ (TTREGn) ≤255
8-bit PWM
2≤ (PWREGn) ≤254
16-bit timer/event counter
1≤ (TTREG4, 3) ≤65535
Warm-up counter
256≤ (TTREG4, 3) ≤65535
16-bit PWM
2≤ (PWREG4, 3) ≤65534
16-bit PPG
and
(PWREG4, 3) + 1 < (TTREG4, 3)
1≤ (PWREG4, 3) < (TTREG4, 3) ≤65535
Note: n = 3 to 4
Page 108
TMP86PS27FG
9.3 Function
The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter,
16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
9.3.1
8-Bit Timer Mode (TC3 and 4)
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 3, 4
Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock)
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211 [Hz]
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
32.6 ms
62.3 ms
fc/27
fc/27
–
8 µs
–
2.0 ms
–
fc/25
fc/25
–
2 µs
–
510 µs
–
fc/23
fc/23
–
500 ns
–
127.5 µs
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 µs later
(TimerCounter4, fc = 16.0 MHz)
(TTREG4), 0AH
: Sets the timer register (80 µs÷27/fc = 0AH).
(EIRH). 5
: Enables INTTC4 interrupt.
LD
(TC4CR), 00010000B
: Sets the operating cock to fc/27, and 8-bit timer mode.
LD
(TC4CR), 00011000B
: Starts TC4.
LD
DI
SET
EI
Page 109
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86PS27FG
TC4CR<TC4S>
Internal
Source Clock
1
Counter
TTREG4
?
2
3
n-1
n 0
1
2
n-1
n 0
1
2
0
n
Match detect
Counter clear
INTTC4 interrupt request
Counter clear
Match detect
Figure 9-2 8-Bit Timer Mode Timing Chart (TC4)
9.3.2
8-Bit Event Counter Mode (TC3, 4)
In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24
Hz in the SLOW1/2 or SLEEP1/2 mode.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output
pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
Note 3: j = 3, 4
TC4CR<TC4S>
TC4 pin input
0
Counter
TTREG4
?
1
2
n-1
n 0
1
2
n-1
n 0
1
2
0
n
Match detect
INTTC4 interrupt request
Counter
clear
Match detect
Counter
clear
Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4)
9.3.3
8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)
This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
To use the programmable divider output, set the output latch of the I/O port to 1.
Page 110
TMP86PS27FG
Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz)
Setting port
LD
(TTREG4), 3DH
: 1/1024÷27/fc÷2 = 3DH
LD
(TC4CR), 00010001B
: Sets the operating clock to fc/27, and 8-bit PDO mode.
LD
(TC4CR), 00011001B
: Starts TC4.
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PDOj pin to the high level.
Note 3: j = 3, 4
Page 111
Page 112
?
INTTC4 interrupt request
PDO4 pin
Timer F/F4
TTREG4
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
0
n
1
Match detect
2
n 0
1
Match detect
2
n 0
1
Match detect
2
n 0
1
Match detect
2
n 0
1
2
3
Set F/F
Held at the level when the timer
is stopped
0
Write of "1"
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86PS27FG
Figure 9-4 8-Bit PDO Mode Timing Chart (TC4)
TMP86PS27FG
9.3.4
8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)
This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The
up-counter counts up using the internal clock.
When a match between the up-counter and the PWREGj value is detected, the logic level output from the
timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the
timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The
INTTCj interrupt request is generated at this time.
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be generated. Upon reset, the timer F/Fj is cleared to 0.
(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be
changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the
INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immediately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output,
the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the
reading data of PWREGj is previous value until INTTCj is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse
different from the programmed value until the next INTTCj interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PWMj pin to the high level.
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP
mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWMj pin during the warm-up period time after exiting the STOP mode.
Note 4: j = 3, 4
Table 9-5 PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211 [Hz]
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
32.8 ms
62.5 ms
fc/2
7
–
8 µs
–
2.05 ms
–
fc/2
5
–
2 µs
–
512 µs
–
fc/2
7
fc/2
5
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
fc/23
fc/23
–
500 ns
–
128 µs
–
fs
fs
fs
30.5 µs
30.5 µs
7.81 ms
7.81 ms
fc/2
fc/2
–
125 ns
–
32 µs
–
fc
fc
–
62.5 ns
–
16 µs
–
Page 113
Page 114
?
Shift registar
0
Shift
INTTC4 interrupt request
PWM4 pin
Timer F/F4
?
PWREG4
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
n
n
n
Match detect
1
n
n+1
Shift
FF
0
n
n
n+1
m
One cycle period
Write to PWREG4
Match detect
1
Shift
FF
0
m
m
m+1
p
Write to PWREG4
Match detect
m
1
Shift
FF
0
p
p
Match detect
1
p
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86PS27FG
Figure 9-5 8-Bit PWM Mode Timing Chart (TC4)
TMP86PS27FG
9.3.5
16-Bit Timer Mode (TC3 and 4)
In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer.
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the
timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the upper byte and lower byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Note 3: j = 3, 4
Table 9-6 Source Clock for 16-Bit Timer Mode
Source Clock
Resolution
NORMAL1/2, IDLE1/2 mode
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211
fs/23
fs/23
128 µs
244.14 µs
8.39 s
16 s
fc/27
fc/27
–
8 µs
–
524.3 ms
–
fc/25
fc/25
–
2 µs
–
131.1 ms
–
fc/23
fc/23
–
500 ns
–
32.8 ms
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later
(fc = 16.0 MHz)
(TTREG3), 927CH
: Sets the timer register (300 ms÷27/fc = 927CH).
(EIRH). 5
: Enables INTTC4 interrupt.
LD
(TC3CR), 13H
:Sets the operating cock to fc/27, and 16-bit timer mode
(lower byte).
LD
(TC4CR), 04H
: Sets the 16-bit timer mode (upper byte).
LD
(TC4CR), 0CH
: Starts the timer.
LDW
DI
SET
EI
TC4CR<TC4S>
Internal
source clock
0
Counter
TTREG3
(Lower byte)
TTREG4
(Upper byte)
?
?
INTTC4 interrupt request
1
2
3
mn-1 mn 0
1
2
mn-1 mn 0
1
n
m
Match
detect
Counter
clear
Match
detect
Counter
clear
Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4)
Page 115
2
0
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
9.3.6
TMP86PS27FG
16-Bit Event Counter Mode (TC3 and 4)
In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3
and 4 are cascadable to form a 16-bit event counter.
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after
the timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is
cleared.
After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC3 pin.
Two machine cycles are required for the low- or high-level pulse input to the TC3 pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 in
the SLOW1/2 or SLEEP1/2 mode. Program the lower byte (TTREG3), and upper byte (TTREG4) in this
order in the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in
the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 3, 4
9.3.7
16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)
This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The
TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator.
The counter counts up using the internal clock or external clock.
When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the
logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The
logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the
counter is cleared. The INTTC4 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or
SLEEP1/2 mode.
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
generated. Upon reset, the timer F/F4 is cleared to 0.
(The logic level output from the PWM4 pin is the opposite to the timer F/F4 logic level.)
Since PWREG4 and 3 in the PWM mode are serially connected to the shift register, the values set to
PWREG4 and 3 can be changed while the timer is running. The values set to PWREG4 and 3 during a run of
the timer are shifted by the INTTCj interrupt request and loaded into PWREG4 and 3. While the timer is
stopped, the values are shifted immediately after the programming of PWREG4 and 3. Set the lower byte
(PWREG3) and upper byte (PWREG3) in this order to program PWREG4 and 3. (Programming only the lower
or upper byte of the register should not be attempted.)
If executing the read instruction to PWREG4 and 3 during PWM output, the values set in the shift register is
read, but not the values set in PWREG4 and 3. Therefore, after writing to the PWREG4 and 3, reading data of
PWREG4 and 3 is previous value until INTTC4 is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt
request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and
the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of
pulse different from the programmed value until the next INTTC4 interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is
stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not program
TC4CR<TFF4> upon stopping of the timer.
Example: Fixing thePWM4 pin to the high level when the TimerCounter is stopped
Page 116
TMP86PS27FG
CLR (TC4CR).3: Stops the timer.
CLR (TC4CR).7 : Sets the PWM4 pin to the high level.
Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4
pin during the warm-up period time after exiting the STOP mode.
Table 9-7 16-Bit PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
8.39 s
16 s
fc/27
fc/27
–
8 µs
–
524.3 ms
–
fc/25
fc/25
–
2 µs
–
131.1 ms
–
fc/23
fc/23
–
500ns
–
32.8 ms
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
fs
fs
fs
30.5 µs
30.5 µs
fc/2
fc/2
–
125 ns
–
8.2 ms
–
fc
fc
–
62.5 ns
–
4.1 ms
–
2
s
Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz)
Setting ports
LDW
(PWREG3), 07D0H
: Sets the pulse width.
LD
(TC3CR), 33H
: Sets the operating clock to fc/23, and 16-bit PWM output
mode (lower byte).
LD
(TC4CR), 056H
: Sets TFF4 to the initial value 0, and 16-bit PWM signal
generation mode (upper byte).
LD
(TC4CR), 05EH
: Starts the timer.
Page 117
2s
Page 118
?
?
PWREG4
(Upper byte)
16-bit
shift register
0
a
Shift
INTTC4 interrupt request
PWM4 pin
Timer F/F4
?
PWREG3
(Lower byte)
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
an
n
an
Match detect
1
an
an+1
Shift
FFFF
0
an
an
an+1
m
b
One cycle period
Write to PWREG4
Write to PWREG3
Match detect
1
Shift
FFFF
0
bm
bm bm+1
p
c
Write to PWREG4
Write to PWREG3
Match detect
bm
1
Shift
FFFF
0
cp
Match detect
cp
1
cp
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86PS27FG
Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4)
TMP86PS27FG
9.3.8
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4)
This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode.
The counter counts up using the internal clock or external clock. When a match between the up-counter and
the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is
switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is
switched to the opposite state again when a match between the up-counter and the timer register (TTREG3,
TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or
SLEEP1/2 mode.
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
generated. Upon reset, the timer F/F4 is cleared to 0.
(The logic level output from the PPG4 pin is the opposite to the timer F/F4.)
Set the lower byte and upper byte in this order to program the timer register. (TTREG3 → TTREG4,
PWREG3 → PWREG4) (Programming only the upper or lower byte should not be attempted.)
For PPG output, set the output latch of the I/O port to 1.
Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz)
Setting ports
LDW
(PWREG3), 07D0H
: Sets the pulse width.
LDW
(TTREG3), 8002H
: Sets the cycle period.
LD
(TC3CR), 33H
: Sets the operating clock to fc/23, and16-bit PPG mode
(lower byte).
LD
(TC4CR), 057H
: Sets TFF4 to the initial value 0, and 16-bit
PPG mode (upper byte).
LD
(TC4CR), 05FH
: Starts the timer.
Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since
PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi.
Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not
be obtained.
Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is
stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not change
TC4CR<TFF4> upon stopping of the timer.
Example: Fixing the PPG4 pin to the high level when the TimerCounter is stopped
CLR (TC4CR).3: Stops the timer
CLR (TC4CR).7: Sets the PPG4 pin to the high level
Note 3: i = 3, 4
Page 119
Page 120
?
TTREG4
(Upper byte)
INTTC4 interrupt request
PPG4 pin
Timer F/F4
?
?
TTREG3
(Lower byte)
PWREG4
(Upper byte)
n
PWREG3
(Lower byte)
?
0
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
m
r
q
mn
Match detect
1
mn mn+1
Match detect
qr-1 qr 0
mn
Match detect
1
mn mn+1
Match detect
qr-1 qr 0
mn
Match detect
1
F/F clear
0
Held at the level when the timer
stops
mn mn+1
Write of "0"
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86PS27FG
Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40)
TMP86PS27FG
9.3.9
Warm-Up Counter Mode
In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a
16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to
low-frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the PDOi, PWMi and PPGi pins may output
pulses.
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG4 and 3 are used for match
detection and lower 8 bits are not used.
Note 3: i = 3, 4
9.3.9.1
Low-Frequency Warm-up Counter Mode
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability
is obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock.
When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer
is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt
request. After stopping the timer in the INTTC4 interrupt service routine, set SYSCR2<SYSCK> to 1 to
switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2<XTEN> to
0 to stop the high-frequency clock.
Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
Maximum Time Setting
(TTREG4, 3 = 0100H)
Maximum Time Setting
(TTREG4, 3 = FF00H)
7.81 ms
1.99 s
Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode
SET
(SYSCR2).6
: SYSCR2<XTEN> ← 1
LD
(TC3CR), 43H
: Sets TFF3=0, source clock fs, and 16-bit mode.
LD
(TC4CR), 05H
: Sets TFF4=0, and warm-up counter mode.
LD
(TTREG3), 8000H
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
: IMF ← 0
DI
SET
(EIRH). 5
: IMF ← 1
EI
SET
:
PINTTC4:
: Enables the INTTC4.
(TC4CR).3
: Starts TC4 and 3.
:
CLR
(TC4CR).3
: Stops TC4 and 3.
SET
(SYSCR2).5
: SYSCR2<SYSCK> ← 1
(Switches the system clock to the low-frequency clock.)
CLR
(SYSCR2).7
: SYSCR2<XEN> ← 0 (Stops the high-frequency clock.)
RETI
:
VINTTC4:
DW
:
PINTTC4
: INTTC4 vector table
Page 121
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86PS27FG
9.3.9.2
High-Frequency Warm-Up Counter Mode
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock.
When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer
is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt
request. After stopping the timer in the INTTC4 interrupt service routine, clear SYSCR2<SYSCK> to 0 to
switch the system clock from the low-frequency to high-frequency, and then SYSCR2<XTEN> to 0 to
stop the low-frequency clock.
Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode
Minimum time (TTREG4, 3 = 0100H)
Maximum time (TTREG4, 3 = FF00H)
16 µs
4.08 ms
Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode
SET
(SYSCR2).7
: SYSCR2<XEN> ← 1
LD
(TC3CR), 63H
: Sets TFF3=0, source clock fs, and 16-bit mode.
LD
(TC4CR), 05H
: Sets TFF4=0, and warm-up counter mode.
LD
(TTREG3), 0F800H
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
: IMF ← 0
DI
SET
(EIRH). 5
: Enables the INTTC4.
(TC4CR).3
: Starts the TC4 and 3.
: IMF ← 1
EI
SET
:
PINTTC4:
:
CLR
(TC4CR).3
: Stops the TC4 and 3.
CLR
(SYSCR2).5
: SYSCR2<SYSCK> ← 0
(Switches the system clock to the high-frequency clock.)
CLR
(SYSCR2).6
: SYSCR2<XTEN> ← 0
(Stops the low-frequency clock.)
RETI
VINTTC4:
:
:
DW
PINTTC4
: INTTC4 vector table
Page 122
TMP86PS27FG
10. Real-Time Clock
The TMP86PS27FG include a real time counter (RTC). A low-frequency clock can be used to provide a periodic
interrupt (0.0625[s],0.125[s],0.25[s],0.50[s]) at a programmed interval, implement the clock function. The RTC can
be used in the mode in which the low-frequency oscillator is active (except for the SLEEP0 mode).
10.1 Configuration
RTCCR
Interrupt request
INTRTC
Selector
RTCSEL
RTCRUN
211/fs 212/fs 213/fs 214/fs
fs
(32.768 kHz)
Binary counter
Figure 10-1 Configuration of the RTC
10.2 Control of the RTC
The RTC is controlled by the RTC control register (RTCCR).
RTC Control Register
RTCCR
(002DH)
7
6
5
4
3
2
1
RTCSEL
RTCSEL
RTCRUN
0
RTCRUN
Interrupt generation period
(fs = 32.768 kHz)
00: 0.50 [s]
01: 0.25 [s]
10: 0.125 [s]
11: 0.0625 [s]
RTC control
0: Stops and clears the binary counter.
1: Starts counting
(Initial value: **** *000)
R/W
Note 1: Program the RTCCR during low-frequency oscillation (when SYSCR2<XTEN> = “1”). For selecting an interrupt generation period, program the RTCSEL when the timer is inactive (RTCRUN = “0”). During the timer operation, do not change
the RTCSEL programming at the same moment the timer stops.
Note 2: The timer automatically stops, and this register is initialized (the timer's binary counter is also initialized) if one of the following operations is performed while the timer is active:
1. Stopping the low-frequency oscillation (with SYSCR2<XTEN> = “0”)
2. When the TMP86PS27FG are put in STOP or SLEEP0 mode
Therefore, before activating the timer after releasing from STOP or SLEEP0 mode, reprogram the registers again.
Note 3: If a read instruction for RTCCR is executed, undefined value is set to bits 7 to 3.
Note 4: If break processing is performed on the debugger for the development tool during the timer operation, the timer stops
counting (contents of the RTCCR isn't altered). When the break is cancelled, processing is restarted from the point at
which it was suspended.
Page 123
10. Real-Time Clock
10.3 Function
TMP86PS27FG
10.3 Function
The RTC counts up on the internal low-frequency clock. When RTCCR<RTCRUN> is set to “1”, the binary
counter starts counting up. Each time the end of the period specified with RTCCR<RTCSEL> is detected, an
INTRTC interrupt is generated, and the binary counter is cleared. The timer continues counting up even after the
binary counter is cleared.
Page 124
TMP86PS27FG
11. Asynchronous Serial interface (UART )
11.1 Configuration
UART control register 1
Transmit data buffer
UARTCR1
TDBUF
3
Receive data buffer
RDBUF
2
INTTXD
Receive control circuit
Transmit control circuit
2
Shift register
Shift register
Parity bit
Stop bit
Noise rejection
circuit
INTRXD
M
P
X
RXD0
M
P
X
TXD0
RXD1
TXD1
Transmit/receive clock
Y
S
fc/13
fc/26
fc/52
fc/104
fc/208
fc/416
INTTC3
fc/96
A
B
C
D
E
F
G
H
fc/26
7
fc/2
8
fc/2
A
B
C
M
P
X
S
2
Y
4
2
Counter
UARTSR
UARTCR2
MULSEL
UART status register
UART control
register 2
Multi function
register
Baud rate generator
MPX: Multiplexer
Figure 11-1 UART (Asynchronous Serial Interface)
Page 125
11. Asynchronous Serial interface (UART )
11.2 Control
TMP86PS27FG
11.2 Control
UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR).
TXD pin and RXD pin can be selected a port assignment by Multi Function Register (MULSEL).
UART Control Register1
UARTCR1
(0025H)
7
6
5
4
3
TXE
RXE
STBT
EVEN
PE
2
1
0
BRG
(Initial value: 0000 0000)
TXE
Transfer operation
0:
1:
Disable
Enable
RXE
Receive operation
0:
1:
Disable
Enable
STBT
Transmit stop bit length
0:
1:
1 bit
2 bits
EVEN
Even-numbered parity
0:
1:
Odd-numbered parity
Even-numbered parity
Parity addition
0:
1:
No parity
Parity
PE
BRG
000:
001:
010:
011:
100:
101:
110:
111:
Transmit clock select
Write
only
fc/13 [Hz]
fc/26
fc/52
fc/104
fc/208
fc/416
TC3 ( Input INTTC3)
fc/96
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UARTCR1<RXE> and UARTCR1<TXE> should be set to “0” before UARTCR1<BRG> is changed.
UART Control Register2
UARTCR2
(0026H)
7
6
5
4
3
2
1
0
RXDNC
RXDNC
Selection of RXD input noise
rejectio time
STOPBR
Receive stop bit length
00:
01:
10:
11:
0:
1:
STOPBR
(Initial value: **** *000)
No noise rejection (Hysteresis input)
Rejects pulses shorter than 31/fc [s] as noise
Rejects pulses shorter than 63/fc [s] as noise
Rejects pulses shorter than 127/fc [s] as noise
Write
only
1 bit
2 bits
Note: When UARTCR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2<RXDNC>
= “10”, longer than 192/fc [s]; and when UARTCR2<RXDNC> = “11”, longer than 384/fc [s].
Page 126
TMP86PS27FG
UART Status Register
UARTSR
(0025H)
7
6
5
4
3
2
1
PERR
FERR
OERR
RBFL
TEND
TBEP
0
(Initial value: 0000 11**)
PERR
Parity error flag
0:
1:
No parity error
Parity error
FERR
Framing error flag
0:
1:
No framing error
Framing error
OERR
Overrun error flag
0:
1:
No overrun error
Overrun error
RBFL
Receive data buffer full flag
0:
1:
Receive data buffer empty
Receive data buffer full
TEND
Transmit end flag
0:
1:
On transmitting
Transmit end
TBEP
Transmit data buffer empty flag
0:
1:
Transmit data buffer full (Transmit data writing is finished)
Transmit data buffer empty
Read
only
Note: When an INTTXD is generated, TBEP flag is set to "1" automatically.
UART Receive Data Buffer
RDBUF
(0FABH)
7
6
5
4
3
2
1
0
Read only
(Initial value: 0000 0000)
UART Transmit Data Buffer
TDBUF
(0FABH)
7
6
5
4
3
2
1
0
Write only
(Initial value: 0000 0000)
Multi Function Register
MULSEL
(0FBBH)
7
UARTSEL
6
5
4
UART function pins select
3
2
1
0
(SIO
SEL)
UART
SEL
0:
1:
(Initial value: **** **00)
P01 (TXD0), P00 (RXD0)
P43 (TXD1), P37 (RXD1)
Note 1: Do not change MULSEL<UARTSEL> during UART operation.
Note 2: Set MULSEL register before performing the setting terminal of a I/O port when changing a terminal.
Page 127
R/W
11. Asynchronous Serial interface (UART )
11.3 Transfer Data Format
TMP86PS27FG
11.3 Transfer Data Format
In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and
parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the
transfer data. The transfer data formats are shown as follows.
PE
STBT
0
Frame Length
8
1
2
3
9
10
0
Start
Bit 0
Bit 1
0
1
Start
Bit 0
1
0
Start
1
1
Start
11
Bit 6
Bit 7
Stop 1
Bit 1
Bit 6
Bit 7
Stop 1
Stop 2
Bit 0
Bit 1
Bit 6
Bit 7
Parity
Stop 1
Bit 0
Bit 1
Bit 6
Bit 7
Parity
Stop 1
12
Stop 2
Figure 11-2 Transfer Data Format
Without parity / 1 STOP bit
With parity / 1 STOP bit
Without parity / 2 STOP bit
With parity / 2 STOP bit
Figure 11-3 Caution on Changing Transfer Data Format
Note: In order to switch the transfer data format, perform transmit operations in the above Figure 11-3 sequence except
for the initial setting.
Page 128
TMP86PS27FG
11.4 Transfer Rate
The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows.
Table 11-1 Transfer Rate (Example)
Source Clock
BRG
16 MHz
8 MHz
4 MHz
000
76800 [baud]
38400 [baud]
19200 [baud]
001
38400
19200
9600
010
19200
9600
4800
011
9600
4800
2400
100
4800
2400
1200
101
2400
1200
600
When TC3 is used as the UART transfer rate (when UARTCR1<BRG> = “110”), the transfer clock and transfer
rate are determined as follows:
Transfer clock [Hz] = TC3 source clock [Hz] / TTREG3 setting value
Transfer Rate [baud] = Transfer clock [Hz] / 16
11.5 Data Sampling Method
The UART receiver keeps sampling input using the clock selected by UARTCR1<BRG> until a start bit is
detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start
bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock
interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority
rule (The data are the same twice or more out of three samplings).
RXD pin
Start bit
RT0
1
2
3
Bit 0
4
5
6
7
8
9 10 11 12 13 14 15 0
1
2
3
4
5
6
7
8
9 10 11
2
3
4
5
6
7
8
9 10 11
RT clock
Start bit
Internal receive data
Bit 0
(a) Without noise rejection circuit
RXD pin
Start bit
RT0
1
2
3
Bit 0
4
5
6
7
8
9 10 11 12 13 14 15 0
1
RT clock
Internal receive data
Start bit
Bit 0
(b) With noise rejection circuit
Figure 11-4 Data Sampling Method
Page 129
11. Asynchronous Serial interface (UART )
11.6 STOP Bit Length
TMP86PS27FG
11.6 STOP Bit Length
Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>.
11.7 Parity
Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>.
11.8 Transmit/Receive Operation
11.8.1 Data Transmit Operation
Set UARTCR1<TXE> to “1”. Read UARTSR to check UARTSR<TBEP> = “1”, then write data in TDBUF
(Transmit data buffer). Writing data in TDBUF zero-clears UARTSR<TBEP>, transfers the data to the transmit
shift register and the data are sequentially output from the TXD pin. The data output include a one-bit start bit,
stop bits whose number is specified in UARTCR1<STBT> and a parity bit if parity addition is specified.
Select the data transfer baud rate using UARTCR1<BRG>. When data transmit starts, transmit buffer empty
flag UARTSR<TBEP> is set to “1” and an INTTXD interrupt is generated.
While UARTCR1<TXE> = “0” and from when “1” is written to UARTCR1<TXE> to when send data are
written to TDBUF, the TXD pin is fixed at high level.
When transmitting data, first read UARTSR, then write data in TDBUF. Otherwise, UARTSR<TBEP> is not
zero-cleared and transmit does not start.
11.8.2 Data Receive Operation
Set UARTCR1<RXE> to “1”. When data are received via the RXD pin, the receive data are transferred to
RDBUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity
bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to
RDBUF (Receive data buffer). Then the receive buffer full flag UARTSR<RBFL> is set and an INTRXD
interrupt is generated. Select the data transfer baud rate using UARTCR1<BRG>.
If an overrun error (OERR) occurs when data are received, the data are not transferred to RDBUF (Receive
data buffer) but discarded; data in the RDBUF are not affected.
Note:When a receive operation is disabled by setting UARTCR1<RXE> bit to “0”, the setting becomes valid when
data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting
may not become valid. If a framing error occurs, be sure to perform a re-receive operation.
Page 130
TMP86PS27FG
11.9 Status Flag
11.9.1 Parity Error
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin
Shift register
Parity
Stop
pxxxx0*
xxxx0**
1pxxxx0
UARTSR<PERR>
After reading UARTSR then
RDBUF clears PERR.
INTRXD interrupt
Figure 11-5 Generation of Parity Error
11.9.2 Framing Error
When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR<FERR> is set to “1”.
The UARTSR<FERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin
Shift register
Stop
Final bit
xxxx0*
xxx0**
0xxxx0
After reading UARTSR then
RDBUF clears FERR.
UARTSR<FERR>
INTRXD interrupt
Figure 11-6 Generation of Framing Error
11.9.3 Overrun Error
When all bits in the next data are received while unread data are still in RDBUF, overrun error flag
UARTSR<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF are not affected.
The UARTSR<OERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Page 131
11. Asynchronous Serial interface (UART )
11.9 Status Flag
TMP86PS27FG
UARTSR<RBFL>
RXD pin
Stop
Final bit
Shift register
xxx0**
RDBUF
yyyy
xxxx0*
1xxxx0
UARTSR<OERR>
After reading UARTSR then
RDBUF clears OERR.
INTRXD interrupt
Figure 11-7 Generation of Overrun Error
Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared.
11.9.4 Receive Data Buffer Full
Loading the received data in RDBUF sets receive data buffer full flag UARTSR<RBFL> to "1". The
UARTSR<RBFL> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin
Stop
Final bit
Shift register
xxx0**
RDBUF
yyyy
xxxx0*
1xxxx0
xxxx
After reading UARTSR then
RDBUF clears RBFL.
UARTSR<RBFL>
INTRXD interrupt
Figure 11-8 Generation of Receive Data Buffer Full
Note:If the overrun error flag UARTSR<OERR> is set during the period between reading the UARTSR and reading
the RDBUF, it cannot be cleared by only reading the RDBUF. Therefore, after reading the RDBUF, read the
UARTSR again to check whether or not the overrun error flag which should have been cleared still remains
set.
11.9.5 Transmit Data Buffer Empty
When no data is in the transmit buffer TDBUF, UARTSR<TBEP> is set to “1”, that is, when data in TDBUF
are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag
UARTSR<TBEP> is set to “1”. The UARTSR<TBEP> is cleared to “0” when the TDBUF is written after
reading the UARTSR.
Page 132
TMP86PS27FG
Data write
TDBUF
xxxx
*****1
Shift register
TXD pin
Data write
zzzz
yyyy
1xxxx0
*1xxxx
****1x
*****1
Start
Bit 0
Final bit
Stop
1yyyy0
UARTSR<TBEP>
After reading UARTSR writing TDBUF
clears TBEP.
INTTXD interrupt
Figure 11-9 Generation of Transmit Data Buffer Empty
11.9.6 Transmit End Flag
When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end flag
UARTSR<TEND> is set to “1”. The UARTSR<TEND> is cleared to “0” when the data transmit is stated after
writing the TDBUF.
Shift register
TXD pin
***1xx
****1x
*****1
1yyyy0
Stop
Start
*1yyyy
Bit 0
Data write for TDBUF
UARTSR<TBEP>
UARTSR<TEND>
INTTXD interrupt
Figure 11-10 Generation of Transmit End Flag and Transmit Data Buffer Empty
Page 133
11. Asynchronous Serial interface (UART )
11.9 Status Flag
TMP86PS27FG
Page 134
TMP86PS27FG
12. Synchronous Serial Interface (SIO)
The TMP86PS27FG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and
receive data buffer that can automatically and continuously transfer up to 64 bits of data.
Serial interface is connected to outside peripherl devices via SO, SI, SCK port.
12.1 Configuration
SIO control / status register
SIOSR
SIOCR1
SIOCR2
CPU
Transmit and
receive data buffer
(8 bytes in DBR)
Buffer control
circuit
Control circuit
Shift register
Shift
clock
7
6
5
4
3
2
1
0
SO
Serial data output
8-bit transfer
4-bit transfer
SI
Serial data input
INTSIO interrupt request
Serial clock
SCK
Serial clock I/O
Figure 12-1 Serial Interface
Page 135
12. Synchronous Serial Interface (SIO)
12.2 Control
TMP86PS27FG
12.2 Control
The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be
determined by reading SIO status register (SIOSR).
The transmit and receive data buffer is controlled by the SIOCR2<BUF>. The data buffer is assigned to address
0FA0H to 0FA7H for SIO in the DBR area, and can continuously transfer up to 8 words (bytes or nibbles) at one
time. When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full
(in the receive mode or transmit/receive mode) interrupt (INTSIO) is generated.
When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a
fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be
selected with SIOCR2<WAIT>.
SIO Control Register 1
SIOCR1
7
6
(0FA8H)
SIOS
SIOINH
SIOS
5
4
Continue / abort transfer
SIOM
2
1
SIOM
Indicate transfer start / stop
SIOINH
3
Transfer mode select
0
SCK
0:
Stop
1:
Start
(Initial value: 0000 0000)
0:
Continuously transfer
1:
Abort transfer (Automatically cleared after abort)
000:
8-bit transmit mode
010:
4-bit transmit mode
100:
8-bit transmit / receive mode
101:
8-bit receive mode
110:
4-bit receive mode
Write
only
Except the above: Reserved
NORMAL1/2, IDLE1/2 mode
SCK
Serial clock select
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/213
fs/25
fs/25
001
fc/28
fc/28
-
010
fc/27
fc/27
-
011
fc/26
fc/26
-
100
fc/25
fc/25
-
101
fc/24
fc/24
-
110
Reserved
111
External clock ( Input from SCK pin )
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz]
Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock.
Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Control Register 2
SIOCR2
(0FA9H)
7
6
5
4
3
WAIT
Page 136
2
1
BUF
0
(Initial value: ***0 0000)
Write
only
TMP86PS27FG
Always sets "00" except 8-bit transmit / receive mode.
WAIT
Wait control
Number of transfer words
(Buffer address in use)
BUF
00:
Tf = TD(Non wait)
01:
Tf = 2TD(Wait)
10:
Tf = 4TD(Wait)
11:
Tf = 8TD (Wait)
000:
1 word transfer
0FA0H
001:
2 words transfer
0FA0H ~ 0FA1H
010:
3 words transfer
0FA0H ~ 0FA2H
011:
4 words transfer
0FA0H ~ 0FA3H
100:
5 words transfer
0FA0H ~ 0FA4H
101:
6 words transfer
0FA0H ~ 0FA5H
110:
7 words transfer
0FA0H ~ 0FA6H
111:
8 words transfer
0FA0H ~ 0FA7H
Write
only
Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving.
Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest
address. ( The first buffer address transmitted is 0FA0H ).
Note 3: The value to be loaded to BUF is held after transfer is completed.
Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0).
Note 5: *: Don't care
Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Status Register
SIOSR
7
6
(0FA9H)
SIOF
SEF
SIOF
SEF
5
4
3
2
1
0
Serial transfer operating status monitor
0:
1:
Transfer terminated
Transfer in process
Shift operating status monitor
0:
1:
Shift operation terminated
Shift operation in process
Read
only
Note 1: Tf; Frame time, TD; Data transfer time
Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1".
(output)
SCK output
TD
Tf
Figure 12-2 Frame time (Tf) and Data transfer time (TD)
Multi Function Register
MULSEL
7
6
5
4
3
2
(0FBBH)
SIOSEL
SIO function pins select
0:
1:
1
0
SIOSEL
(UARTSEL)
P05 (SI0), P06 (SO0), P07 (SCK0)
P40 (SI1), P41 (SO1), P42 (SCK1)
Note 1: Do not change MULSEL<SIOSEL> during SIO operation.
Page 137
(Initial value: **** **00)
R/W
12. Synchronous Serial Interface (SIO)
12.3 Serial clock
TMP86PS27FG
Note 2: Set MULSEL register before performing the setting terminal of a I/O port when changing a terminal.
12.3 Serial clock
12.3.1 Clock source
Internal clock or external clock for the source clock is selected by SIOCR1<SCK>.
12.3.1.1 Internal clock
Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The
SCK pin goes high when transfer starts.
When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode)
cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock
and holds the next shift operation until the read/write processing is completed.
Table 12-1 Serial Clock Rate
NORMAL1/2, IDLE1/2 mode
DV7CK = 0
SCK
Clock
000
fc/2
13
001
SLOW1/2,
SLEEP1/2 mode
DV7CK = 1
Baud Rate
Clock
1.91 Kbps
5
Baud Rate
Clock
fs/2
1024 bps
fs/2
1024 bps
fc/28
61.04 Kbps
fc/28
61.04 Kbps
-
-
010
fc/27
122.07 Kbps
fc/27
122.07 Kbps
-
-
011
fc/26
244.14 Kbps
fc/26
244.14 Kbps
-
-
100
fc/25
488.28 Kbps
fc/25
488.28 Kbps
-
-
101
fc/24
976.56 Kbps
fc/24
976.56 Kbps
-
-
110
-
-
-
-
-
-
111
External
External
External
External
External
External
5
Baud Rate
Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz)
Automatically
wait function
SCK
pin (output)
SO
a0
pin (output)
Written transmit
data
a1
a2
a3
a
b0
b
b1
b2
b3
c0
c1
c
Figure 12-3 Automatic Wait Function (at 4-bit transmit mode)
12.3.1.2 External clock
An external clock connected to the SCK pin is used as the serial clock. In this case, output latch of this
port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This
pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for
interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz).
Page 138
TMP86PS27FG
SCK
pin (Output)
tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes)
4/fs (In the SLOW1/2, SLEEP1/2 modes)
tSCKL, tSCKH > 4tcyc
tSCKL tSCKH
Figure 12-4 External clock pulse width
12.3.2 Shift edge
The leading edge is used to transmit, and the trailing edge is used to receive.
12.3.2.1 Leading edge
Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/
output).
12.3.2.2 Trailing edge
Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output).
SCK pin
SO pin
Bit 0
Bit 1
Bit 2
Bit 3
Shift register
3210
*321
**32
***3
Bit 2
Bit 3
(a) Leading edge
SCK pin
SI pin
Shift register
Bit 0
Bit 1
0***
****
10**
210*
3210
*; Don’t care
(b) Trailing edge
Figure 12-5 Shift edge
12.4 Number of bits to transfer
Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of
the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving.
The data is transferred in sequence starting at the least significant bit (LSB).
12.5 Number of words to transfer
Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2<BUF>.
Page 139
12. Synchronous Serial Interface (SIO)
12.6 Transfer Mode
TMP86PS27FG
An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of
words is to be changed during transfer, the serial interface must be stopped before making the change. The number of
words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not
required to be stopped.
SCK pin
SO pin
a0
a1
a2
a3
INTSIO interrupt
(a) 1 word transmit
SCK pin
SO pin
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
b3
c0
c1
c2
c3
INTSIO interrupt
(b) 3 words transmit
SCK pin
SI pin
a0
a1
a2
a3
b0
b1
b2
INTSIO interrupt
(c) 3 words receive
Figure 12-6 Number of words to transfer (Example: 1word = 4bit)
12.6 Transfer Mode
SIOCR1<SIOM> is used to select the transmit, receive, or transmit/receive mode.
12.6.1 4-bit and 8-bit transfer modes
In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data
(number of transfer words to be transferred) to the data buffer registers (DBR).
After the data are written, the transmission is started by setting SIOCR1<SIOS> to “1”. The data are then
output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit
(LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift
register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (Buffer
empty) interrupt is generated to request the next transmitted data.
When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next
transmitted data are not loaded to the data buffer register by the time the number of data words specified with
the SIOCR2<BUF> has been transmitted. Writing even one word of data cancels the automatic-wait; therefore,
when transmitting two or more words, always write the next word before transmission of the previous word is
completed.
Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do
not use the DBR of the remained 5 words.
Page 140
TMP86PS27FG
When an external clock is used, the data must be written to the data buffer register before shifting next data.
Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request
to writing of the data to the data buffer register by the interrupt service program.
The transmission is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer
empty interrupt service program.
SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.
That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF>
is cleared to “0” when a transfer is completed.
When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to
“0”.
When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next
data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will
end.
If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then
SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO interrupt
DBR
a
b
Write Write
(a)
(b)
Figure 12-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)
Page 141
12. Synchronous Serial Interface (SIO)
12.6 Transfer Mode
TMP86PS27FG
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Input)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO interrupt
a
DBR
b
Write Write
(a)
(b)
Figure 12-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)
SCK pin
SIOSR<SIOF>
SO pin
MSB of last word
tSODH = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)
tSODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 12-9 Transmiiied Data Hold Time at End of Transfer
12.6.2 4-bit and 8-bit receive modes
After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. The
data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word
of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the
number of words specified with the SIOCR2<BUF> has been received, an INTSIO (Buffer full) interrupt is
generated to request that these data be read out. The data are then read from the data buffer registers by the
interrupt service program.
When the internal clock is used, and the previous data are not read from the data buffer register before the
next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read.
A wait will not be initiated if even one data word has been read.
Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore,
during SIO do not use such DBR for other applications.
Page 142
TMP86PS27FG
When an external clock is used, the shift operation is synchronized with the external clock; therefore, the
previous data are read before the next data are transferred to the data buffer register. If the previous data have
not been read, the next data will not be transferred to the data buffer register and the receiving of any more data
will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay
between the time when the interrupt request is generated and when the data received have been read.
The receiving is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer full
interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has
ended can be determined from the status of SIOSR<SIOF>. SIOSR<SIOF> is cleared to “0” when the receiving is ended. After confirmed the receiving termination, the final receiving data is read. When SIOCR1<SIOINH> is set, the receiving is immediately ended and SIOSR<SIOF> is cleared to “0”. (The received data is
ignored, and it is not required to be read out.)
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0” then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of data receiving, SIOCR2<BUF> must be rewritten before the received data is read
out.
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the transfer mode.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SI pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO Interrupt
DBR
a
b
Read out
Read out
Figure 12-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock)
12.6.3 8-bit transfer / receive mode
After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first
to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1<SIOS> to “1”.
When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving,
the data are input to the SI pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit
data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when
the number of data words specified with the SIOCR2<BUF> has been transferred. Usually, read the receive
data from the buffer register in the interrupt service. The data buffer register is used for both transmitting and
receiving; therefore, always write the data to be transmitted after reading the all received data.
When the internal clock is used, a wait is initiated until the received data are read and the next transfer data
are written. A wait will not be initiated if even one transfer data word has been written.
Page 143
12. Synchronous Serial Interface (SIO)
12.6 Transfer Mode
TMP86PS27FG
When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is
necessary to read the received data and write the data to be transmitted next before starting the next shift operation. When an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written.
The transmit/receive operation is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to
“1” in INTSIO interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the transmitting/receiving is ended at the time that the final bit of the data has been transmitted.
That the transmitting/receiving has ended can be determined from the status of SIOSR<SIOF>.
SIOSR<SIOF> is cleared to “0” when the transmitting/receiving is ended.
When SIOCR1<SIOINH> is set, the transmit/receive operation is immediately ended and SIOSR<SIOF> is
cleared to “0”.
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0”, then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”.
If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of transmit/receive operation, SIOCR2<BUF> must be rewritten before reading and
writing of the receive/transmit data.
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the transfer mode.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(output)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
SI pin
c0
c1
c2
c3
c4
c5
c6
c7
d0
d1
d2
d3
d4
d5
d6
d7
INTSIO interrupt
DBR
c
a
Write (a)
Read out (c)
b
Write (b)
d
Read out (d)
Figure 12-11 Transfer / Receive Mode (Example: 8bit, 1word transfer, Internal clock)
Page 144
TMP86PS27FG
SCK pin
SIOSR<SIOF>
SO pin
Bit 6
Bit 7 of last word
tSODH = min 4/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)
tSODH = min 4/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 12-12 Transmitted Data Hold Time at End of Transfer / Receive
Page 145
12. Synchronous Serial Interface (SIO)
12.6 Transfer Mode
TMP86PS27FG
Page 146
TMP86PS27FG
13. 10-bit AD Converter (ADC)
The TMP86PS27FG have a 10-bit successive approximation type AD converter.
13.1 Configuration
The circuit configuration of the 10-bit AD converter is shown in Figure 13-1.
It consists of control register ADCCR1 and ADCCR2, converted value register ADCDR1 and ADCDR2, a DA
converter, a sample-hold circuit, a comparator, and a successive comparison circuit.
DA converter
VAREF
VSS
R/2
R
R/2
AVDD
Analog input
multiplexer
AIN0
A
Sample hold
circuit
Reference
voltage
Y
10
Analog
comparator
n
S EN
Successive approximate circuit
Shift clock
AINDS
ADRS
SAIN
INTADC
Control circuit
4
ADCCR1
2
AMD
IREFON
AIN7
3
ACK
ADCCR2
AD converter control register 1, 2
8
ADCDR1
2
EOCF ADBF
ADCDR2
AD conversion result register 1, 2
Note: Before using AD converter, set appropriate value to I/O port register conbining a analog input port. For details, see the section on "I/O ports".
Figure 13-1 10-bit AD Converter
Page 147
13. 10-bit AD Converter (ADC)
13.2 Register configuration
TMP86PS27FG
13.2 Register configuration
The AD converter consists of the following four registers:
1. AD converter control register 1 (ADCCR1)
This register selects the analog channels and operation mode (Software start or repeat) in which to perform AD conversion and controls the AD converter as it starts operating.
2. AD converter control register 2 (ADCCR2)
This register selects the AD conversion time and controls the connection of the DA converter (Ladder
resistor network).
3. AD converted value register 1 (ADCDR1)
This register used to store the digital value fter being converted by the AD converter.
4. AD converted value register 2 (ADCDR2)
This register monitors the operating status of the AD converter.
AD Converter Control Register 1
ADCCR1
(000EH)
7
ADRS
6
5
AMD
4
3
2
AINDS
1
SAIN
AD conversion start
0:
1:
AD conversion start
AMD
AD operating mode
00:
01:
10:
11:
AD operation disable
Software start mode
Reserved
Repeat mode
AINDS
Analog input control
0:
1:
Analog input enable
Analog input disable
Analog input channel select
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADRS
SAIN
0
(Initial value: 0001 0000)
R/W
Note 1: Select analog input channel during AD converter stops (ADCDR2<ADBF> = "0").
Note 2: When the analog input channel is all use disabling, the ADCCR1<AINDS> should be set to "1".
Note 3: During conversion, Do not perform port output instruction to maintain a precision for all of the pins because analog input
port use as general input port. And for port near to analog input, Do not input intense signaling of change.
Note 4: The ADCCR1<ADRS> is automatically cleared to "0" after starting conversion.
Note 5: Do not set ADCCR1<ADRS> newly again during AD conversion. Before setting ADCCR1<ADRS> newly again, check
ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g.,
interrupt handling routine).
Note 6: After STOP or SLOW/SLEEP mode are started, AD converter control register1 (ADCCR1) is all initialized and no data can
be written in this register. Therfore, to use AD converter again, set the ADCCR1 newly after returning to NORMAL1 or
NORMAL2 mode.
Page 148
TMP86PS27FG
AD Converter Control Register 2
7
ADCCR2
(000FH)
6
IREFON
ACK
5
4
3
IREFON
"1"
2
1
ACK
0
"0"
(Initial value: **0* 000*)
DA converter (Ladder resistor) connection
control
0:
1:
Connected only during AD conversion
Always connected
AD conversion time select
(Refer to the following table about the conversion time)
000:
001:
010:
011:
100:
101:
110:
111:
39/fc
Reserved
78/fc
156/fc
312/fc
624/fc
1248/fc
Reserved
R/W
Note 1: Always set bit0 in ADCCR2 to "0" and set bit4 in ADCCR2 to "1".
Note 2: When a read instruction for ADCCR2, bit6 to 7 in ADCCR2 read in as undefined data.
Note 3: After STOP or SLOW/SLEEP mode are started, AD converter control register2 (ADCCR2) is all initialized and no data can
be written in this register. Therfore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL1 or
NORMAL2 mode.
Table 13-1 ACK setting and Conversion time
Condition
ACK
000
Conversion
time
16 MHz
8 MHz
4 MHz
2 MHz
10 MHz
5 MHz
2.5 MHz
39/fc
-
-
-
19.5 µs
-
-
15.6 µs
001
Reserved
010
78/fc
-
-
19.5 µs
39.0 µs
-
15.6 µs
31.2 µs
011
156/fc
-
19.5 µs
39.0 µs
78.0 µs
15.6 µs
31.2 µs
62.4 µs
100
312/fc
19.5 µs
39.0 µs
78.0 µs
156.0 µs
31.2 µs
62.4 µs
124.8 µs
101
624/fc
39.0 µs
78.0 µs
156.0 µs
-
62.4 µs
124.8 µs
-
110
1248/fc
78.0 µs
156.0 µs
-
-
124.8 µs
-
-
111
Reserved
Note 1: Setting for "−" in the above table are inhibited.
fc: High Frequency oscillation clock [Hz]
Note 2: Set conversion time setting should be kept more than the following time by Analog reference voltage (VAREF) .
-
VAREF = 4.5 to 5.5 V
15.6 µs and more
-
VAREF = 2.7 to 5.5 V
31.2 µs and more
AD Converted value Register 1
ADCDR1
(0021H)
7
6
5
4
3
2
1
0
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
3
2
1
0
(Initial value: 0000 0000)
AD Converted value Register 2
ADCDR2
(0020H)
7
6
5
4
AD01
AD00
EOCF
ADBF
(Initial value: 0000 ****)
Page 149
13. 10-bit AD Converter (ADC)
13.2 Register configuration
TMP86PS27FG
EOCF
ADBF
AD conversion end flag
0:
1:
Before or during conversion
Conversion completed
AD conversion BUSY flag
0:
1:
During stop of AD conversion
During AD conversion
Read
only
Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to
ADCDR2 more first than ADCDR1.
Note 2: The ADCDR2<ADBF> is set to "1" when AD conversion starts, and cleared to "0" when AD conversion finished. It also is
cleared upon entering STOP mode or SLOW mode .
Note 3: If a read instruction is executed for ADCDR2, read data of bit3 to bit0 are unstable.
Page 150
TMP86PS27FG
13.3 Function
13.3.1 Software Start Mode
After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conversion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started.
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF> is set to 1, the AD conversion finished interrupt (INTADC) is generated.
ADRS is automatically cleared after AD conversion has started. Do not set ADCCR1<ADRS> newly again
(Restart) during AD conversion. Before setting ADRS newly again, check ADCDR2<EOCF> to see that the
conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine).
AD conversion start
AD conversion start
ADCCR1<ADRS>
ADCDR2<ADBF>
ADCDR1 status
Indeterminate
1st conversion result
2nd conversion result
EOCF cleared by reading
conversion result
ADCDR2<EOCF>
INTADC interrupt request
ADCDR1
ADCDR2
Conversion result
read
Conversion result
read
Conversion result
read
Conversion result
read
Figure 13-2 Software Start Mode
13.3.2 Repeat Mode
AD conversion of the voltage at the analog input pin specified by ADCCR1<SAIN> is performed repeatedly.
In this mode, AD conversion is started by setting ADCCR1<ADRS> to “1” after setting ADCCR1<AMD> to
“11” (Repeat mode).
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF> is set to 1, the AD conversion finished interrupt (INTADC) is generated.
In repeat mode, each time one AD conversion is completed, the next AD conversion is started. To stop AD
conversion, set ADCCR1<AMD> to “00” (Disable mode) by writing 0s. The AD convert operation is stopped
immediately. The converted value at this time is not stored in the AD converted value register.
Page 151
13. 10-bit AD Converter (ADC)
13.3 Function
TMP86PS27FG
ADCCR1<AMD>
“11”
“00”
AD conversion start
ADCCR1<ADRS>
1st conversion
result
Conversion operation
Indeterminate
ADCDR1,ADCDR2
2nd conversion result
3rd conversion result
1st conversion result
2nd conversion result
AD convert operation suspended.
Conversion result is not stored.
3rd conversion result
ADCDR2<EOCF>
EOCF cleared by reading
conversion result
INTADC interrupt request
ADCDR1
Conversion
result read
ADCDR2
Conversion
result read
Conversion
result read
Conversion
result read
Conversion
result read
Conversion
result read
Figure 13-3 Repeat Mode
13.3.3
Register Setting
1. Set up the AD converter control register 1 (ADCCR1) as follows:
• Choose the channel to AD convert using AD input channel select (SAIN).
• Specify analog input enable for analog input control (AINDS).
• Specify AMD for the AD converter control operation mode (software or repeat mode).
2. Set up the AD converter control register 2 (ADCCR2) as follows:
• Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Figure 13-1 and AD converter control register 2.
• Choose IREFON for DA converter control.
3. After setting up (1) and (2) above, set AD conversion start (ADRS) of AD converter control register 1
(ADCCR1) to “1”. If software start mode has been selected, AD conversion starts immediately.
4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD converted value register 1 (ADCDR1) and the AD conversion finished flag (EOCF) of AD converted
value register 2 (ADCDR2) is set to “1”, upon which time AD conversion interrupt INTADC is generated.
5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register
read, although EOCF is cleared the previous conversion result is retained until the next conversion is
completed.
Page 152
TMP86PS27FG
Example :After selecting the conversion time 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store
the upper 8 bits in address 0009FH in RAM. The operation mode is software start mode.
SLOOP :
: (port setting)
:
;Set port register approrriately before setting AD
converter registers.
:
:
(Refer to section I/O port in details)
LD
(ADCCR1) , 00100011B
; Select AIN3
LD
(ADCCR2) , 11011000B
;Select conversion time(312/fc) and operation
mode
SET
(ADCCR1) . 7
; ADRS = 1(AD conversion start)
TEST
(ADCDR2) . 5
; EOCF= 1 ?
JRS
T, SLOOP
LD
A , (ADCDR2)
LD
(9EH) , A
LD
A , (ADCDR1)
LD
(9FH), A
; Read result data
; Read result data
13.4 STOP/SLOW Modes during AD Conversion
When standby mode (STOP or SLOW mode) is entered forcibly during AD conversion, the AD convert operation
is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value). Also, the
conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to read
the conversion results before entering standby mode (STOP or SLOW mode).) When restored from standby mode
(STOP or SLOW mode), AD conversion is not automatically restarted, so it is necessary to restart AD conversion.
Note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing
into the analog reference voltage.
Page 153
13. 10-bit AD Converter (ADC)
13.5 Analog Input Voltage and AD Conversion Result
TMP86PS27FG
13.5 Analog Input Voltage and AD Conversion Result
The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 13-4.
3FFH
3FEH
3FDH
AD
conversion
result
03H
02H
01H
VAREF
0
1
2
3
1021 1022 1023 1024
Analog input voltage
VSS
1024
Figure 13-4 Analog Input Voltage and AD Conversion Result (Typ.)
Page 154
TMP86PS27FG
13.6 Precautions about AD Converter
13.6.1 Restrictions for AD Conversion interrupt (INTADC) usage
When an AD interrupt is used, it may not be processed depending on program composition. For example, if
an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15
(INTADC) is being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being
processed.
The completion of AD conversion can be detected by the following methods:
(1) Method not using the AD conversion end interrupt
Whether or not AD conversion is completed can be detected by monitoring the AD conversion end flag
(EOCF) by software. This can be done by polling EOCF or monitoring EOCF at regular intervals after start of
AD conversion.
(2) Method for detecting AD conversion end while a lower-priority interrupt is being processed
While an interrupt with priority lower than INTADC is being processed, check the AD conversion end flag
(EOCF) and interrupt latch IL15. If IL15 = 0 and EOCF = 1, call the AD conversion end interrupt processing
routine with consideration given to PUSH/POP operations. At this time, if an interrupt request with priority
higher than INTADC has been set, the AD conversion end interrupt processing routine will be executed first
against the specified priority. If necessary, we recommend that the AD conversion end interrupt processing routine be called after checking whether or not an interrupt request with priority higher than INTADC has been
set.
13.6.2 Analog input pin voltage range
Make sure the analog input pins (AIN0 to AIN7) are used at voltages within VAREF to VSS. If any voltage
outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain.
The other analog input pins also are affected by that.
13.6.3 Analog input shared pins
The analog input pins (AIN0 to AIN7) are shared with input/output ports. When using any of the analog
inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary
to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other
pins may also be affected by noise arising from input/output to and from adjacent pins.
13.6.4 Noise Countermeasure
The internal equivalent circuit of the analog input pins is shown in Figure 13-5. The higher the output
impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capacitor external to the chip.
Internal resistance
AINi
Permissible signal
source impedance
5 kΩ (typ)
Analog comparator
Internal capacitance
C = 22 pF (typ.)
5 kΩ (max)
DA converter
Note) i = 7 to 0
Figure 13-5
Analog Input Equivalent Circuit and Example of Input Pin Processing
Page 155
13. 10-bit AD Converter (ADC)
13.6 Precautions about AD Converter
TMP86PS27FG
Page 156
TMP86PS27FG
14. Key-on Wakeup (KWU)
In the TMP86PS27FG, the STOP mode is released by not only P20(INT5/STOP) pin but also four (STOP2 to
STOP5) pins.
When the STOP mode is released by STOP2 to STOP5 pins, the STOP pin needs to be used.
In details, refer to the following section " 14.2 Control ".
14.1 Configuration
INT5
STOP
STOP mode
release signal
(1: Release)
STOP2
STOP3
STOP4
STOPCR
(0FAAH)
STOP5
STOP4
STOP3
STOP2
STOP5
Figure 14-1 Key-on Wakeup Circuit
14.2 Control
STOP2 to STOP5 pins can controlled by Key-on Wakeup Control Register (STOPCR). It can be configured as
enable/disable in 1-bit unit. When those pins are used for STOP mode release, configure corresponding I/O pins to
input mode by I/O port register beforehand.
Key-on Wakeup Control Register
STOPCR
7
6
5
4
(0FAAH)
STOP5
STOP4
STOP3
STOP2
3
2
1
0
(Initial value: 0000 ****)
STOP5
STOP mode released by STOP5
0:Disable
1:Enable
Write
only
STOP4
STOP mode released by STOP4
0:Disable
1:Enable
Write
only
STOP3
STOP mode released by STOP3
0:Disable
1:Enable
Write
only
STOP2
STOP mode released by STOP2
0:Disable
1:Enable
Write
only
14.3 Function
Stop mode can be entered by setting up the System Control Register (SYSCR1), and can be exited by detecting the
"L" level on STOP2 to STOP5 pins, which are enabled by STOPCR, for releasing STOP mode (Note1).
Page 157
14. Key-on Wakeup (KWU)
14.3 Function
TMP86PS27FG
Also, each level of the STOP2 to STOP5 pins can be confirmed by reading corresponding I/O port data register,
check all STOP2 to STOP5 pins "H" that is enabled by STOPCR before the STOP mode is startd (Note2,3).
Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM> = “0”), inhibit input from STOP2 to
STOP5 pins by Key-on Wakeup Control Register (STOPCR) or must be set "H" level into STOP2 to STOP5 pins
that are available input during STOP mode.
Note 2: When the STOP pin input is high or STOP2 to STOP5 pins inputwhich is enabled by STOPCR is low, executing an
instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release
sequence (Warm up).
Note 3: The input circuit of Key-on Wakeup input and Port input is separatedÅAso each input voltage threshold value is
diffrent. Therefore, a value comes from port input before STOP mode start may be diffrent from a value which is
detected by Key-on Wakeup input (Figure 14-2).
Note 4: STOP pin doesn’t have the control register such as STOPCR, so when STOP mode is released by STOP2 to
STOP5 pins, STOP pin also should be used as STOP mode release function.
Note 5: In STOP mode, Key-on Wakeup pin which is enabled as input mode (for releasing STOP mode) by Key-on
Wakeup Control Register (STOPCR) may genarate the penetration current, so the said pin must be disabled AD
conversion input (analog voltage input).
Note 6: When the STOP mode is released by STOP2 to STOP5 pins, the level of STOP pin should hold "L" level (Figure
14-3).
External pin
Port input
Key-on wakeup
input
Figure 14-2 Key-on Wakeup Input and Port Input
b) In case of STOP2 to STOP5
a) STOP
STOP pin
STOP pin "L"
STOP mode
Release
STOP mode
STOP2 pin
STOP mode
Release
STOP mode
Figure 14-3 Priority of STOP pin and STOP2 to STOP5 pins
Table 14-1 Release level (edge) of STOP mode
Release level (edge)
Pin name
SYSCR1<RELM>="1"
(Note2)
SYSCR1<RELM>="0"
STOP
"H" level
Rising edge
STOP2
"L" level
Don’t use (Note1)
STOP3
"L" level
Don’t use (Note1)
STOP4
"L" level
Don’t use (Note1)
STOP5
"L" level
Don’t use (Note1)
Page 158
TMP86PS27FG
15. LCD Driver
The TMP86PS27FG has a driver and control circuit to directly drive the liquid crystal device (LCD). The pins to
be connected to LCD are as follows:
1. Segment output port 40 pins (SEG39 to SEG0)
2. Common output port4 pins (COM3 to COM0)
In addition, C0, C1, V1, V2, V3 pin are provided for the LCD driver’s booster circuit.
The devices that can be directly driven is selectable from LCD of the following drive methods:
1. 1/4 Duty (1/3 Bias) LCD
Max 160 Segments(8 segments × 20 digits)
2. 1/3 Duty (1/3 Bias) LCD
Max 120 Segments(8 segments × 15 digits)
3. 1/2 Duty (1/2 Bias) LCD
Max 80 Segments(8 segments × 10 digits)
4. Static LCD
Max 40 Segments(8 segments × 5 digits)
15.1 Configuration
LCDCR
7
6
EDSP BRES
5
4
VFSEL
3
2
1
DUTY
0
SLF
DBR
fc/217, fs/29
display data area
fc/216, fs/28
fc/215
fc/213
Timing
control
Duty
control
Display data select control
fc/213, fs/25
fc/211, fs/23
Blanking
control
fc/210, fs/22
fc/29
Constant voltage
booster circuit
C0 C1
V1 V2 V3
Display data buffer register
Common driver
COM0
to
Segment driver
COM3
SEG0
SEG39
Figure 15-1 LCD Driver
Note: The LCD driver incorporates a dedicated divider circuit. Therefore, the break function of a debugger (development
tool) will not stop LCD driver output.
Page 159
15. LCD Driver
15.2 Control
TMP86PS27FG
15.2 Control
The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver’s display is enabled using
the EDSP.
LCD Driver Control Register
LCDCR
(0028H)
7
6
EDSP
BRES
5
4
3
VFSEL
2
1
DUTY
0
SLF
(Initial value: 0000 0000)
EDSP
LCD Display Control
0: Blanking
1: Enables LCD display (Blanking is released)
BRES
Booster circuit control
0: Disable (use divider resistance)
1: Enable
NORMAL1/2, IDLE/1/2 mode
VFSEL
DUTY
Selection of boost frequency
Selection of driving methods
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP0/1/2 mode
00
fc/213
fs/25
fs/25
01
fc/211
fs/23
fs/23
10
fc/210
fs/22
fs/22
11
fc/29
fc/29
–
NORMAL1/2, IDLE/1/2 mode
SLF
R/W
00: 1/4 Duty (1/3 Bias)
01: 1/3 Duty (1/3 Bias)
10: 1/2 Duty (1/2 Bias)
11: Static
Selection of LCD frame frequency
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP0/1/2 mode
00
fc/217
fs/29
fs/29
01
fc/216
fs/28
fs/28
10
fc/215
fc/215
–
11
fc/213
fc/213
–
Note 1: When <BRES>(Booster circuit control) is set to “0”, VDD ≥ V3 ≥ V2 ≥ V1 ≥ VSS should be satisfied.
When <BRES> is set to “1”, 5.5 [V] ≥ V3 ≥ VDD should be satisfied.
If these conditions are not satisfied, it not only affects the quality of LCD display but also may damage the device due to
over voltage of the port.
Note 2: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set LCDCR<DUTY> to "10" or "11"
when the booster circuit is enable.
Note 3: Do not set SLF to “10” or “11” in SLOW1/2 modes.
Note 4: Do not set VFSEL to “11” SLOW1/2 modes.
Page 160
TMP86PS27FG
15.2.1 LCD driving methods
As for LCD driving method, 4 types can be selected by LCDCR<DUTY>. The driving method is initialized
in the initial program according to the LCD used.
VLCD3
VLCD3
1/fF
1/fF
0
0
−VLCD3
Data "1"
Data "0"
−VLCD3
(a) 1/4 Duty (1/3 Bias)
VLCD3
Data "0"
(b) 1/3 Duty (1/3 Bias)
VLCD3
1/fF
Data "1"
1/fF
0
0
−VLCD3
−VLCD3
Data "1"
Data "0"
Data "1"
(d) Static
(c) 1/2 Duty (1/2 Bias)
Note 1: fF: Frame frequency
Note 2: VLCD3: LCD drive voltage
Figure 15-2 LCD Drive Waveform (COM-SEG pins)
Page 161
Data "0"
15. LCD Driver
15.2 Control
TMP86PS27FG
15.2.2 Frame frequency
Frame frequency (fF) is set according to driving method and base frequency as shown in the following Table
15-1. The base frequency is selected by LCDCR<SLF> according to the frequency fc and fs of the basic clock
to be used.
Table 15-1 Setting of LCD Frame Frequency
(a) At the single clock mode. At the dual clock mode (DV7CK = 0).
Frame frequency [Hz]
SLF
Base frequency [Hz]
1/4 Duty
1/3 Duty
4 fc
--- • -------3 2 17
1/2 Duty
Static
4 fc
--- • -------2 2 17
fc
-------17
2
fc
-------17
2
fc
-------17
2
(fc = 16 MHz)
122
163
244
122
(fc = 8 MHz)
61
81
122
61
fc
-------16
2
fc
-------16
2
4 fc
--- • -------2 2 16
fc
-------16
2
(fc = 8 MHz)
122
163
244
122
(fc = 4 MHz)
61
81
122
61
fc
-------15
2
fc
-------15
2
4 fc
--- • -------2 2 15
fc
-------15
2
(fc = 4 MHz)
122
163
244
122
(fc = 2 MHz)
61
81
122
61
fc
-------13
2
fc
-------13
2
4 fc
--- • -------2 2 13
fc
-------13
2
(fc = 1 MHz)
122
244
122
00
4 fc
--- • -------3 2 16
01
4 fc
--- • -------3 2 15
10
11
4 fc
--- • -------3 2 13
163
Note: fc: High-frequency clock [Hz]
Table 15-2
(b) At the dual clock mode (DV7CK = 1 or SYSCK = 1)
Frame frequency [Hz]
SLF
00
01
Base frequency [Hz]
1/4 Duty
1/3 Duty
1/2 Duty
Static
fs
-----9
2
fs
-----9
2
4 fs
--- • -----3 29
4 fs
--- • -----2 29
fs
-----9
2
(fs = 32.768 kHz)
64
85
128
64
fs
-----8
2
fs
-----8
2
4 fs
--- • -----3 28
4 fs
--- • -----2 28
fs
-----8
2
(fs = 32.768 kHz)
128
171
256
128
Note: fs: Low-frequency clock [Hz]
Page 162
TMP86PS27FG
15.2.3 Driving method for LCD driver
In the TMP86PS27FG, LCD driving voltages can be generated using either an internal booster circuit or an
external resistor divider. This selection is made in LCDCR<BRES>.
15.2.3.1 When using the booster circuit (LCDCR<BRES>="1")
When the reference voltage is connected to the V1 pin, the booster circuit boosts the reference voltage
twofold (V2) or threefold (V3) to generate the output voltages for segment/common signals. When the
reference voltage is connected to the V2 pin, it is reduced to 1/2 (V1) or boosted to 3/2 (V3). When the
reference voltage is connected to the V3 pin, it is reduced to 1/3 (V1) or 2/3 (V2).
LCDCR<VFSEL> is used to select the reference frequency in the booster circuit. The faster the boosting frequency, the higher the segment/common drive capability, but power consumption is increased.
Conversely, the slower the boosting frequency, the lower the segment/common drive capability, but power
consumption is reduced. If the drive capability is insufficient, the LCD may not be displayed clearly.
Therefore, select an optimum boosting frequency for the LCD panel to be used.
Table 15-3 shows the V3 pin current capacity and boosting frequency.
Note: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set
LCDCR<DUTY> to "10" or "11" when the booster circuit is enable (LCDCR<BRES>="1").
Keep the following
condition.
VDD
V3
V2
V3
V1 = 1/3 x V3
C = 0.1 to 0.47 µF
V1
C
C
Reference voltage
C1
C0
C
VSS
a) Reference pin = V1
Keep the following
condition.
VDD
V3
V2
V3
V2 = 2/3 x V3
C = 0.1 to 0.47 µF
V1
C
C
C
Reference voltage
C1
C0
VSS
b) Reference pin = V2
Page 163
C
15. LCD Driver
15.2 Control
TMP86PS27FG
VDD
Keep the following
condition.
V3
C
V2
V3
C
V1
Reference voltage
C
C
= 0.1 to 0.47 µF
C1
C
C0
VSS
c) Reference pin = V3
VDD
Keep the following
condition.
V3
V2
V3 =
V1
C
C
C
C
= 0.1 to 0.47 µF
C1
C0
C
VSS
d) Reference pin = V3
Note 1: When the TMP86PS27FG uses the booster circuit to drive the LCD, the power supply and capacitor for the booster circuit
should be connected as shown above.
Note 2: When the reference voltage is connected to a pin other than V1, add a capacitor between V1 and GND.
Note 3: The connection examples shown above are different from those shown in the datasheets of the existing mask or OTP
products. Since the above connection method enhances the boosting characteristics, it is recommended that new boards
be designed using the above connection method. (Using the existing connection method does not affect LCD display.)
Figure 15-3 Connection Examples When Using the Booster Circuit (LCDCR<BRES> = “1”)
Table 15-3 V3 Pin Current Capacity and Boosting Frequency (typ.)
VFSEL
Boosting frequency
fc = 16 MHz
fc = 8 MHz
fc = 4 MHz
fc = 32.768 MHz
00
fc/213 or fs/25
−37 mV/ µA
−80 mV/ µA
−138 mV/ µA
−76 mV/ µA
01
fc/211 or fs/23
−19 mV/ µA
−24 mV/ µA
−37 mV/ µA
−23 mV/ µA
10
fc/210 or fs/22
−17 mV/ µA
−19 mV/ µA
−24 mV/ µA
−18 mV/ µA
11
fc/29
−16 mV/ µA
−17 mV/ µA
−19 mV/ µA
–
Note 1: The current capacity is the amount of voltage that falls per 1µA.
Note 2: The boosting frequency should be selected depending on your LCD panel.
Note 3: For the reference pin V1 or V2, a current capacity ten times larger than the above is recommended to ensure stable operation.
For example, when the boosting frequency is fc/29 (at fc = 8 MHz), −1.7 mV/ µA or more is recommended for the current
capacity of the reference pin V1.
Page 164
TMP86PS27FG
15.2.3.2 When using an external resistor divider (LCDCR<BRES>="0")
When an external resistor divider is used, the voltage of an external power supply is divided and input
on V1, V2, and V3 to generate the output voltages for segment/common signals.
The smaller the external resistor value, the higher the segment/common drive capability, but power consumption is increased. Conversely, the larger the external resistor value, the lower the segment/common
drive capability, but power consumption is reduced. If the drive capability is insufficient, the LCD may
not be displayed clearly. Therefore, select an optimum resistor value for the LCD panel to be used.
Adjustment of
contrast
VDD
Adjustment of
contrast
VDD
V3
Adjustment of
contrast
VDD
V3
V3
R1
R1
V2
V2
C0
Open
C1
Open
R2
Open
C0
Open
C1
Open
C1
Open
V1
V1
VSS
VSS
R1
VSS
1/2 Bias (R1 = R2)
1/3 Bias (R1 = R2 = R3)
V1
R2
R3
Keep the following conditon.
VDD V3 V2 V1
V2
C0
Static
VSS
Figure 15-4 Connection Examples When Using an External Resistor Divider
(LCDCR<BRES> = “0”)
15.3 LCD Display Operation
15.3.1 Display data setting
Display data is stored to the display data area (assigned to address 0F80H to 0F93H, 20bytes) in the DBR.
The display data which are stored in the display data area is automatically read out and sent to the LCD driver
by the hardware. The LCD driver generates the segment signal and common signal according to the display
data and driving method. Therefore, display patterns can be changed by only over writing the contents of display data area by the program. Table 15-5 shows the correspondence between the display data area and SEG/
COM pins.
LCD light when display data is “1” and turn off when “0”. According to the driving method of LCD, the
number of pixels which can be driven becomes different, and the number of bits in the display data area which
is used to store display data also becomes different.
Therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the
addresses not connected to LCD can be used to store general user process data (see Table 15-4).
Note:The display data memory contents become unstable when the power supply is turned on; therefore, the display data memory should be initialized by an initiation routine.
Page 165
15. LCD Driver
15.3 LCD Display Operation
TMP86PS27FG
Table 15-4 Driving Method and Bit for Display Data
Driving methods
Bit 7/3
Bit 6/2
Bit 5/1
Bit 4/0
1/4 Duty
COM3
COM2
COM1
COM0
1/3 Duty
–
COM2
COM1
COM0
1/2 Duty
–
–
COM1
COM0
Static
–
–
–
COM0
Note: –: This bit is not used for display data
Table 15-5 LCD Display Data Area (DBR)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0F80H
SEG1
SEG0
0F81H
SEG3
SEG2
0F82H
SEG5
SEG4
0F83H
SEG7
SEG6
Bit 1
Bit 0
COM1
COM0
0F84H
SEG9
SEG8
0F85H
SEG11
SEG10
0F86H
SEG13
SEG12
0F87H
SEG15
SEG14
0F88H
SEG17
SEG16
0F89H
SEG19
SEG18
0F8AH
SEG21
SEG20
0F8BH
SEG23
SEG22
0F8CH
SEG25
SEG24
0F8DH
SEG27
SEG26
0F8EH
SEG29
SEG28
0F8FH
SEG31
SEG30
0F90H
SEG33
SEG32
0F91H
SEG35
SEG34
0F92H
SEG37
SEG36
0F93H
SEG39
SEG38
COM3
COM2
COM1
COM0
COM3
COM2
15.3.2 Blanking
Blanking is enabled when EDSP is cleared to “0”.
Blanking turns off LCD through outputting a GND level to SEG/COM pin.
When in STOP mode, EDSP is cleared to “0” and automatically blanked. To redisplay ICD after exiting
STOP mode, it is necessary to set EDSP back to “1”.
Note:During reset, the LCD segment outputs and LCD common outputs are fixed “0” level. But the multiplex terminal of input/output port and LCD segment output becomes high impedance. Therefore, when the reset input is
long remarkably, ghost problem may appear in LCD display.
Page 166
TMP86PS27FG
15.4 Control Method of LCD Driver
15.4.1 Initial setting
Figure 15-5 shows the flowchart of initialization.
Example : To operate a 1/4 duty LCD of 40 segments × 4 com-mons at frame frequency fc/216 [Hz], and booster frequency fc/213 [Hz]
LD
(LCDCR), 01000001B
; Sets LCD driving method and frame frequency. Boost frequency
LD
(P*LCR), 0FFH
; Sets segment output control register. (*; Port No.)
:
:
:
:
LD
; Sets the initial value of display data.
(LCDCR), 11000001B
; Display enable
Sets LCD driving method (DUTY).
Sets boost frequency (VFSEL).
Sets frame frequency (SLF).
Enables booster circuit (BRES)
Sets segment output control registers
(P*LCR (*; Port No.))
Initialization of display data area.
Display enable (EDSP)
(Releases from blanking.)
Figure 15-5 Initial Setting of LCD Driver
15.4.2 Store of display data
Generally, display data are prepared as fixed data in program memory (ROM) and stored in display data area
by load command.
Page 167
15. LCD Driver
15.4 Control Method of LCD Driver
TMP86PS27FG
Example :To display using 1/4 duty LCD a numerical value which corresponds to the LCD data stored in data memory at address 80H (when pins COM and SEG are connected to LCD as in Figure 15-6), display data
become as shown in Table 15-6.
LD
A, (80H)
ADD
A, TABLE-$-7
LD
HL, 0F80H
LD
W, (PC + A)
LD
(HL), W
RET
TABLE:
DB
11011111B, 00000110B,
11100011B, 10100111B,
00110110B, 10110101B,
11110101B, 00010111B,
11110111B, 10110111B
Note:DB is a byte data difinition instruction.
COM0
COM1
COM2
COM3
SEG0
SEG1
Figure 15-6 Example of COM, SEG Pin Connection (1/4 Duty)
Table 15-6 Example of Display Data (1/4 Duty)
No.
display
Display data
No.
0
11011111
5
10110101
1
00000110
6
11110101
2
11100011
7
00000111
3
10100111
8
11110111
4
00110110
9
10110111
Page 168
display
Display data
TMP86PS27FG
Example 2: Table 15-6 shows an example of display data which are displayed using 1/2 duty LCD in the
same way as Table 15-7. The connection between pins COM and SEG are the same as shown in Figure 15-7.
COM0
SEG3
SEG0
SEG2
COM1
SEG1
Figure 15-7 Example of COM, SEG Pin Connection
Table 15-7 Example of Display Data (1/2 Duty)
Display data
Display data
Number
Number
High order address
Low order address
High order address
Low order address
0
**01**11
**01**11
5
**11**10
**01**01
1
**00**10
**00**10
6
**11**11
**01**01
2
**10**01
**01**11
7
**01**10
**00**11
3
**10**10
**01**11
8
**11**11
**01**11
4
**11**10
**00**10
9
**11**10
**01**11
Note: *: Don’t care
Page 169
15. LCD Driver
15.4 Control Method of LCD Driver
TMP86PS27FG
15.4.3 Example of LCD drive output
COM0
COM1
COM2
COM3
SEG0
SEG1
EDSP
VLCD3
SEG0
0
VLCD3
SEG1
0
Display data area
VLCD3
COM0
0
Address
0F80H 1011 0101
VLCD3
COM1
0
VLCD3
COM2
0
VLCD3
COM3
0
VLCD3
0
COM0-SEG0
(Selected)
−VLCD3
VLCD3
0
COM2-SEG1
(Non selected)
−VLCD3
Figure 15-8 1/4 Duty (1/3 bias) Drive
Page 170
TMP86PS27FG
SEG1
SEG0
SEG2
COM0
COM1
COM2
EDSP
VLCD3
SEG0
0
Display data area
Address
VLCD3
SEG1
0
VLCD3
SEG2
0F80H
*111 *010
0F81H
**** *001
0
VLCD3
COM0
0
VLCD3
*: Don’t care
COM1
0
VLCD3
COM2
0
VLCD3
COM0-SEG1
(Selected)
0
−VLCD3
VLCD3
COM1-SEG2
(Non selected)
0
−VLCD3
Figure 15-9 1/3 Duty (1/3 bias) Drive
Page 171
15. LCD Driver
15.4 Control Method of LCD Driver
TMP86PS27FG
COM0
SEG3
COM0
COM2
COM1
COM1
EDSP
VLCD3
SEG0
0
Display data area
Address
VLCD3
SEG1
0
VLCD3
SEG2
0F80H **01 **01
0F81H **11 **10
*: Don’t care
0
VLCD3
SEG3
0
VLCD3
COM0
0
VLCD3
COM1
0
VLCD3
0
COM0-SEG1
(Selected)
VLCD3
−VLCD3
0
−VLCD3
COM1-SEG2
(Non selected)
Figure 15-10 1/2 Duty (1/2 bias) Drive
Page 172
TMP86PS27FG
SEG0
SEG1
SEG5
SEG6
SEG4
SEG2
SEG3
SEG7
COM0
Display data area
EDSP
Address
0F80H
***0 ***1
0F81H
***1 ***1
0F82H
***1 ***0
0F83H
***0 ***1
*: Don’t care
VLCD3
SEG0
0
VLCD3
SEG4
0
VLCD3
SEG7
0
VLCD3
COM0
0
VLCD3
COM0-SEG0
(Selected)
0
−VLCD3
VLCD3
COM0-SEG4
0
(Non selected)
−VLCD3
Figure 15-11 Static Drive
Page 173
15. LCD Driver
15.4 Control Method of LCD Driver
TMP86PS27FG
Page 174
TMP86PS27FG
16. OTP operation
This section describes the funstion and basic operationalblocks of TMP86PS27FG. The TMP86PS27FG has
PROM in place of the mask ROM which is included in the TMP86CM27FG/CP27AFG. The configuration and
function are the same as the TMP86CM27FG/CP27AFG. In addition, TMP86PS27FG operates as the single clock
mode when releasing reset. When using the dual clock mode, oscillate a low-frequency clock by [ SET. (SYSCR2).
XTEN ] command at the beginning of program.
16.1 Operating mode
The TMP86PS27FG has MCU mode and PROM mode.
16.1.1 MCU mode
The MCU mode is set by fixing the TEST/VPP pin to the low level. (TEST/VPP pin cannot be used open
because it has no built-in pull-down resistor).
16.1.1.1 Program Memory
The TMP86PS27FG has 60K bytes built-in one-time-PROM (addresses 1000 to FFFFH in the MCU
mode, addresses 0000 to EFFFH in the PROM mode).
When using TMP86PS27FG for evaluation of mask ROM products, the program is written in the program storing area shown in Figure 16-1.
Since the TMP86PS27FG supports several mask ROM sizes, check the difference in memory size and
program storing area between the one-time PROM and the mask ROM to be used.
Page 175
16. OTP operation
16.1 Operating mode
TMP86PS27FG
0000H
1000H
0000H
1000H
0000H
Program
Program
Program
EFFFH
FFFFH
FFFFH
Mask ROM
0000H
FFFFH
Don’t use
PROM mode
MCU mode
(a) ROM size = 64 Kbytes
0000H
0000H
Don’t use
4000H
3000H
4000H
Program
Program
Program
EFFFH
FFFFH
FFFFH
FFFFH
Mask ROM
PROM mode
MCU mode
(b) ROM size = 48 Kbytes
0000H
0000H
Don’t use
0000H
Don’t use
7000H
8000H
8000H
Program
Program
Program
EFFFH
FFFFH
FFFFH
Mask ROM
FFFFH
MCU mode
(c) ROM size = 32 Kbytes
Don’t use
PROM mode
Figure 16-1 Program Memory Area
Note: The area that is not in use should be set data to FFH, or a general-purpose PROM programmer should
be set only in the program memory area to access.
16.1.1.2 Data Memory
TMP86PS27FG has a built-in 1024 bytes Data memory (static RAM).
16.1.1.3 Input/Output Circuiry
1. Control pins
The control pins of the TMP86PS27FG are the same as those of the TMP86CM27FG/
CP27AFG except that the TEST pin does not have a built-in pull-down resistor.
2. I/O ports
The I/O circuitries of the TMP86PS27FG I/O ports are the same as those of the
TMP86CM27FG/CP27AFG.
Page 176
TMP86PS27FG
16.1.2 PROM mode
The PROM mode is set by setting the RESET pin, TEST pin and other pins as shown in Table 16-1 and Figure 16-2. The programming and verification for the internal PROM is acheived by using a general-purpose
PROM programmer with the adaptor socket.
Table 16-1 Pin name in PROM mode
Pin name
(PROM mode)
I/O
Function
Pin name
(MCU mode)
A16
Input
Program memory address input
P70
A15 to A8
Input
Program memory address input
P57 to P50
A7 to A0
Input
Program memory address input
P17 to P10
D7 to D0
Input/Output
Program memory data input/output
P67 to P60
CE
Input
Chip enable signal input
P04
OE
Input
Output enable signal input
P03
PGM
Input
Program mode signal input
P02
VPP
Power supply
+12.75V/5V (Power supply of program)
TEST
VCC
Power supply
+6.25V/5V
VDD
GND
Power supply
0V
VSS
VCC
Setting pin
Fix to "H" level in PROM mode
AVDD,P01,P21
GND
Setting pin
Fix to "L" level in PROM mode
VAREF,P00,P05,P22,P20
RESET
Setting pin
Fix to "L" level in PROM mode
RESET
XIN (CLK)
Input
XIN
XOUT
Output
Set oscillation with resonator
In case of external CLK input, set CLK to XIN
and set XOUT to open.
XOUT
Note 1: The high-speed program mode can be used. The setting is different according to the type of PROM programmer to use, refer to each description of PROM programmer.
TMP86PS27FG does not support the electric signature mode, apply the ROM type of PROM programmer
to TC571000D/AD.
Always set the adapter socket switch to the "N" side when using TOSHIBA’s adaptor socket.
Page 177
16. OTP operation
16.1 Operating mode
TMP86PS27FG
VCC
TMP86PS27FG
VPP (12.5 V/5 V)
TEST
VCC setting pins
P04
CE
P03
OE
P17
P02
PGM
P50
P60
~
A15 ~ A0
~
~
P10
A16
D0 ~ D7
P67
P57
P70
XIN
16 MHz
GND setting pins
XOUT
VSS
GND
Note 1: EPROM adaptor socket (TC571000 • 1M bit EPROM)
Note 2: PROM programmer connection adaptor sockets
BM11701 for TMP86PS27FG
Note 3: Inside pin name for TMP86PS27FG
Outside pin name for EPROM
Figure 16-2 PROM mode setting
Page 178
Refer to pin function
for the other pin setting.
TMP86PS27FG
16.1.2.1 Programming Flowchart (High-speed program writing)
Start
VCC = 6.25 V
VPP = 12.75 V
Address = Start address
N=0
Program 0.1 ms pulse
N=N+1
N = 25?
Yes
No
Error
Address = Address + 1
Verify
OK
No
Last address ?
Yes
VCC = 5 V
VPP = 5 V
Read
all data
Error
Fail
OK
Pass
Figure 16-3 Programming Flowchart
The high-speed programming mode is set by applying Vpp=12.75V (programming voltage) to the Vpp
pin when the Vcc = 6.25 V. After the address and data are fixed, the data in the address is written by
applying 0.1[msec] of low level program pulse to PGM pin. Then verify if the data is written.
If the programmed data is incorrect, another 0.1[msec] pulse is applied to PGM pin. This programming
procedure is repeated until correct data is read from the address (maximum of 25 times).
Subsequently, all data are programmed in all address. When all data were written, verfy all address under
the condition Vcc=Vpp=5V.
Page 179
16. OTP operation
16.1 Operating mode
TMP86PS27FG
16.1.2.2 Program Writing using a General-purpose PROM Programmer
1. Recommended OTP adaptor
BM11701 for TMP86PS27FG
2. Setting of OTP adaptor
Set the switch (SW1) to "N" side.
3. Setting of PROM programmer
a. Set PROM type to TC571000D/AD.
Vpp: 12.75 V (high-speed program writing mode)
b. Data transmission ( or Copy) (Note 1)
The PROM of TMP86PS27FG is located on different address; it depends on operating
mode: MCU mode and PROM mode. When you write the data of ROM for mask ROM products, the data shuold be transferred (or copied ) from the address for MCU mode to that for
PROM mode before writing operation is executed. For the applicable program areas of MCU
mode and PROM mode are different, refer to TMP86PS27FG" Figure 16-1 Program Memory Area ".
Example: In the block transfer (copy) mode, executed as below.
60KB ROM capacity: 01000~0FFFFH → 00000~0EFFFH
48 KB ROM capacity: 04000~0FFFFH → 03000~0EFFFH
32KB ROM capacity: 08000~0FFFFH → 07000~0EFFFH
c. Setting of the program address (Note 1)
Start address: 0000H (When 48KB ROM capacity, atart address is 3000H.
When 32 KB, ROM capacity, start address is 7000H.)
End address: EFFFH
4. Writting
Write and verify according to the above procedure "Setting of PROM programmer".
Note 1: For the setting method, refer to each description of PROM programmer.
Make sure to set the data of address area that is not in use to FFH.
Note 2: When setting MCU to the adaptor or when setting the adaptor to the PROM programmer, set the first
pin of the adaptor and that of PROM programmer socket matched. If the first pin is conversely set,
MCU or adaptor or programmer would be damaged.
Note 3: The TMP86PS27FG does not support the electric signature mode.
If PROM programmer uses the signature, the device would be damaged because of applying voltage
of 12±0.5V to pin 9(A9) of the address. Don’t use the signature.
Page 180
TMP86PS27FG
17. Input/Output Circuitry
17.1 Control Pins
The input/output circuitries of the TMP86PS27FG control pins are shown below.
Control Pin
I/O
Input/Output Circuitry
Remarks
Osc. enable
fc
VDD
XIN
XOUT
Resonator connecting pins
(High frequency)
Rf = 1.2 MΩ (Typ.)
VDD
Rf
Input
Output
RO
RO = 0.5 kΩ (Typ.)
XIN
XOUT
XTEN
Osc. enable
XTIN
XTOUT
Input
Output
fs
VDD
Rf
R
VDD
RO
Resonator connecting pins
(Low frequency)
Rf = 6 MΩ(Typ.)
RO = 220 kΩ (Typ.)
XTIN
XTOUT
VDD
RIN
RESET
Input
R
Address-trap-reset
Hysteresis input
Pull-up resistor
RIN = 220 kΩ (Typ.)
R = 100 Ω(Typ.)
Watchdog timer
System-clock-reset
R
TEST
Input
Page 181
Without pull-down resistor
R = 100 Ω (Typ.)
Fix the TEST pin at low-level
17. Input/Output Circuitry
17.2 Input/Output Ports
TMP86PS27FG
17.2 Input/Output Ports
Port
I/O
Input/Output Circuitry
Initial "High-Z"
Remarks
SEG output
VDD
Data output
P0
I/O
Disable
R
Tri-state output
Hysteresis input
R = 100 Ω (Typ.)
LCD segment output
Pin input
Initial "High-Z"
SEG output
VDD
Data output
P1
Tri-state output
R = 100 Ω (Typ.)
LCD segment output
I/O
Disable
R
Pin input
Initial "High-Z"
P2
I/O
VDD
Sink open drain output
Hysteresis input
R = 100 Ω (Typ.)
Data output
R
Pin input
Initial "High-Z"
VDD
Pch control
Data output
P3
I/O
R
Sink open drain output or
C-MOS output
Hysteresis input
High current output (N-ch)
R = 100 Ω (typ.)
Pin input
Initial "High-Z"
VDD
Pch control
Data output
P4
Sink open drain output or
C-MOS output
Hysteresis input
R = 100 Ω (typ.)
I/O
R
Pin input
Page 182
TMP86PS27FG
Port
I/O
Input/Output Circuitry
Remarks
Initial "High-Z"
SEG output
P5, P7
I/O
Data output
R
Sink open drain output
LCD segment output
R = 100 Ω (typ.)
Pin Input
AIN
Initial "High-Z"
VDD
Data output
P6
I/O
Disable
R
Tri-state I/O
Hysteresis input
AIN input
R = 100 Ω (typ.)
Pin input
Note: The absolute maximum ratings of P0, P1, P5 and P7 port input voltage should be used in −0.3 to VDD + 0.3 volts.
Page 183
17. Input/Output Circuitry
17.2 Input/Output Ports
TMP86PS27FG
Page 184
TMP86PS27FG
18. Electrical Characteristics
18.1 Absolute Maximum Ratings
The absolute maximum ratings are rated values, which must not be exceeded during operation, even for an instant.
Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down
or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
(VSS = 0 V)
Parameter
Symbol
Pins
Ratings
−0.3 to 6.5
Supply voltage
VDD
Program voltage
VPP
Input voltage
VIN
−0.3 to VDD + 0.3
VOUT
−0.3 to VDD + 0.3
Output voltage
Output current (Per 1 pin)
Output current (Total)
Unit
TEST/VPP
−0.3 to 13.0
IOUT1
P0, P1, P3, P4, P6 port
−1.8
IOUT2
P0, P1, P2, P4, P5, P6, P7 port
3.2
IOUT3
P3 port
30
Σ IOUT1
P0, P1, P3, P4, P6 port
−30
Σ IOUT2
P0, P1, P2, P4, P5, P6, P7 port
60
Σ IOUT3
P3 port
80
Power dissipation [Topr = 85°C]
PD
250
Soldering temperature (Time)
Tsld
260 (10 s)
Storage temperature
Tstg
−55 to 125
Operating temperature
Topr
−40 to 85
Page 185
V
mA
mW
°C
18. Electrical Characteristics
18.2 Recommended Operating Condition
TMP86PS27FG
18.2 Recommended Operating Condition
The recommended operating conditions for a device are operating conditions under which it can be guaranteed that
the device will operate as specified. If the device is used under operating conditions other than the recommended
operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may
occur. Thus, when designing products which include this device, ensure that the recommended operating conditions
for the device are always adhered to.
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
fc = 16 MHz
Supply voltage
fc = 8 MHz
VDD
fs =
32.768 kHz
NORMAL1, 2 mode
IDLE0, 1, 2 mode
Input high level
Except hysteresis input
VIH2
Hysteresis input
IDLE0, 1, 2 mode
SLOW mode
Input low level
VIL1
Except hysteresis input
VIL2
Hysteresis input
Clock frequency
4.5
2.7
fc
XIN, XOUT
fs
XTIN, XTOUT
VDD ≥ 4.5 V
VDD ≥ 4.5 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
V
VDD × 0.70
VDD × 0.75
VDD
VDD × 0.90
VDD × 0.30
0
VDD × 0.25
VDD × 0.10
1.0
30.0
Page 186
5.5
2.0
VDD < 4.5 V
VIL3
Unit
SLEEP mode
VDD < 4.5 V
VIH3
Max
NORMAL1, 2 mode
STOP mode
VIH1
Min
16.0
8.0
34.0
MHz
kHz
TMP86PS27FG
18.3 DC Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
Min
Typ.
Max
Unit
–
0.9
–
V
–
–
±2
µA
100
220
450
kΩ
VHS
Hysteresis input
IIN1
TEST
IIN2
Sink open drain, Tri-state
port
IIN3
RESET, STOP
Input resistance
RIN
RESET pull-up
Oscilation feedback
resistance
Rfx
XIN-XOUT
–
1.2
–
Rfxt
XTIN-XTOUT
–
6
–
ILO1
Hysteresis voltage
Input current
VDD = 5.5 V, VIN = 5.5 V/0 V
Sink open drain port
VDD = 5.5 V, VOUT = 5.5 V
–
–
2
ILO2
Tri-state port
VDD = 5.5 V, VOUT = 5.5 V/0 V
–
–
±2
Output high voltage
VOH
Tri-state port
VDD = 4.5 V, VOH = -0.7 mA
4.1
–
–
Output low voltage
VOL
VDD = 4.5 V, VOL = 1.6 mA
–
–
0.4
Output low current
IOL1
VDD = 4.5 V, VOL = 0.4 V
–
1.6
–
Output low current
IOL2
VDD = 4.5 V, VOL = 1.0 V
–
20
–
VDD = 5.5 V
–
9.5
12
–
7
8.5
–
12
20
–
8
13
–
6
12
–
0.5
10
Output leakage current
Except XOUT, XTOUT, P3
port
Except XOUT, XTOUT, P3
port
High current port
(P3 port)
VIN = 5.3/0.2 V
Supply current in
IDLE0, 1, 2 mode
fc = 16 MHz
fs = 32.768 kHz
Supply current in
SLEEP1 mode
IDD
Supply current in
SLEEP0 mode
Supply current in
STOP mode
µA
V
mA
Supply current in
NORMAL1, 2 mode
Supply current in
SLOW1 mode
MΩ
mA
VDD = 3.0 V
VIN = 2.8 V/0.2 V
fs = 32.768 kHz
VDD = 5.5 V
VIN = 5.3 V/0.2 V
µA
Note 1: Typical values show those at Topr = 25°C, VDD = 5 V
Note 2: Input current (IIN1, IIN3); The current through pull-up or pull-down resistor is not included.
Note 3: IDD does not include IREF current.
Note 4: The supply currents in SLOW2 and SLEEP2 modes are equivalent to those in IDLE0, IDLE1, and IDLE2 modes.
Page 187
18. Electrical Characteristics
18.4 AD Conversion Characteristics
TMP86PS27FG
18.4 AD Conversion Characteristics
(VSS = 0.0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Analog reference voltage
VAREF
Power supply voltage of analog control circuit
AVDD
Condition
Min
Typ.
Max
AVDD − 1.0
–
AVDD
VDD
V
∆VAREF
3.5
–
–
Analog input voltage
VAIN
VSS
–
VAREF
Power supply current of analog
reference voltage
IREF
–
0.6
1.0
–
–
±2
–
–
±2
–
–
±2
–
–
±4
Analog reference voltage range (Note 4)
VDD = AVDD = VAREF = 5.5 V
VSS = AVSS = 0.0 V
Non linearity error
VDD = AVDD = 5.0 V
Zero point error
VSS = AVSS = 0.0 V
Full scale error
VAREF = 5.0 V
Total error
Unit
mA
LSB
(VSS = 0.0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Analog reference voltage
VAREF
Power supply voltage of analog control circuit
AVDD
Condition
Min
Typ.
Max
AVDD − 1.0
–
AVDD
VDD
V
∆VAREF
2.5
–
–
Analog input voltage
VAIN
VSS
–
VAREF
Power supply current of analog
reference voltage
IREF
–
0.5
0.8
–
–
±2
–
–
±2
–
–
±2
–
–
±4
Analog reference voltage range (Note 4)
VDD = AVDD = VAREF = 4.5 V
VSS = AVSS = 0.0 V
Non linearity error
Zero point error
Full scale error
VDD = AVDD = 2.7 V
VSS = AVSS = 0.0 V
VAREF = 2.7 V
Total error
Unit
mA
LSB
Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line.
Note 2: Conversion time is different in recommended value by power supply voltage.
About conversion time, please refer to “Register Configuration”.
Note 3: Please use input voltage to AIN input Pin in limit of VAREF − VSS.
When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion
value.
Note 4: Analog reference voltage range: ∆VAREF = VAREF − VSS
Note 5: When AD converter is not used, fix the AVDD pin on the VDD level.
Page 188
TMP86PS27FG
18.5 AC Characteristics
(VSS = 0 V, VDD = 4.5 to 5.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.25
–
4
117.6
–
133.3
For external clock operation
(XIN input)
fc = 16 MHz
–
31.25
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
NORMAL1, 2 mode
Machine cycle time
tcy
IDLE0, 1, 2 mode
SLOW1, 2 mode
SLEEP0, 1, 2 mode
High level clock pulse width
tWCH
Low level clock pulse width
tWCL
High level clock pulse width
tWSH
Low level clock pulse width
tWSL
Unit
µs
(VSS = 0 V, VDD = 2.7 to 4.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
NORMAL1, 2 mode
Machine cycle time
tcy
IDLE0, 1, 2 mode
SLOW1, 2 mode
tWCH
Low level clock pulse width
tWCL
High level clock pulse width
tWSH
Low level clock pulse width
tWSL
Typ.
Max
0.5
–
4
Unit
µs
117.6
–
133.3
For external clock operation
(XIN input)
fc = 8 MHz
–
62.5
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
SLEEP0, 1, 2 mode
High level clock pulse width
Min
Page 189
18. Electrical Characteristics
18.6 DC Characteristics, AC Characteristics (PROM mode)
TMP86PS27FG
18.6 DC Characteristics, AC Characteristics (PROM mode)
18.6.1 Read operation in PROM mode
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Min
Typ.
Max
VIH4
2.2
–
VCC
Low level input voltage (TTL)
VIL4
0
–
0.8
Power supply
VCC
Program supply of program
VPP
4.75
5.0
5.25
Address access time
tACC
–
1.5tcyc + 300
–
High level input voltage (TTL)
Condition
VCC = 5.0 ± 0.25 V
Note: tcyc = 250 ns at fCLK = 16 MHz
A16 to A0
CE
OE
PGM
tACC
D7 to D0
High-Z
Data output
Page 190
Unit
V
ns
TMP86PS27FG
18.6.2 Program operation (High-speed)
(Topr = 25 ± 5 °C)
Parameter
Symbol
Typ.
Max
2.2
–
VCC
0
–
0.8
VCC
6.0
6.25
6.5
Program supply of program
VPP
12.5
12.75
13.0
Pulse width of initializing program
tPW
0.095
0.1
0.105
High level input voltage (TTL)
VIH4
Low level input voltage (TTL)
VIL4
Power supply
Condition
Min
VCC = 6.0 V
Unit
V
ms
High-speed program writing
A16 to A0
CE
OE
D7 to D0
Unknown
Input data
Output data
tPW
PGM
VPP
Write
Verify
Note 1: The power supply of VPP (12.75 V) must be set power-on at the same time or the later time for a power supply of VCC and must be clear power-on at the same time or early time for a power supply of VCC.
Note 2: The pull-up/pull-down device on the condition of VPP = 12.75 V ± 0.25 V causes a damage for the device.
Do not pull-up/pull-down at programming.
Note 3: Use the recommended adapter and mode.
Using other than the above condition may cause the trouble of the writting.
Page 191
18. Electrical Characteristics
18.7 Recommended Oscillating Conditions
TMP86PS27FG
18.7 Recommended Oscillating Conditions
XIN
C1
XOUT
XTIN
C2
(1) High-frequency Oscillation
XTOUT
C1
C2
(2) Low-frequency Oscillation
Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these
factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the
device will actually be mounted.
Note 2: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by
Murata Manufacturing Co., Ltd.
For details, please visit the website of Murata at the following URL:
http://www.murata.co.jp
18.8 Handling Precaution
- The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown
below.
1. When using the Sn-37Pb solder bath
Solder bath temperature = 230 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
2. When using the Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature = 245 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
Note: The pass criteron of the above test is as follows:
Solderability rate until forming ≥ 95 %
- When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we
recommend electrically shielding the package in order to maintain normal operating condition.
Page 192
TMP86PS27FG
19. Package Dimensions
P-QFP80-1420-0.80B
Unit: mm
Page 193
19. Package Dimensions
TMP86PS27FG
Page 194
This is a technical document that describes the operating functions and electrical specifications of the 8-bit
microcontroller series TLCS-870/C (LSI).
Toshiba provides a variety of development tools and basic software to enable efficient software
development.
These development tools have specifications that support advances in microcomputer hardware (LSI) and
can be used extensively. Both the hardware and software are supported continuously with version updates.
The recent advances in CMOS LSI production technology have been phenomenal and microcomputer
systems for LSI design are constantly being improved. The products described in this document may also
be revised in the future. Be sure to check the latest specifications before using.
Toshiba is developing highly integrated, high-performance microcomputers using advanced MOS
production technology and especially well proven CMOS technology.
We are prepared to meet the requests for custom packaging for a variety of application areas.
We are confident that our products can satisfy your application needs now and in the future.